HOLT ADK-2130mPCIe, Technical Manual

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Holt Integrated Circuits
23
Table 1 – Memory mapped I/O Device control signals
Device Signal Source Function Address Software
read/write
Use
BC_TRIG FPGA->Device BC trigger pulse 0x8000 Read/Write Set High then low (1/0)
NMR FPGA Resets Device 0x8002 Read/Write Set Low then High
TEST FPGA Test pin state 0x8003 Read/Write Set High for Test mode.
See 6130 data sheet
for test mode.
BCENA FPGA Enables BC 0x8004 Read/Write Set high to enable BC
MTRUN FPGA -> Device Enables MT 0x8009 Read/Write Set high to enable MT
RT1ENA FPGA -> Device Enables RT1 0x800A Read/Write Set High to Enable RT1
RT2ENA FPGA -> Device Enables RT2 0x800B Read/Write Set High to Enable RT2
TXINHA/TXINHB J4 Connector Inhibits bus 0x800C Read only Hard-wired to J4
INPUT_CONTROL FPGA Set Demo mode
or User mode 0x800E Read/Write 0=Demo mode
(default)
1=User mode
SPARE_INPUT J4 Connector Spare input 0x800E Read only Readable Spare input.
MTPKTRDY Device -> FPGA Monitor Packet
ready device
output
0x800F Read only Optional read
ACTIVE Device -> FPGA Active state 0x8010 Read only Optional read
RT1MC8 Device->FPGA RT1 Mode Code 8 0x8011 Read only Optional read
RT2MC8 Device->FPGA RT2 Mode Code 8 0x8012 Read only Optional read
READY Device->FPGA Indicates Ready
state 0x8013 Read only Optional read. Used by
demo software to
determine when
devices are ready after
MR.