Circuit Descriptions
6-14
6-5 DVD Data Processor
6-5-1 Outline
DIC1(KS1453) performs Sync detection, EFM demodulation and error correction and Spindle motor control (CLV
control) after inputting sliced EFM signal of RF signal at disc playback and EFM read clock (PLCK) signal
generated from PLL. Outputs data which converted to the last audio and video from A/V decoder (ZIC1). KS1453
uses external memory(4M DRAM) as buffer as well as for error correction and carries out Variable Bit Rate transfer
function. VBR function uses the external buffer as buffer to absorb the difference of transfer rate occurring because
the transfer rate of disc playback is faster than data transfer rate demanded by A/V decoder(Video/Audio Signal
Process Chip).
In case of general disc refresh, the memory is almost filled up periodically. It is because Write rate to memory after
disc playback and signal process is faster than Read of A/V decoder. When the memory is filled, this status is
reported by interrupt to main micom, which controls the servo to kick back the pick-up to the previous track after
memorizing the last data read from disc until now. It takes some times to jump to the previous track and return to
the original(jump location) again. The memory will have an empty space because A/V decoder reads out data of
memory.
When the memory has an empty space, where data can be processed and written and the pick-up correctly gets to
the original location(before kick back location) again, it reads data again avoids the interrupt of data read
previously. The basic operation repeats to perform as described above.
6-5-2 Block Diagram
Fig. 6-19
MAD[7..0]
HA[10..8]
*WR(89)
HA0
INT7(ZIRQZD)
INT8(/DVDINT)
*RD(88)
MIC1 TMP95C265F
HDATA[7..0]
HADDR[2..0]
/CS
/RD
/WR
/INT
ZWAIT
DVD-D[7..0]
VSTROBE
REQUEST
DACK
*ERR
zIC1
(ZiVA4.1)
173
172
171
174
159
CLOCK 27MHz
CLOCK 33.8688MHz
CLOCK 27MHz
14
95
69
70
58
71
SDATA[7..0]
CSTROBE
DATREQ
DATACK
DTER
O
E
W
E
C
A
S
R
A
S
[
[D
1
5.
.
0
[
[A
8.
.
0
[
[
D
D
1
5.
.
0
[
[
D
A
D
R
8.
.
0
Z
R
A
S
Z
C
A
S
Z
W
E
O
Z
O
E
O
MDAT[7:0]
MRZA(3)
ZCS(2)
MWR(128)
MRD(127)
ZIRQZD(126)
1WAIT
EFMI
PLCK
116
104
109
110
MDP
MDS
EFM
PLCK
DIC1
(KS1453)
DIC2 (KM416C254)
Summary of Contents for DV-P303U
Page 29: ...Reference Information 2 22 MEMO ...
Page 31: ...Product Specification 3 2 MEMO ...
Page 49: ...5 14 Disassembly and Reaasembly MEMO ...
Page 69: ...Circuit Descriptions 6 20 MEMO ...
Page 79: ...Troubleshooting 7 10 MEMO ...
Page 80: ...8 1 8 Exploded View 8 1 Cabinet Assembly 8 2 Deck Assembly Page 8 2 8 3 ...
Page 82: ...8 3 Exploded Views 8 2 Deck Assembly 107 906 ...
Page 83: ...Exploded Views 8 4 MEMO ...
Page 85: ...9 2 Replacement Parts List MEMO ...
Page 87: ...PCB Diagrams 1 11 1 Main COMPONENT SOLDER SIDE ...
Page 88: ...PCB Diagrams 2 11 2 Jack ...
Page 89: ...PCB Diagrams 3 11 3 Key 11 4 Deck ...
Page 90: ...12 1 12 Wiring Diagram ...
Page 91: ...Wiring Diagram 12 2 MEMO ...
Page 93: ...Schematic Diagrams 13 2 13 1 Power ...
Page 94: ...Schematic Diagrams 13 3 13 2 Main Micom ...
Page 95: ...Schematic Diagrams 13 4 13 3 Servo ...
Page 96: ...Schematic Diagrams 13 5 13 4 Video ...
Page 97: ...Schematic Diagrams 13 6 13 5 Audio ...
Page 98: ...Schematic Diagrams 13 7 13 6 RF ...
Page 99: ...Schematic Diagrams 13 8 13 7 ZiVA ...
Page 100: ...Schematic Diagrams 13 9 13 8 DSP ...
Page 101: ...Schematic Diagrams 13 10 13 9 Front Micom VFD Display ...
Page 102: ...Schematic Diagrams 13 11 13 10 Key ...
Page 103: ...Schematic Diagrams 13 12 13 11 Deck ...
Page 104: ...Schematic Diagrams 13 13 13 12 Remote Control ...
Page 105: ...Schematic Diagrams 13 14 MEMO ...
