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Deskstar 7K400 Hard Disk Drive Specification

6.6.2 Read DRQ interval time

For read sectors and read multiple operations the interval from the end of negation of the DRQ bit until setting of
the next DRQ bit is as follows:

•

In the event that a host reads the status register only before the sector or block transfer DRQ interval, the
DRQ interval 4.2

•

In the event that a host reads the status register after or both before and after the sector or block transfer, the
DRQ interval is 11.5

Summary of Contents for Deskstar 7K400

Page 1: ...Hard Disk Drive Specification Deskstar 7K400 3 5 inch Ultra ATA 133 hard disk drive 3 5 inch Serial ATA hard disk drive Models HDS724040KLAT80 HDS724040KLSA80 Version 1 7 12 September 2006 ...

Page 2: ......

Page 3: ...Hard Disk Drive Specification Deskstar 7K400 3 5 inch Ultra ATA 133 hard disk drive 3 5 inch Ultra Serial ATA hard disk drive Models HDS724040KLAT80 HDS724040KLSA80 Version 1 7 12 September 2006 ...

Page 4: ...nges are periodically made to the information herein these changes will be incorporated in new editions of the publication Hitachi may make improvements or changes in any products or programs described in this publication at any time It is possible that this publication may contain reference to or information about Hitachi products machines and programs programming or services that are not announc...

Page 5: ...mmand overhead 14 4 5 2 Mechanical positioning 15 4 5 3 Drive ready time 16 4 5 4 Data transfer speed 17 4 5 5 Throughput 18 4 5 6 Operating modes 19 5 0 Defect flagging strategy 21 6 0 Specification 23 6 1 Electrical Interface 23 6 1 1 Connector location 23 6 1 2 DC power connector 24 6 1 3 AT signal connector 24 6 2 Signal definitions PATA model 25 6 3 Signal descriptions 26 6 4 Interface logic ...

Page 6: ...supply current typical 51 7 3 3 Power supply generated ripple at drive power connector 52 7 4 Reliability 53 7 4 1 Data integrity 53 7 4 2 Cable noise interference 53 7 4 3 Start stop cycles 53 7 4 4 Preventive maintenance 53 7 4 5 Data reliability 53 7 4 6 Required power off sequence 53 7 5 Mechanical specifications 54 7 5 1 Physical dimensions and weight 54 7 5 2 Mounting hole locations 55 7 5 3...

Page 7: ...70 9 9 Device Head Register 70 9 10 Error Register 71 9 11 Features Register 71 9 12 Sector Count Register 71 9 13 Sector Number Register 72 9 14 Status Register 72 10 0 General operation 75 10 1 Reset response 75 10 2 Register initialization 76 10 3 Diagnostic and Reset considerations 77 10 4 Sector Addressing Mode 78 10 4 1 Logical CHS addressing mode 78 10 4 2 LBA addressing mode 78 10 5 Overla...

Page 8: ...Disable Address Offset Mode 98 10 16 2 Identify Device Data 98 10 16 3 Exceptions in Address Offset Mode 98 10 17 48 bit Address Feature Set 99 10 18 Streaming Feature Set 99 10 18 1 Streaming commands 100 10 18 2 Urgent bit 100 10 18 3 Flush to Disk bit 100 10 18 4 Not Sequential bit 100 10 18 5 Read Continuous bit 101 10 18 6 Write Continuous bit 101 10 18 7 Handle Streaming Error bit 101 10 18 ...

Page 9: ...RT Error Log 153 12 20 3 Extended Self test log sector 155 12 20 4 Read Stream Error log 156 12 20 5 Write Stream Error log 157 12 20 6 Streaming Performance log 158 12 21 Read Long 22h 23h 160 12 22 Read Multiple C4h 162 12 23 Read Multiple Ext 29h 164 12 24 Read Native Max ADDRESS F8h 166 12 25 Read Native Max Address Ext 27h 167 12 26 Read Sectors 20h 21h 168 12 27 Read Sector s Ext 24h 170 12 ...

Page 10: ...evice Attribute Data Structure 211 12 46 3 Device Attribute Thresholds data structure 214 12 46 4 S M A R T Log Directory 216 12 46 5 S M A R T summary error log sector 216 12 46 6 Self test log data structure 218 12 46 7 Selective self test log data structure 219 12 46 8 Error reporting 220 12 47 Standby E2h 96h 221 12 48 Standby Immediate E0h 94h 222 12 49 Write Buffer E8h 223 12 50 Write DMA CA...

Page 11: ...able 24 Multiword DMA cycle timing chart 34 Table 25 Multiword DMA cycle timings 34 Table 26 Ultra DMA cycle timing chart Initiating Read 35 Table 27 Ultra DMA cycle timings Initiating Read 35 Table 28 Ultra DMA cycle timing chart Host pausing Read 36 Table 29 Ultra DMA cycle timings Host pausing Read 36 Table 30 Ultra DMA cycle timing chart Host terminating Read 37 Table 31 Ultra DMA cycle timing...

Page 12: ...atus Register 72 Table 65 Reset response table 75 Table 66 Default Register Values 76 Table 67 Diagnostic codes 76 Table 68 Reset error register values 77 Table 69 Power conditions 81 Table 70 Command table for device lock operation 88 Table 71 Seek overlap 91 Table 72 Enable Disable Address Offset Mode 98 Table 73 Command Set 1 of 2 109 Table 74 Command Set 2 of 2 110 Table 75 Command Set subcomm...

Page 13: ...mand data structure 154 Table 111 Error data structure 154 Table 112 Extended Self test log descriptor entry 156 Table 113 Read Stream Error Log 156 Table 114 Stream Error Log entry 157 Table 115 Write Stream Error Log 158 Table 116 Streaming Performance Parameters log 158 Table 117 Sector Time Array Entry Linearly Interpolated 159 Table 118 Position Array Entry Linearly Interpolated 159 Table 119...

Page 14: ...Attribute Data Structure 211 Table 156 Device Attribute Thresholds Data Structure 215 Table 157 Individual Threshold Data Structure 215 Table 158 S M A R T Log Directory 216 Table 159 S M A R T summary error log sector 216 Table 160 Error log data structure 217 Table 161 Command data structure 217 Table 162 Error data structure 217 Table 163 Self test log data structure 218 Table 164 Selective sel...

Page 15: ...ions Abbreviation Meaning A Ampere AC alternating current AT Advanced Technology ATA Advanced Technology Attachment BIOS Basic Input Output System C Celsius CSA Canadian Standards Association C UL Canadian Underwriters Laboratory Cyl cylinder DC Direct Current DFT Drive Fitness Test DMA Direct Memory Access ECC error correction code EEC European Economic Community EMC electromagnetic compatibility...

Page 16: ... LBA logical block addressing Lw unit of A weighted sound power m meter max maximum MB 1 000 000 bytes Mbps 1 000 000 bits per second MHz megahertz MLC Machine Level Control mm millimeter ms millisecond us ms microsecond O Output OD Open Drain Programmed Input Output POH power on hours Pop population P N part number p p peak to peak PSD power spectral density RES radiated electromagnetic susceptib...

Page 17: ...E Verband Deutscher Electrotechniker W watt 3 state transistor transistor tristate logic 1 4 Caution Do not apply force to the top cover Do not cover the breathing hole on the top cover Do not touch the interface connector pins or the surface of the printed circuit board This drive can be damaged by electrostatic discharge ESD Any damages incurred to the drive after its removal from the shipping p...

Page 18: ...Deskstar 7K400 Hard Disk Drive Specification 4 ...

Page 19: ...71 KB is used for firmware Ring buffer implementation Write Cache Queued feature support Advanced ECC On The Fly EOF Automatic Error Recovery procedures for read and write commands Self Diagnostics on Power on and resident diagnostics PIO Register Data Transfer Mode 4 16 6 MB s DMA Data Transfer Multiword mode Mode 2 16 6 MB s Ultra DMA Mode 6 133 MB s Serial ATA Data Transfer1 5Gbps CHS and LBA m...

Page 20: ...Deskstar 7K400 Hard Disk Drive Specification 6 ...

Page 21: ...Deskstar 7K400 Hard Disk Drive specification 7 Part 1 Functional specification ...

Page 22: ...Deskstar 7K400 Hard Disk Drive Specification 8 ...

Page 23: ...itions of the servo and takes corresponding action if an error occurs Monitors various timers such as head settle and servo failure Performs self checkout diagnostics 3 2 Head disk assembly The head disk assembly HDA is assembled in a clean room environment and contains the disks and actuator assembly Air is constantly circulated and filtered when the drive is operational Venting of the HDA is acc...

Page 24: ...Deskstar 7K400 Hard Disk Drive Specification 10 ...

Page 25: ... system interface The logical layout to Physical layout that is the actual Head and Sectors translation is done automatically in the drive The default setting can be obtained by issuing an IDENTIFY DEVICE command Table 1 Formatted capacity HDS724040KLAT20 HDS724040KLSA80 Physical Layout Label capacity GB 400 Bytes per sector 512 Sectors per track 567 1170 Number of heads 10 Number of disks 5 Data ...

Page 26: ... the maximum performance to users Table 2 Mechanical positioning performance Data transfer rates Mbps 757 Interface transfer rates Mb s 133 Data buffer size1 KB 8192 Rotational speed RPM 7200 Number of buffer segments read up to 128 Number of buffer segments write up to 63 Recording density max Kbpi 686 Track density TPI 90 Areal density max Gbits in2 62 Number of data bands 30 Table 3 World Wide ...

Page 27: ...eassigned data Spare cylinder The spare cylinder is used by Hitachi Global Storage Technologies manufacturing and includes data sent from a defect loca tion Table 4 Cylinder allocation Data Zone Physical Cylinders Blk Trk 0 2 783 1170 1 4 500 1134 2 4 800 1080 3 4 900 1080 4 4800 1012 5 4900 1012 6 4900 990 7 4300 945 8 4200 918 9 3900 900 10 3900 877 11 3100 877 12 3300 855 13 2700 855 14 3200 81...

Page 28: ...ends on the system and the application 4 5 1 Command overhead Command overhead is defined as the time required from the time the command is written into the command register by a host to the assertion of DRQ for the first data byte of a READ command when the requested data is not in the buffer excluding Physical seek time and Latency The table below gives average command overhead Table 5 Command o...

Page 29: ...blems The average seek time is mea sured as the weighted average of all possible seek combinations max Σ m10 n Tnin Tnout n 1 Weighted Average max 1 max where max Maximum seek length n Seek length 1 to max Tnin Inward measured seek time for an n track seek Tnout Outward measured seek time for an n track seek 4 5 2 2 Full stroke seek time without command overhead including settling Full stroke seek...

Page 30: ...le track seek is measured as the average of one 1 single track seek from every track in both directions inward and out ward 4 5 2 6 Average latency 4 5 3 Drive ready time Ready The condition in which the drive is able to perform a media access command for example read write immediately Power onThis includes the time required for the internal self diagnostics Note Max Power On to ready time is the ...

Page 31: ...ollowing formula Sustained Transfer Rate A B C D where A 512 number of data sectors per cylinder B number of Surfaces per cylinder 1 head switch time C cylinder change time D number of surfaces time for one revolution Instantaneous buffer host transfer rate Mbyte s defines the maximum data transfer rate on the AT Bus It also depends on the speed of the host The method of measurement is given in 4 ...

Page 32: ...host system responds instantaneously and host data transfer is faster than sustained data rate 4 5 5 2 Random access The following table illustrates simple sequential access for three disk enclosure Table 13 Random Access performance The above table gives the time required to execute a total of 1000h read commands which access a single random LBA Typi cal and Max values are given by 105 and 110 of...

Page 33: ...ration mode Write Write operation mode Read Read operation mode Unload Idle Spindle rotation at 7200 RPM with heads unloaded Idle Spindle motor and servo system are working normally Commands can be received and pro cessed immediately Standby Actuator is unloaded and spindle motor is stopped Commands can be received immediately Sleep Actuator is unloaded and spindle motor is stopped Only soft reset...

Page 34: ...Deskstar 7K400 Hard Disk Drive Specification 20 ...

Page 35: ...physical locations is calculated by an internally maintained table Shipped format Data areas are optimally used No extra sector is wasted as a spare throughout user data areas All pushes generated by defects are absorbed by the spare tracks of the inner zone Table 16 Plist physical format Defects are skipped without any constraint such as track or cylinder boundary N N 1 N 2 N 3 defect defect skip...

Page 36: ...Deskstar 7K400 Hard Disk Drive Specification 22 ...

Page 37: ...tar 7K400 Hard Disk Drive Specification 23 6 0 Specification 6 1 Electrical Interface 6 1 1 Connector location Refer to the following illustration to see the location of the connectors PATA Model SATA M odel ...

Page 38: ... using AMP pins part number 350078 4 strip part number 61173 4 loose piece or their equivalents Pin assignments are shown in the figure below 6 1 3 AT signal connector The PATA signal connector is a 40 pin connector The SATA signal connector is a 8 pin connector The power connector is a 15 pin connector 4 3 2 1 Pin Voltage 1 12 V 2 GND 3 GND 4 5V ...

Page 39: ... DMA burst Table 17 Signal definitions PIN SIGNAL I O Type PIN SIGNAL I O Type 01 RESET I TTL 02 GND 03 DD7 I O 3 state 04 DD08 I O 3 state 05 DD6 I O 3 state 06 DD09 I O 3 state 07 DD5 I O 3 state 08 DD10 I O 3 state 09 DD4 I O 3 state 10 DD11 I O 3 state 11 DD3 I O 3 state 12 DD12 I O 3 state 13 DD2 I O 3 state 14 DD13 I O 3 state 15 DD1 I O 3 state 16 DD14 I O 3 state 17 DD0 I O 3 state 18 DD15...

Page 40: ...lected See Table 42 I O address map on page 43 RESET This line is used to reset the drive It shall be kept at a Low logic state during power up and kept High thereafter DIOW The rising edge of this signal holds data from the data bus to a register or data register of the drive DIOR When this signal is low it enables data from a register or data register of the drive onto the data bus The data on t...

Page 41: ...ndicate that it is no longer busy and is able to provide status Following the receipt of a valid Execute Drive Diagnostics command device 1 shall negate PDIAG within 1 ms to indicate to device 0 that it is busy and has not yet passed its drive diagnostics If device 1 is present then device 0 shall wait up to 6 seconds from the receipt of a valid Execute Drive Diagnostics command for drive 1 to ass...

Page 42: ...ising and falling edge of HSTROBE latch the data from DD 15 0 into the device The host may stop toggling HSTROBE to pause an Ultra DMA data out transfer STOP Ultra DMA This signal is used only for Ultra DMA data transfers between host and drive The STOP signal shall be asserted by the host prior to initiation of an Ultra DMA burst A STOP shall be negated by the host before data is transferred in a...

Page 43: ...S2 A Differential signal A from Phy RX Input S3 A RX Input Signal S4 Gnd 2nd mate Gnd S5 B Differential signal B from Phy TX Output S6 B TX Output S7 Gnd 2nd mate Gnd Key and spacing separate signal and power segments P1 V33 3 3V power 3 3V P2 V33 3 3V power 3 3V P3 V33 3 3V power pre charge 2nd Mate 3 3V P4 Gnd 1st mate Gnd P5 Gnd 2nd mate Gnd P6 Gnd 2nd mate Gnd P7 V5 5V power pre charge 2nd Mat...

Page 44: ...ected to the serial ATA cable The following standard shall be referenced about signal specifications Serial ATA High Speed Serialized AT Attachment Revision 1 0a 7 January 2003 6 4 2 Out of band signaling SATA model Table 20 The timing of COMRESET COMINT and COMWAKE Table 21 Parameter descriptions PARAMETER DESCRIPTION Nominal ns t1 ALINE primitives 106 7 t2 Spacing 320 t3 ALIGN primitives 106 7 t...

Page 45: ... Disk Drive Specification 31 6 5 Signal timings PATA model 6 5 1 Reset timings Table 22 System reset timing chart PARAMETER DESCRIPTION Min µs Max µs t10 RESET low width 25 t14 RESET high to not BUSY 31 t10 t14 RESET BUSY ...

Page 46: ...til set ting of the next DRQ bit PARAMETER DESCRIPTION MIN ns MAX ns t0 Cycle time 120 t1 Address valid to DIOR DIOW setup 25 t2 DIOR DIOW pulse width 70 t2i DIOR DIOW recovery time 25 t3 DIOW data setup 20 t4 DIOW data hold 10 t5 DIOR data setup 20 t6 DIOR data hold 5 t9 DIOR DIOW to address valid hold 10 tA IORDY setup width 35 tB IORDY pulse width 1250 IOCS16 t9 t0 t2 t2i t3 t4 t5 t8 t7 t1 tB R...

Page 47: ...end of negation of the DRQ bit until setting of the next DRQ bit is as follows In the event that a host reads the status register only before the sector or block transfer DRQ interval the DRQ interval 4 2 µs In the event that a host reads the status register after or both before and after the sector or block transfer the DRQ interval is 11 5 µs ...

Page 48: ...0 Cycle time 120 tD DIOR DIOW asserted pulse width 70 tE DIOR data access 50 tF DIOR data hold 5 tG DIOR DIOW data setup 20 tH DIOW data hold 10 tI DMACK to DIOR DIOW setup 0 tJ DIOR DIOW to DMACK hold 5 tKR tKW DIOR DIOW negated pulse width 25 tLR tLW DIOR DIOW to DMARQ delay 35 tM CS 1 0 valid to DIOR DIOW 25 tN CS 1 0 10 tZ DMACK to read data released 25 WRITE DATA READ DATA DMACK DMARQ DIOR DI...

Page 49: ... 70 20 55 20 55 20 50 tZIORDY Minimum time before driv ing IORDY 0 0 0 0 0 0 tFS First DSTROBE time 0 230 0 200 0 170 0 130 0 120 90 tCYC Cycle time 112 73 54 39 25 17 t2CYC Two cycle time 230 154 115 86 57 38 tAZ Maximum time allowed for output drivers to release 10 10 10 10 10 10 tZAD Drivers to assert 0 0 0 0 0 0 tDS Data setup time at host 15 10 7 7 5 4 8 tDH Data hold time at host 5 5 5 5 5 4...

Page 50: ...hould be ready to receive two more data words after HDMARDY is negated Table 29 Ultra DMA cycle timings Host pausing Read PARAMETER DESCRIPTION all values in ns MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX tSR DSTROBE to HDMARDY time 50 30 20 tRFS HDMARDY to final DSTROBE time 75 70 60 60 60 50 DSTROBE HDMARDY DMACK DMARQ tSR STOP tRFS ...

Page 51: ...tLI Limited interlock time 0 150 0 150 0 150 0 100 0 100 0 75 tAZ Maximum time allowed for output drivers to release 10 10 10 10 10 10 tZAH Minimum delay time required for output 20 20 20 20 20 20 tMLI Interlock time with minimum 20 20 20 20 20 20 tCS CRC word setup time at device 15 10 7 7 5 5 tCH CRC word hold time at device 5 5 5 5 5 5 tACK Hold time for DMACK 20 20 20 20 20 20 tIORDYZ Maximum ...

Page 52: ...ed interlock time 0 150 0 150 0 150 0 100 0 100 0 75 tAZ Maximum time allowed for output drivers to release 10 10 10 10 10 10 tZAH Maximum delay time required for output 20 20 20 20 20 20 tMLI Interlock time with minimum 20 20 20 20 20 20 tCS CRC word setup time at device 15 10 7 7 5 5 tCH CRC word hold time at device 5 5 5 5 5 5 tACK Hold time for DMACK 20 20 20 20 20 20 tIORDYZ Maximum time befo...

Page 53: ... Setup time for DMACK 20 20 20 20 20 20 tENV Envelope time 20 70 20 70 20 70 20 55 20 55 20 55 tZIORDY Minimum time before driving IORDY 0 0 0 0 0 0 tLI Limited interlock time 0 150 0 150 0 150 0 100 0 100 0 75 tCYC Cycle time 112 73 54 39 25 16 8 t2CYC Two cycle time 230 154 115 86 57 38 tDS Data setup time at device 15 10 7 7 5 4 tDH Data Hold time at device 5 5 5 5 5 4 6 HSTROBE DDMARDY DMACK D...

Page 54: ...it shall be ready to receive two more strobes after DDMARDY is negated Table 37 Ultra DMA cycle timing chart Device Pausing Write PARAMETER DESCRIPTION all values in ns MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX tSR HSTROBE to DDMARDY time 50 30 20 tRFS DDMARDY to final HSTROBE time 75 70 60 60 60 50 HSTROBE DDMARDY DMACK DMARQ tSR STOP tRFS ...

Page 55: ...STROBE time 75 70 60 60 60 50 tRP Ready to pause time 160 125 100 100 100 85 tLI Limited interlock time 0 150 0 150 0 150 0 100 0 100 0 75 tMLI Interlocking time with minimum 20 20 20 20 20 20 tCS CRC word setup time at device 15 10 7 7 5 5 tCH CRC word hold time at device 5 5 5 5 5 5 tACK Hold time for DMACK negation 20 20 20 20 20 20 tIORDYZ Maximum time before releasing IORDY 20 20 20 20 20 20 ...

Page 56: ...SS Time from HSTROBE edge to assertion of STOP 50 50 50 50 50 50 tLI Limited interlock time 0 150 0 150 0 150 0 100 0 100 0 75 tMLI Interlock time with minimum 20 20 20 20 20 20 tCS CRC word setup time at device 15 10 7 7 5 5 tCH CRC word hold time at device 5 5 5 5 5 5 tACK Hold time for DMACK 20 20 20 20 20 20 tIORDYZ Maximum time before releasing IORDY 20 20 20 20 20 20 HSTROBE DDMARDY DMACK DM...

Page 57: ...ents before interrupt the value is invalid 6 9 1 Cabling The maximum cable length from the host system to the drive plus circuit pattern length in the host system shall not exceed 18 inches For higher data transfer application 8 3 MB s a modification in the system design is recommended to reduce cable noise and cross talk such as a shorter cable bus termination or a shielded cable For systems oper...

Page 58: ...Deskstar 7K400 Hard Disk Drive Specification 44 ...

Page 59: ...Deskstar 7K400 Hard Disk Drive Specification 45 7 0 Jumper Settings 7 1 Connector location 7 1 1 Jumper pin identification Jumper pins Pin A Pin B Pin I DERA001 prz ...

Page 60: ... 1 if it is present The Device 1 Slave Present setting is for a slave device that does not comply with the ATA specification Note In conventional terminology Device 0 designates a Master and Device 1 designates a Slave 7 1 3 Jumper positions 7 1 3 1 16 logical head default normal use The figure below shows the jumper positions used to select Device 0 Device 1 Cable Selection or Device1 Slave Prese...

Page 61: ... default The figure below shows the jumper positions used to select Device 0 Device 1 Cable Selection or Device1 Slave Present setting 15 logical heads instead of default 16 logical head models Notes 1 To enable the CSEL mode Cable Selection mode the jumper block must be installed at E F In the CSEL mode the drive address is determined by AT interface signal 28 CSEL as follows When CSEL is grounde...

Page 62: ...h clips the LBA to 66055248 The CHS is unchanged from the factory default of 16383 16 63 7 1 3 4 Power up in Standby The figure below shows the jumper positions used to select Device 0 Device 1 Cable Selection or Device 1 Slave Present to enable Power up in Standby Table 44 Jumper settings for Disabling Auto Spin G I E C A H F D B DEVICE 0 Master G I E C A H F D B DEVICE 1 Slave G I E C A H F D B ...

Page 63: ...SET FEATURES subcommand 07h Refer to 12 28 Set Features 3 To enable the CSEL mode Cable Selection mode the jumper block must be installed at E F In the CSEL mode the drive address is determined by AT interface signal 28 CSEL as follows When CSEL is grounded or at a low level the drive address is 0 Device 0 When CSEL is open or at a high level the drive address is 1 Device 1 ...

Page 64: ... humidity Operating conditions Temperature 5C to 55ºC See note below Relative humidity 8 to 90 non condensing Maximum wet bulb temperature 29 4ºC non condensing Maximum temperature gradient 15ºC hour Altitude 300 to 3 048 m Non operating conditions Temperature 40C to 65ºC Relative humidity 5 to 95 non condensing Maximum wet bulb temperature 35ºC non condensing Altitude 300 to 12 000 m 0 1 0 2 0 3 ...

Page 65: ...plied to the drive 7 3 2 Power supply current typical Except for a peak of less than 100 ms duration 1 Random seeks at 40 duty cycle 2 Seek duty 30 W R duty 45 Idle duty 25 Table 47 Input voltage Input voltage supply2 During run and spin up Absolute max spike voltage1 Supply rise time 5 V 5 V 5 0 3 to 7 V 0 to 5 sec 12 V 12 V 10 8 0 3 to 15 V 0 to 5 sec Table 48 Power supply current of PATA model ...

Page 66: ...al level difference at the four screws position and has less than 300 millivolts peak to peak level difference to the ground of the drive power connector Table 49 Power supply current of SATA model Power supply current of SATA model 5 Volts mA 12 Volts mA Total W values in milliamps RMS Pop Mean Std Dev Pop Mean Std Dev Idle average 470 12 600 12 9 6 Idle ripple peak to peak 250 40 600 20 Low RPM ...

Page 67: ...nt section 7 4 3 Start stop cycles The drive withstands a minimum of 50 000 start stop cycles in a 40 C environment and a minimum of 10 000 start stop cycles in extreme temperature or humidity within the operating range 7 4 4 Preventive maintenance None 7 4 5 Data reliability Probability of not recovering data is 1 in 1014 bits read ECC On The Fly correction 1 Symbol 8 bits 4 Interleave 12 ECCs ar...

Page 68: ...d in order to keep the air pressure inside of the disk enclosure equal to external air pressure The following table lists the dimensions of the drive Table 51 Physical dimensions and weight Height mm 25 4 0 4 Width mm 101 6 0 4 Length mm 146 0 0 6 Weight grams maximum 700 BR EAT HER HO LE D ia 2 0 0 1 19 7 0 4 38 9 0 4 101 6 0 4 146 0 6 25 4 0 4 LEFT FR O N T D O N O T B LO C K T H E B R E A T H E...

Page 69: ...ations and size of the drive are shown below All dimensions are in mm Figure 1 Mounting hole locations Thread 1 2 3 4 5 6 7 6 32 UNC 41 28 0 5 44 45 0 2 95 25 0 2 6 35 0 2 28 5 0 5 60 0 0 2 41 6 0 2 Side View 5 6 7 Bottom View 1 2 3 4 I F Connector 4X Max penetration 4 0 mm 6X Max penetration 4 5 mm ...

Page 70: ...Deskstar 7K400 Hard Disk Drive Specification 56 7 5 3 Connector locations PATA m odel 3X 5 08 0 1 4 6 0 5 42 73 REF 13 43 REF 33 39 4 REF SATA model ...

Page 71: ...propriate screws or equivalent mounting hardware The recommended mounting screw torque is 0 6 1 0 Nm 6 10 Kgf cm The recommended mounting screw depth is 4 mm maximum for bottom and 4 5 mm maximum for horizontal mounting Drive level vibration test and shock test are to be conducted with the drive mounted to the table using the bottom four screws 7 5 5 Heads unload and actuator lock The head load un...

Page 72: ...g in the specified conditions No errors occur with 0 5 G 0 to peak 5 to 300 to 5 Hz sine wave 0 5 oct min sweep rate with 3 minute dwells at two major resonances No data loss occurs with 1 G 0 to peak 5 to 300 to 5 Hz sine wave 0 5 oct min sweep rate with 3 minute dwells at two major resonances 7 6 2 Nonoperating vibration The drive does not sustain permanent damage or loss of previously recorded ...

Page 73: ...ry procedures No error occurs with a 10 G half sine shock pulse of 11 ms duration in all models No data loss occurs with a 30 G half sine shock pulse of 4 ms duration in all models No data loss occurs with a 55 G half sine shock pulse of 2 ms duration in all models 7 6 4 Nonoperating shock The drive will operate with no degradation of performance after being subjected to shock pulses with the foll...

Page 74: ...ulse The figure below shows the maximum acceleration level and duration 7 6 5 Nonoperating rotational shock All shock inputs shall be applied around the actuator pivot axis Table 56 Rotational shock Table 55 Sinusoidal shock wave Acceleration level G Duration ms 225 2 150 11 Duration Rad sec2 1 ms 30 000 2 ms 20 000 ...

Page 75: ...llowing formula Dwell time 0 5 x 60 RPM Seek rate 0 4 average seek time dwell time 7 8 Identification labels The following labels are affixed to every drive A label containing the Hitachi logo the Hitachi Global Storage Technologies part number and the statement Made by Hitachi Global Storage Technologies Inc or Hitachi Global Storage Technol ogies approved equivalent A label containing the drive ...

Page 76: ... 9 4 Safe handling The product is conditioned for safe handling in regards to sharp edges and corners 7 9 5 Environment The product does not contain any known or suspected carcinogens Environmental controls meet or exceed all applicable government regulations in the country of origin Safe chemi cal usage and manufacturing control are used to protect the environment An environmental impact assessme...

Page 77: ... 2 0001 401 and NB 2 0001 403 7 10 1 CE mark The product is declared to be in conformity with requirements of the following EC directives under the sole responsibility of Hitachi Global Storage Technologies Japan Ltd Council Directive 89 336 EEC on the approximation of laws of the Member States relating to electromagnetic compatibility 7 10 2 C TICK mark The product complies with the following Aus...

Page 78: ...Deskstar 7K400 Hard Disk Drive Specification 64 ...

Page 79: ...vision ATA generation Revision 4 dated on 23 December 2003 with certain limitations described in 2 0 Deviations From Standard 8 2 Terminology 8 3 Deviations from standard The device conforms to the referenced specifications with the following deviations Check Power Mode Check Power Mode command returns FFh to Sector Count Register when the device is in Idle mode This command does not support 80h a...

Page 80: ...Deskstar 7K400 Hard Disk Drive Specification 66 ...

Page 81: ...ost alternate status Addresses Functions CS0 CS1 DA2 DA1 DA0 READ DIOR WRITE DIOW N N x x x Data bus high impedance Not used Control block registers N A 0 x x Data bus high impedance Not used N A 1 0 x Data bus high impedance Not used N A 1 1 0 Alternate Status Device Control N A 1 1 1 Device Address Not used Command block registers A N 0 0 0 Data Data A N 0 0 1 Error Register Features A N 0 1 0 S...

Page 82: ... the end of the com mand this register is updated to reflect the current cylinder number In LBA Mode this register contains Bits 16 23 At the end of the command this register is updated to reflect the current LBA Bits 16 23 The cylinder number may be from zero to the number of cylinders minus one When 48 bit addressing commands are used the most recently written content contains LBA Bits 16 23 and...

Page 83: ... DRQ 1 is in the Status Register 9 7 Device Control Register Table 61 Device Control Register 7 6 5 4 3 2 1 0 HOB 1 SRST IEN 0 Bit Definitions HOB HOB high order byte is defined by the 48 bit Address feature set A write to any Command Register shall clear the HOB bit to zero SRST Software Reset The device is held at reset when RST 1 Setting RST 0 again enables the device To ensure that the device ...

Page 84: ...st significant DS1 Drive Select 1 The Drive Select bit for device 1 is active low DS1 0 when device 1 slave is selected and active DS0 Drive Select 0 The Drive Select bit for device 0 is active low DS0 0 when device 0 master is selected and active 7 6 5 4 3 2 1 0 1 L 1 DRV HS3 HS2 HS1 HS0 L Binary encoded address mode select When L 0 addressing is by CHS mode When L 1 addressing is by LBA mode DRV...

Page 85: ...6 sectors in 48 bit addressing is specified If the register is zero at command completion the command was successful If it is not successfully completed the register contains the number of sectors which need to be transferred in order to complete the request The contents of the register are defined otherwise on some commands These definitions are given in the command descriptions 7 6 5 4 3 2 1 0 C...

Page 86: ...ters The host should not read or write any registers when BSY 1 If the host reads any register when BSY 1 the contents of the Status Register will be returned DRDY RDY Device Ready RDY 1 indicates that the device is capable of responding to a command RDY will be set to zero during power on until the device is ready to accept a command If the device detects an error while processing a command RDY i...

Page 87: ...e it set to 1 even if the host is continuously reading the Status Register Therefore the host should not attempt to use IDX for timing purposes ERR Error ERR 1 indicates that an error occurred during execution of the previous command The Error Register should be read to determine the error type The device sets bit ERR 0 when the next command is received from the host ...

Page 88: ...Deskstar 7K400 Hard Disk Drive Specification 74 ...

Page 89: ...sponse table POR hard reset soft reset Aborting Host interface O O Aborting Device operation 1 1 Initialization of hardware O X X Internal diagnostic O X X Spinning spindle O X X Initialization of registers 2 O O O DASP handshake O O X PDIAG handshake O O O Reverting programmed parameters to default Number of CHS set by Initialize Device Parameters Multiple mode Write Cache Read look ahead ECC byt...

Page 90: ...rd reset or the Execute Device Diagnostic command is shown in the figure below Table 67 Default Register Values Register Default Value Error Diagnostic Code Sector Count 01h Sector Number 01h Cylinder Low 00h Cylinder High 00h Device Head A0h Status 50h Alternate Status 50h Table 68 Diagnostic codes Code Description 01h No error detected 02h Formatter device error 03h Sector buffer error 04h ECC c...

Page 91: ...e 0 may assert DASP to indicate device activity Hard Reset Soft Reset If Device 1 is present Device 0 shall read PDIAG to determine when it is valid to clear the BSY bit and whether Device 1 has reset without any errors otherwise Device 0 shall simply reset and clear the BSY bit DASP is asserted by Device 0 and Device 1 if it is present in order to indicate device active Execute Device Diagnostic ...

Page 92: ...host requests the number of sectors per logical track and the number of heads per logical cylinder The device then computes the number of logical cylinders available in requested mode The default CHS translation mode is described in the Identify Device Information The current CHS translation mode also is described in the Identify Device Information 10 4 2 LBA addressing mode Logical sectors on the...

Page 93: ...o one setting a pending interrupt and asserting INTRQ if selected and if nIEN is cleared to zero SERV shall remain set until all commands ready for service have been serviced The pending interrupt shall be cleared and INTRQ negated by a Status register read or a write to the Command register When the device is ready to continue processing a bus released command and BSY or DRQ is set to one i e the...

Page 94: ...ed Sleep Mode The lowest power consumption when the device is powered on occurs in Sleep Mode When in Sleep Mode the device requires a reset to be activated Standby Mode The device interface is capable of accepting commands but since the media may not be immediately accessible there is a delay while waiting for the spindle to reach operating speed Idle Mode In Idle Mode the device is capable of re...

Page 95: ...hysical interface as defined in the following table Ready RDY is not a power condition A device may post ready at the interface even though the media may not be accessible Table 70 Power conditions Mode BSY RDY Interface active Media Active x x Yes Active Idle o 1 Yes Active Standby o 1 Yes Inactive Sleep x x No Inactive ...

Page 96: ...isting Accordingly lower attribute values indicate that the analysis algorithms being used by the device are predicting a higher probability of a degrading or faulty condition 10 7 3 Attribute thresholds Each attribute value has a corresponding attribute threshold limit which is used for direct comparison to the attribute value to indicate the existence of a degrading or faulty condition The numer...

Page 97: ...re modification all error log data is discarded and the device error count for the life of the device is reset to zero 10 7 8 Self test The device provides the self test features which are initiated by SMART Execute Off line Immediate command The self test checks the fault of the device reports the test status in Device Attributes Data and stores the test result in the SMART self test log sector a...

Page 98: ...n Media access commands are enabled by either a Security Unlock command or a Security Erase Unit command Device Unlocked Mode The device enables all commands If a password is not set this mode is entered after power on otherwise it is entered by a Security Unlock or a Security Erase Unit command Device Frozen Mode The device enables all commands except those which can update the device lock functi...

Page 99: ...d is set the device will automatically enter lock mode the next time the device is powered on Master Password When the Master Password is set the device does NOT enable the Device Lock Function and the device CANNOT be locked with the Master Password but the Master Password can be used for unlocking the locked device Identify Device Information word 92 contains the value of the Master Password Rev...

Page 100: ...POR 1 refer to the commands in Figure 10 8 5 Command table on page 90 POR Device Locked mode Unlock CMD Command 1 Command 1 Password Erase Unit Password Match Reject Complete Complete Erase Unit Lock function Disable Normal operation All commands are available Freeze Lock command Enter Device Frozen mode Normal Operation expect Set Password Disable Password Erase Unit Unlock commands Enter Device ...

Page 101: ...NLOCK command has an attempt limit the purpose of which is to prevent attempts to unlock the drive with various passwords numerous times The device counts the password mismatch If the password does not match the device counts it without distinguishing the Master password and the User password If the count reaches 5 EXPIRE bit bit 4 of Word 128 in Identify Device information is set and then the SEC...

Page 102: ...perations o o o Initialize Device Parameters o o o S M A R T Execute Off line Immediate o o o NOP S M A R T Read Attribute Values o o o Read Buffer o o o S M A R T Read Attribute Thresholds o o o Read DMA x o o S M A R T Return Status o o o Read DMA Ext x o o S M A R T Save Attribute Values o o o Read DMA Queued x o o S M A R T Read Log Sector o o o Read DMA Queued Ext x o o S M A R T Write Log Se...

Page 103: ...e is as follows i Issue a Read Native Max ADDRESS command to get the real device maximum LBA Returned value shows that native device maximum LBA is 12 692 735 C1ACFFh regardless of the current setting ii Make the entire device accessible including the protected area by setting the device maximum LBA to 12 692 735 C1ACFFh via Set Max ADDRESS command The option may be either nonvolatile or volatile ...

Page 104: ...t Max Lock Set Max Freeze Lock Set Max Unlock The Set Max Set Password command allows the host to define the password to be used during the current power on cycle The password does not persist over a power cycle but does persist over a hardware or software reset This password is not related to the password used for the Security Mode Feature set When the password is set the device is in the Set_Max...

Page 105: ...rom the host however the actual seek operation for the next seek command starts immediately after the actual seek operation for the first seek command is completed In other words the execution of two seek commands overlaps excluding the time required for the actual seek operation With this overlap the total elapsed time for a number of seek commands results in the total accumulated time for actual...

Page 106: ...e data onto the disk While writing data after completed acknowledgment of a write command soft reset or hard reset does not affect its operation However power off terminates the writing operation immediately and unwritten data is lost The Soft reset Standby Immediate command and Flush Cache commands during the writing of the cached data are executed after the completion of writing to media So the ...

Page 107: ...Nonrecovered write errors When a write operation cannot be completed after the Error Recovery Procedure ERP is fully carried out the sector s are reallocated to the spare location An error is reported to the host system only when the write cache is disabled and the auto reallocation has failed If the Write Cache function is ENABLED when the number of available spare sectors reaches 0 sector both A...

Page 108: ...fter power cycle A device needs a SET FEATURES subcommand to spin up to active state when the device has powered up into Standby The device remains in Standby until the SET FEATURES subcommand is received If power up into Standby is enabled when an IDENTIFY DEVICE is received while the device is in Standby as a result of powering up into Standby the device shall set word 0 bit 2 to one to indicate...

Page 109: ...ATURES command in detail This feature set uses the following functions A SET FEATURES subcommand to enable Advanced Power Management A SET FEATURES subcommand to disable Advanced Power Management Advanced Power Management is independent of the Standby timer setting If both Advanced Power Management and the Standby timer are set the device will go to the Standby state when the timer times out or th...

Page 110: ...anagement and the Standby timer setting are independent functions The device shall enter Standby mode if any of the following are true 1 The Standby timer has been set and times out 2 Automatic Power Management is enabled and the associated algorithm indicates that the Standby mode should be entered to save power 3 Automatic Acoustic Management is enabled and the associated algorithm indicates tha...

Page 111: ...Features subcommand code 09h Enable Address Offset Mode offsets address Cylinder 0 Head 0 Sector 1 LBA 0 to the start of the non volatile protected area established using the Set Max Address command The offset condition is cleared by Subcommand 89h Disable Address Offset Mode Hardware reset or Power on Reset If Reverting to Power on Defaults has been enabled by Set Features command it is cleared b...

Page 112: ...ted area A subsequent Set Max Address command with the address returned by Read Max Address command allows access to the entire drive Addresses wrap so the entire drive remains addressable If a non volatile protected area has not been established before the device receives a Set Features Table 73 Enable Disable Address Offset Mode 10 16 2 Identify Device Data Identify Device data word 83 bit 7 ind...

Page 113: ...ster to one and then reading the desired register If HOB in the Device Control register is cleared to zero the host reads the most recently written content when the register is read A write to any Command Block register shall cause the device to clear the HOB bit to zero in the Device Control register The most recently written content always gets written by a register write regardless of the state...

Page 114: ...is device vendor specific The streaming commands may access any user LBA on a device These commands may be interspersed with non streaming commands but there may be an impact on performance due to the unknown time required to complete the non streaming commands The streaming commands should be issued using a specified minimum number of sectors transferred per command as specified in word 95 of the...

Page 115: ...ined data A future read of this area may not report an error even though the data is erroneous 10 18 7 Handle Streaming Error bit The Handle Streaming Error bit specifies to the device that this command starts at the LBA of a recently reported error section so the device may attempt to continue its corresponding error recovery sequence where it left off earlier This mechanism allows the host to sc...

Page 116: ...Deskstar 7K400 Hard Disk Drive Specification 102 ...

Page 117: ...as a device that is no longer responding Interrupts are cleared when the host reads the Status Register issues a reset or writes to the Command Register 11 1 PIO Data In commands The following are Data In commands Device Configuration Identity Identify Device Read Buffer Read Log Ext Read Long Read Multiple Read Multiple Ext Read Sector s Read Sector s Ext Read Stream PIO S M A R T Read Attribute ...

Page 118: ...t the command by setting BSY 0 ERR 1 ABT 1 and interrupting the host If an error occurs the device will set BSY 0 ERR 1 and DRQ 1 The device will then store the error status in the Error Register and interrupt the host The registers will contain the location of the sector in error The error location will be reported using CHS mode or LBA mode The mode is decided by the mode select bit bit 6 of the...

Page 119: ... receive a sector b The host writes one sector of data including ECC bytes via the Data Register c The device sets BSY 1 after it has received the sector d After processing the sector of data the device sets BSY 0 and interrupts the host e In response to the interrupt the host reads the Status Register f The device clears the interrupt in response to the Status Register being read The Write Multip...

Page 120: ...tribute Autosave S M A R T Enable Disable Automatic Off Line S M A R T Enable Operations S M A R T Execute Off line Data Collection S M A R T Return Status S M A R T Save Attribute Values Standby Standby Immediate Execution of these commands involves no data transfer a The host writes any required parameters to the Features Sector Count Sector Number Cylinder and Device Head Registers b The host w...

Page 121: ...mmands The host resets the DMA channel prior to reading status from the device The DMA protocol allows high performance multitasking operating systems to eliminate processor overhead asso ciated with PIO transfers Host write any required parameters to the Features Sector Count Sector Number Cylinder and Device Head registers The host initializes the Slave DMA channel The host writes any required p...

Page 122: ...device clears BDY 2 Data Transfer and Command Completion If the device is ready for data transfer REL is cleared a the host transfers the data for the command identified by the Tag number using tghe DMA transfer pro tocol currently in effect b the device generates an interrupt to the host when all of the data has been transferred c the host may issue another command or wait for service request fro...

Page 123: ...e E3 1 1 1 0 0 0 1 1 3 Idle 97 1 0 0 1 0 1 1 1 3 Idle Immediate E1 1 1 1 0 0 0 0 1 3 Idle Immediate 95 1 0 0 1 0 1 0 1 3 Initialize Device Parameters 91 1 0 0 1 0 0 0 1 3 NOP 00 0 0 0 0 0 0 0 0 1 Read Buffer E4 1 1 1 0 0 1 0 0 4 Read DMA C8 1 1 0 0 1 0 0 0 4 Read DMA C9 1 1 0 0 1 0 0 1 4 Read DMA Ext 25 0 0 1 0 0 1 0 1 5 Read DMA Queued C7 1 1 0 0 0 1 1 1 5 Read DMA Queued Ext 26 0 0 1 0 0 1 1 0 1...

Page 124: ...on B0 1 0 1 1 0 0 0 0 1 S M A R T Read Attribute Values B0 1 0 1 1 0 0 0 0 1 S M A R T Read Attribute Thresholds B0 1 0 1 1 0 0 0 0 3 S M A R T Return Status B0 1 0 1 1 0 0 0 0 3 S M A R T Save Attribute Values B0 1 0 1 1 0 0 0 0 2 S M A R T Write Log Sector B0 1 0 1 1 0 0 0 0 3 Standby E2 1 1 1 0 0 0 1 0 3 Standby 96 1 0 0 1 0 1 1 0 3 Standby Immediate E0 1 1 1 0 0 0 0 0 3 Standby Immediate 94 1 ...

Page 125: ...Operations B0 D9 S M A R T Return Status B0 DA S M A R T Enable Disable Automatic Off line B0 DB Set Features Enable Write Cache EF 02 Set Transfer mode EF 03 Enable Advanced Power Management EF 05 Enable Power up in Standby Feature Set EF 06 Power up in Standby Feature Set Device Spin up EF 07 Enable Address Offset mode EF 09 Enable Automatic Acoustic Management EF 42 52 bytes of ECC apply on Rea...

Page 126: ...meaning is already obsolete there is no difference between 0 and 1 Using 0 is recommended for future compatibility B Option Bit This indicates that the Option Bit of the Sector Count Register be specified This bit is used by Set Max ADDRESS command V Valid This indicates that the bit is part of an output parameter and should be specified x This indicates that the hex character is not used This ind...

Page 127: ...r is at speed and the device is not in Standby or Sleep mode Other wise the Sector Count Register is set to 0 Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Error see below Sector Count Sector Count V V V V V V V V Sector Number Sector Number Cylinder Low Cylinder Low Cylinder High Cylinder High Device Head 1 1 D Dev...

Page 128: ...ata High Feature Current V V V V V Error See Below Previous V V V V V V V V Sector Count Current V V V V V V V V Sector Count HOB 0 Previous V V V V V V V V HOB 1 Sector Number Current Sector Number HOB 0 Previous HOB 1 Cylinder Low Current Cylinder Low HOB 0 Previous HOB 1 Cylinder High Current Cylinder High HOB 0 V V V V V V V V Previous HOB 1 Device Head 1 1 1 D Device Head Command 0 1 0 1 0 0 ...

Page 129: ...s register Identify Device words 99 98 micriseconds This time shall be used by the device when a streaming command with the same stream ID and a CCTL of zero is issued The time is measured from the write of the command register to the final INTRQ for command completion Sector Count Current Allocation Unit Size In Sectors 7 0 Sector Count Previous Allocation Unit Size In Sectors 15 8 ...

Page 130: ... settings After successful execution of a DEVICE CONFIGURATION FREEZE LOCK com mand all DEVICE CONFIGURATION SET DEVICE CONFIGURATION FREEZE LOCK DEVICE CONFIGURATION IDENTIFY and DEVICE CONFIGURATION RESTORE commands are aborted by the device The DEVICE CONFIGURATION FREEZE LOCK condition shall be cleared by a power down The DEVICE CONFIGURATION FREEZE LOCK condition shall not be cleared by hardw...

Page 131: ...t set in the overlay received from a DEVICE CONFIGURATION IDENTIFY command no action is taken for that bit The format of the overlay transmitted by the device is described in the table in Table 81 Device Configuration Overlay Data structure on page 118 The restrictions on changing these bits is described in the text following that table If any of the bit modification restrictions described are vio...

Page 132: ...ted 15 7 Reserved 6 1 Ultra DMA mode 6 and below are supported 5 1 Ultra DMA mode 5 and below are supported 4 1 Ultra DMA mode 4 and below are supported 3 1 Ultra DMA mode 3 and below are supported 2 1 Ultra DMA mode 2 and below are supported 1 1 Ultra DMA mode 1 and below are supported 0 1 Ultra DMA mode 0 is supported 3 6 Maximum LBA address 7 Command set feature set supported 15 13 Reserved 12 ...

Page 133: ...lid bit location bits 7 0 Sector count error reason code description 01h DCO feature is frozen 02h Device is now Security Locked mode 03h Device s feature is already modified with DCO 04h User attempt to disable any feature enabled 05h Device is now SET MAX Locked or Frozen mode 06h Protected area is now established 07h DCO is not supported 08h Subcommand code is invalid FFh other reason ...

Page 134: ...w microcode This error is reported only when the reload of microcode is requested In reloading new microcode the device does not preserve its state and settings but reset them just like the device is executing a power on For instance the device does DASP handshake in reloading new microcode Thus the device does not recognize the slave device even though it exists Also when the spin up of the devic...

Page 135: ...e register contains a diagnostic code See Table 67 Default Register Values on page 76 for the definition Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Error see below Sector Count Sector Count Sector Number Sector Number Cylinder Low Cylinder Low Cylinder High Cylinder High Device Head 1 1 Device Head Command 1 0 0 ...

Page 136: ...and Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Error see below Sector Count Sector Count Sector Number Sector Number Cylinder Low Cylinder Low Cylinder High Cylinder High Device Head 1 1 D Device Head Command 1 1 1 0 0 1 1 1 Status see below Error Register Status Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 CRC UNC 0 IDN 0 A...

Page 137: ...2 1 0 Register 7 6 5 4 3 2 1 0 Data Low Data Low Data High Data High Feature Current Error see below Previous Sector Count Current Sector Count HOB 0 Previous HOB 1 Sector Number Current Sector Number HOB 0 Previous HOB 1 Cylinder Low Current Cylinder Low HOB 0 Previous HOB 1 Cylinder High Current Cylinder High HOB 0 Previous HOB 1 Device Head D Device Head Command 1 1 1 0 1 0 1 0 Status See below...

Page 138: ...A address bits 8 15 Low and bits 16 23 High are to be formatted L 1 H This indicates the head number of the track to be formatted L 0 In LBA mode this reg ister specifies that LBA address bits 24 27 are to be formatted L 1 Input parameters from the device Sector Number In LBA mode this register specifies the current LBA address bits as 0 7 L 1 Cylinder High Low In LBA mode this register specifies ...

Page 139: ...se Prepare F3h command should be completed immediately prior to the Format Unit command If the device receives a Format Unit command without a prior Security Erase Prepare command the device aborts the Format Unit command All values in Feature register are reserved and any values other than 11h should not be put into Feature register This command does not request a data transfer Command execution ...

Page 140: ...0 beginning on page 127 Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Error see below Sector Count Sector Count Sector Number Sector Number Cylinder Low Cylinder Low Cylinder High Cylinder High Device Head 1 1 D Device Head Command 1 1 1 0 1 1 0 0 Status see below Error Register Status Register 7 6 5 4 3 2 1 0 7 6 5...

Page 141: ...spin up after power up Identify Device is incomplete 03 00XXH Number of heads in default translate mode 04 0 Reserved 05 0 Reserved 06 003FH Number of sectors per track in default translate mode 07 0000H Number of bytes in sector gap 08 0000H Number of bytes in sync field 09 0000H Reserved 10 19 XXXX Serial number in ASCII 0 not specified 20 0003H Controller type 0003 dual ported multiple sector b...

Page 142: ...a transfer cycle timing mode 52 0200H DMA data transfer cycle timing mode Refer to Word 62 and 63 53 0007H Validity flag of the word 15 3 0 Reserved 2 1 1 Word 88 is Valid 1 1 1 Word 64 70 are Valid 0 1 1 Word 54 58 are Valid 54 XXXXH Number of current cylinders 55 XXXXH Number of current heads 56 XXXXH Number of current sectors per track 57 58 XXXXH Current capacity in sectors Word 57 specifies t...

Page 143: ...nds 240 ns 8 3 MB s 68 0078H Minimum PIO Transfer Cycle Time With IORDY Flow Control 15 0 78h Cycle time in nanoseconds 120 ns 16 6 MB s 69 74 0000H Reserved 75 00XXH Queue depth 15 5 Reserved 4 0 Maximum queue depth 76 79 0000H Reserved 80 00FCH Major version number 15 0 Fch ATA 2 ATA 3 ATA ATAPI 4 ATA ATAPI 5 ATA ATAPI 7 81 001AH Minor version number 15 0 1Ah ATA ATAPI 7 T13 1532D revision 1 82 ...

Page 144: ...0 Removable Media Status Notification feature 3 1 Advanced Power Management Feature Set 2 0 CFA feature set 1 1 READ WRITE DMA QUEUED 0 1 DOWNLOAD MICROCODE command 84 4733H Command set feature supported extension 15 14 01 Word 84 is valid 13 11 0 Reserved 10 1 URG bit supported for WRITE STREAM DMA and WRITE STREAM PIO 9 1 URG bit supported for READ STREAM DMA and READ STREAM PIO 8 1 World wide n...

Page 145: ...d 13 READ BUFFER command 12 WRITE BUFFER command 11 Reserved 10 Host Protected Area Feature Set 9 DEVICE RESET command 8 SERVICE interrupt 7 RELEASE interrupt 6 LOOK AHEAD 5 WRITE CACHE 4 PACKET Command Feature Set 3 Power Management Feature Set 2 Removable Feature Set 1 Security Feature Set 0 SMART Feature Set ...

Page 146: ... Media Status Notification feature 3 Advanced Power Management Feature Set 2 CFA feature set 1 READ WRITE DMA QUEUED 0 DOWNLOAD MICROCODE command 87 4723H or 4733H Command set feature enabled 15 14 01 Word 87 is valid 13 11 0 Reserved 10 1 URG bit supported for WRITE STREAM DMA and WRITE STREAM PIO 9 1 URG bit supported for READ STREAM DMA and READ STREAM PIO 8 1 World wide name supported 7 0 WRIT...

Page 147: ...0 Not Active 9 Mode 1 1 Active 0 Not Active 8 Mode 0 1 Active 0 Not Active 7 0 7F Ultra DMA transfer mode supported 7 Reserved 0 6 Mode 6 1 Support 5 Mode 5 1 Support 4 Mode 4 1 Support 3 Mode 3 1 Support 2 Mode 2 1 Support 1 Mode 1 1 Support 0 Mode 0 1 Support 89 XXXXH Time required for Security Erase Unit completion Time value x 2 minutes 90 0000H Time required for Enhanced Security Erase comple...

Page 148: ...thod 0 Shall be set to one if Device 0 94 XXXXH Current Advanced Acoustic Management value 15 8 Vendor s Recommended Acoustic Management level 7 0 Current Acoustic Management level 95 xxxxH Stream Minimum Request Size Number of sectors that provides optimum performance in streaming environment This number shall be a power of two with a minimum of eight sectors 4096 bytes The starting LBA value for...

Page 149: ...reaming Transfer Time PIO The worst case sustainable transfer time per sector for the device is calculated as follows Streaming Transfer Time word 104 words 99 98 65536 If the Streaming Feature set is not supported by the device the content of word 104 shall be zero 105 106 0000H Reserved 107 58C5H Inter seek delay for ISO 779 acoustic testing in microseconds 108 111 xxxxH World wide name the opti...

Page 150: ...hat are vendor specific Word Content Description 129 xxxxH Current Set Feature Option Bit assignments 15 4 Reserve 3 Auto reassign 1 Enabled 2 Reverting 1 Enabled 1 Read Look ahead 1 Enabled 0 Write Cache 1 Enabled 130 159 xxxxH Reserved 160 254 0000H Reserved 255 xxA5H 15 8 Checksum This value is the two s complement of the sum of all bytes in byte 0 through 510 7 0 Signature ...

Page 151: ...ow When the automatic power down sequence is enabled the drive will enter Standby mode automatically if the time out interval expires with no drive access from the host The time out interval will be reinitialized if there is a drive access before the time out interval expires Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Fe...

Page 152: ...t commands immediately The Idle Immediate command will not affect the auto power down time out parameter Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Error see below Sector Count Sector Count Sector Number Sector Number Cylinder Low Cylinder Low Cylinder High Cylinder High Device Head 1 1 D Device Head Command 1 1 ...

Page 153: ...ans that there are no sectors rather than 256 sectors per track H This indicates the number of heads minus 1 per cylinder The minimum is 0 and the maxi mum is 15 The following condition needs to be met to avoid invalid number of cylinders beyond FFFFh Total number of user addressable sectors sector count x H 1 FFFFh The total number of user addressable sectors is described in Identify Device comma...

Page 154: ...y host is not changed Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature V V V V V V V V Error see below Sector Count Sector Count Initial value Sector Number Sector Number Initial value Cylinder Low Cylinder Low Initial value Cylinder High Cylinder High Initial value Device Head 1 1 D Device Head Initial value Command 0...

Page 155: ...nts of the sector may be different if any reads or writes have occurred since the Write Buffer command was issued Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Error see below Sector Count Sector Count Sector Number Sector Number Cylinder Low Cylinder Low Cylinder High Cylinder High Device Head 1 1 D Device Head Com...

Page 156: ...its 0 7 L 1 Cylinder High Low This indicates the cylinder number of the first sector to be transferred L 0 In LBA mode this register specifies the transfer of LBA address bits 8 15 Low and 16 23 High L 1 H This indicates the head number of the first sector to be transferred L 0 In LBA mode this register specifies that LBA bits 24 27 is to be transferred L 1 R This indicates the retry bit This bit ...

Page 157: ...ster contains the current LBA bits 0 7 L 1 Cylinder High Low This indicates the cylinder number of the last transferred sector L 0 In LBA mode this register contains the current LBA bits 8 15 Low and bits16 23 High L 1 H This indicates the head number of the sector to be transferred L 0 In LBA mode this register contains the current LBA bits 24 27 L 1 ...

Page 158: ...n the Sector Count register is specified then 65 536 sectors will be transferred Sector Number Current LBA 7 0 Sector Number Previous LBA 31 24 Cylinder Low Current LBA 15 8 Cylinder Low Previous LBA 39 32 Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low Data Low Data High Data High Feature Current Error see below Previous Sect...

Page 159: ...nrecoverable error Sector Number HOB 1 LBA 31 24 of the address of the first unrecoverable error Cylinder Low HOB 0 LBA 15 8 of the address of the first unrecoverable error Cylinder Low HOB 1 LBA 39 32 of the address of the first unrecoverable error Cylinder High HOB 0 LBA 23 16 of the address of the first unrecoverable error Cylinder High HOB 1 LBA 47 40 of the address of the first unrecoverable ...

Page 160: ...r LBA address bits 23 8 H Starting head number or LBA address bits 27 24 Input parameters from the device on bus release Sector Count Bits 7 3 Tag contain the Tag of the command being bus released Bit 2 REL is set to one Bit 1 I O is cleared to zero Bit 0 C D is cleared to zero Sector Number Cylinder High low H n a SRV Cleared to zero when the device performs a bus release This bit is set to one w...

Page 161: ...plete Sector Count Bits 7 3 Tag contain the Tag of the completed command Bit 2 REL is cleared to zero Bit 1 I O is set to one Bit 0 C D is set to one Sector Number Cylinder High Low H Sector address of unrecoverable error applicable only when an unrecoverable error has occurred SRV Cleared to zero ...

Page 162: ...delivered Sector Number Current LBA 7 0 Sector Number Previous LBA 31 24 Cylinder Low Current LBA 15 8 Cylinder Low Previous LBA 39 32 Cylinder High Current LBA 23 16 Cylinder High Previous LBA 47 40 Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low Data Low Data High Data High Feature Current V V V V V V V V Error see below Pre...

Page 163: ... Number HOB 0 LBA 7 0 of the address of the first unrecoverable error applicable only when an unrecoverable error has occurred Sector Number HOB 1 LBA 31 24 of the address of the first unrecoverable error applicable only when an unrecoverable error has occurred Cylinder Low HOB 0 LBA 15 8 of the address of the first unrecoverable error applicable only when an unrecoverable error has occurred Cylin...

Page 164: ...linder Low Current The first sector of the log to be read low order bits 7 0 Cylinder Low Previous The first sector of the log to be read high order bits 15 8 Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low Data Low Data High Data High Feature Current Error see below Previous Sector Count Current V V V V V V V V Sector Count H...

Page 165: ...associated with the log specified in the Sector Number register is not supported or enabled or if the values in the Sector Count Sector Number or Cylinder Low registers are invalid the device shall return com mand aborted Log Address Content Feature set Type 00h Log directory N A Read Only 03h Extended Comprehensive SMART error log SMART error logging Ready Only 06h SMART self test log SMART self ...

Page 166: ...ddress 01h 7 0 1 02h Number of sectors in the log at log address 01h 15 8 1 03h Number of sectors in the log at log address 01h 7 0 1 04h Number of sectors in the log at log address 01h 15 8 1 05h Number of sectors in the log at log address 20h 7 0 1 40h Number of sectors in the log at log address 20h 15 8 1 41h Number of sectors in the log at log address 21h 7 0 1 42h Number of sectors in the log...

Page 167: ...rors reported by the device These error log data structure entries are viewed as a circular buffer The fifth error shall create an error log structure that replaces the first error log data structure The next error after that shall create an error log data structure that replaces the second error log structure etc Unused error log data structures shall be filled with zeros 12 20 2 3 1 Data format ...

Page 168: ...mber register 7 0 1 05h Sector number register 15 8 1 06h Cylinder Low register 7 0 1 07h Cylinder Low register 15 8 1 08h Cylinder High register 7 0 1 09h Cylinder High register 15 8 1 0Ah Device Head register 1 0Bh Command register 1 0Ch Reserved 1 0Dh Timestamp milliseconds from Power on 4 0Eh 18 Description Bytes Offset Reserved 1 00h Error register 7 0 1 01h Sector count register 7 0 See Note...

Page 169: ...og sector The figure below defines the format of each of the sectors that comprise the Extended SMART self test log The Extended SMART self test log sector shall support 48 bit and 28 bit addressing All 28 bit entries contained in the SMART self test log defined in 11 42 6 Self test log data structure on page0203 shall also be included in the Extended SMART self test log with all 48 bit entries Th...

Page 170: ...y be greater than 31 but only the most recent 31 errors are represented by entries in the log If the Read Stream Error Count reaches the maximum value that can be represented after the next error is detected the Read Stream Error Count shall remain at the maximum value After successful completion of a Read Log Ext command with the LBA Low Register set to 22h the Read Stream Error Log shall be rese...

Page 171: ...at of the Write Stream Error log Entries are placed into the Write Stream Error log only when the SE bit is set to one in the Status Register The 512 bytes returned shall contain a maximum of 31 error entries The Write Stream Error Count shall contain the total number of Write Stream Errors detected since the last successful completion of the Read Log Ext command with LBA Low register set to 21h T...

Page 172: ...ow register is 20h This data set is referred to as the Streaming Performance Parameters log the length of which in sectors is statically indicated in Read Log Ext log address 00h Log Directory The host should base its calculations on the larger of its Typical Host Interface Sector Time and the device reported Sector Time values and on the sum of the device reported Access Time values and any addit...

Page 173: ...location LBA 7 0 LBA 47 40 n n 5 Identify Device words 99 98 65536 time units per sector at the reference location n 6 n 7 Description Bytes LBA of start of region LBA 7 0 LBA 47 40 n n 5 Position number in the range 0 32767 n 6 n 7 Description Bytes Difference in position from last stream access to new stream access n n 1 Time that may be required to begin access at new stream access position in ...

Page 174: ...r Count must be set to one Sector Number This indicates the sector number of the sector to be transferred L 0 In LBA mode this register contains LBA bits 0 7 L 1 Cylinder High Low This indicates the cylinder number of the sector to be transferred L 0 In LBA mode this register contains LBA bits 8 15 Low 16 23 High L 1 H This indicates the head number of the sector to be transferred L 0 In LBA mode ...

Page 175: ...tes the cylinder number of the transferred sector L 0 In LBA mode this register contains current LBA bits 8 15 Low 16 23 High L 1 H This indicates the head number of the transferred sector L 0 In LBA mode this register contains current LBA bits 24 27 L 1 The device internally uses 52 bytes of ECC data on all data written or read from the disk The 4 byte mode of oper ation is provided via an emulat...

Page 176: ...er contains LBA bits 8 15 Low 16 23 High L 1 H This indicates the head number of the sector to be transferred L 0 In LBA mode this register contains LBA bits 24 27 L 1 Input parameters from the device Sector Count This indicates the number of requested sectors not transferred This number is zero unless an unrecoverable error occurs Sector Number This indicates the sector number of the transferred ...

Page 177: ...w This indicates the cylinder number of the transferred sector L 0 In LBA mode this register contains current LBA bits 8 15 Low 16 23 High L 1 H This indicates the head number of the transferred sector L 0 In LBA mode this register contains current LBA bits 24 27 L 1 ...

Page 178: ...BA 7 0 Sector Number Previous LBA 31 24 Cylinder Low Current LBA 15 8 Cylinder Low Previous LBA 39 32 Cylinder High Current LBA 23 16 Cylinder High Previous LBA 47 40 Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low Data Low Data High Data High Feature Current Error see below Previous Sector Count Current V V V V V V V V Sector...

Page 179: ... HOB 1 LBA 31 24 of the address of the first unrecoverable error Cylinder Low HOB 0 LBA 15 8 of the address of the first unrecoverable error Cylinder Low HOB 1 LBA 39 32 of the address of the first unrecoverable error Cylinder High HOB 0 LBA 23 16 of the address of the first unrecoverable error Cylinder High HOB 1 LBA 47 40 of the address of the first unrecoverable error ...

Page 180: ...he native max LBA bits 8 15 Low and bits 16 23 High L 1 In CHS mode this register contains the native max cylinder number L 0 H In LBA mode this register contains the native max LBA bits 24 27 L 1 In CHS mode this register contains the native maximum head number L 0 Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Erro...

Page 181: ...x address Cylinder High HOB 1 LBA 47 40 of the address of the Native max address Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low Data Low Data High Data High Feature Current Error see below Previous Sector Count Current Sector Count HOB 0 Previous HOB 1 Sector Number Current Sector Number HOB 0 V V V V V V V V Previous HOB 1 V...

Page 182: ...s the head number of the first sector to be transferred L 0 In LBA mode this register contains the LBA bits 24 27 L 1 R This is the retry bit but this bit is ignored Input parameters from the device Sector Count This is the number of requested sectors not transferred This will be zero unless an unre coverable error occurs Sector Number This is the sector number of the last transferred sector L 0 I...

Page 183: ...is the cylinder number of the last transferred sector L 0 In LBA mode this register contains the current LBA bits 8 15 Low and bits 16 23 High L 1 H This is the head number of the last transferred sector L 0 In LBA mode this register contains the current LBA bits 24 27 L 1 ...

Page 184: ...nder Low Current LBA 15 8 Cylinder Low Previous LBA 39 32 Cylinder High Current LBA 23 16 Cylinder High Previous LBA 47 40 Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low Data Low Data High Data High Feature Current Error see below Previous Sector Count Current V V V V V V V V Sector Count HOB 0 Previous V V V V V V V V HOB 1 ...

Page 185: ... HOB 1 LBA 31 24 of the address of the first unrecoverable error Cylinder Low HOB 0 LBA 15 8 of the address of the first unrecoverable error Cylinder Low HOB 1 LBA 39 32 of the address of the first unrecoverable error Cylinder High HOB 0 LBA 23 16 of the address of the first unrecoverable error Cylinder High HOB 1 LBA 47 40 of the address of the first unrecoverable error ...

Page 186: ... is set to one and the Command Completion Time Limit expires the device shall stop execution of the command and pro vide ending status with BSY bit cleared to zero the SE bit set to one the ERR bit cleared to zero and report the fact that the Command Completion Time Limit expired by setting the CCTO bit in the error log to one In all cases the device shall attempt to transfer the amount of data re...

Page 187: ... next read stream command with the same Stream ID may not be sequential in LBA space HSE bit4 HSE Handle Stream Error specifies that this command starts at the LBA of the last reported error for this stream so the device may attempt to continue its cor responding error recovery sequence where it left off earlier Stream ID bit 0 2 Stream ID specifies the stream to be read The device shall operate a...

Page 188: ...r shall be set to one if an error has occurred during the execution of the command and the RC bit is set to one In this case the LBA returned in the Sector Number registers shall be the address of the first sector in error and the Sector Count registers shall contain the number of consecutive sectors that may contain errors If the RC bit is set to one when the command is issued and ICRC UNC IDNF A...

Page 189: ...the Command Completion Time Limit expires the device shall stop execution of the command and pro vide ending status with BSY bit cleared to zero the SE bit set to one the ERR bit cleared to zero and report the fact that the Command Completion Time Limit expired by setting the CCTO bit in the error log to one In all cases the device shall attempt to transfer the amount of data requested within the ...

Page 190: ...ream command with the same Stream ID may not be sequential in LBA space HSE bit4 HSE Handle Stream Error specifies that this command starts at the LBA of the last reported error for this stream so the device may attempt to continue its corresponding error recovery sequence where it left off earlier Stream ID bit 0 2 Stream ID specifies the stream to be read The device shall operate according to th...

Page 191: ...r has occurred during the execution of the command and the RC bit is set to one In this case the LBA returned in the Sector Number registers shall be the address of the first sector in error and the Sector Count registers shall contain the number of consecutive sectors that may contain errors If the RC bit is set to one when the command is issued and a UNC IDNF ABRT or CCTO error occurs the SE bit...

Page 192: ...6 23 High L 1 H This is the head number of the first sector to be transferred L 0 In LBA mode this register contains the LBA bits 24 27 L 1 R This is the retry bit this bit is ignored Input parameters from the device Sector Count This is the number of requested sectors not verified This number will be zero unless an unrecoverable error occurs Sector Number This is the sector number of the last tra...

Page 193: ...is the cylinder number of the last transferred sector L 0 In LBA mode this register contains the current LBA bits 8 15 Low and bits 16 23 High L 1 H This is the head number of the last transferred sector L 0 In LBA mode this register contains the current LBA bits 24 27 L 1 ...

Page 194: ...umber Previous LBA 31 24 Cylinder Low Current LBA 15 8 Cylinder Low Previous LBA 39 32 Cylinder High Current LBA 23 16 Cylinder High Previous LBA 47 40 Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low Data Low Data High Data High Feature Current Error see below Previous Sector Count Current V V V V V V V V Sector Count HOB 0 Pr...

Page 195: ... HOB 1 LBA 31 24 of the address of the first unrecoverable error Cylinder Low HOB 0 LBA 15 8 of the address of the first unrecoverable error Cylinder Low HOB 1 LBA 39 32 of the address of the first unrecoverable error Cylinder High HOB 0 LBA 23 16 of the address of the first unrecoverable error Cylinder High HOB 1 LBA 47 40 of the address of the first unrecoverable error ...

Page 196: ...Register Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Error see below Sector Count Sector Count Sector Number Sector Number Cylinder Low Cylinder Low Cylinder High Cylinder High Device Head 1 1 D Device Head Command 0 0 0 1 Status see below Error Register Status Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 CRC UNC 0 ID...

Page 197: ...ty Disable Password command The device will compare the password sent from this host with that specified in the control word Identifier Zero indicates that the device should check the supplied password against the user pass word stored internally One indicates that the device should check the given password against the master password stored internally Command Block Output Registers Command Block ...

Page 198: ... is to prevent accidental erasure of the device This command does not request the transfer of data Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Error see below Sector Count Sector Count Sector Number Sector Number Cylinder Low Cylinder Low Cylinder High Cylinder High Device Head 1 1 D Device Head Command 1 1 1 1 0 ...

Page 199: ...e feature device lock func tion After the completion of this command all the user data will be initialized to zero with a write operation At this time the data write is not verified with a read operation to determine if the data sector is initialized correctly At this time the defective sector information and the reassigned sector information for the device are not updated The security erase prepa...

Page 200: ...isables the security mode feature device lock function however the master password is still stored internally within the device and may be reactivated later when a new user password is set If you execute this command when disabling the security mode feature device lock function the password sent by the host is NOT compared with either the Master Password or the User Password The device then erases...

Page 201: ...ted when the device is in frozen mode Security Set Password Security Unlock Security Disable Password Security Erase Unit Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Error see below Sector Count Sector Count Sector Number Sector Number Cylinder Low Cylinder Low Cylinder High Cylinder High Device Head 1 1 D Device ...

Page 202: ...ommand Table 140 Security Set Password Information Identifier Zero indicates that the device should check the supplied password against the user password stored internally One indicates that the device should check the given password against the master password stored internally Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data...

Page 203: ...el bits The setting of the Identifier and Security level bits interact as follows Identifier User Security level High The password supplied with the command will be saved as the new user password The security mode feature lock function will be enabled from the next power on The drive may then be unlocked by either the user password or the previously set master password Identifier Master Security l...

Page 204: ...or each password mismatch When this counter reaches zero all password protected commands are rejected until there is a hard reset or a power off Identifier A zero indicates that the device regards Password as the User Password A one indicates that the device regards Password as the Master Password The user can detect if the attempt to unlock the device has failed due to a mismatched password since...

Page 205: ...ameters from the device Sector Number In LBA mode this register contains the current LBA bits 0 7 L 1 Cylinder High Low In LBA mode this register contains the current LBA bits 8 15 Low and bits16 23 High L 1 H In LBA mode this register contains the current LBA bits 24 27 L 1 Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Fea...

Page 206: ... released Output parameters to the device D Selected device Input parameters from the device Input from the device as a result of a Service command are described in the command description for the command for which Service is being requested Command Block Output Registers Register 7 6 5 4 3 2 1 0 Data Feature Sector Count Sector Number Cylinder Low Cylinder High Device Head 1 1 D Command 1 1 1 1 0...

Page 207: ... Status Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 CRC UNC 0 IDN 0 ABT T0N AMN BSY RDY DF DSC DRQ COR IDX ERR 0 0 0 0 0 V 0 0 0 V 0 0 V 02H Enable write cache 03H Set transfer mode based on value in sector count register 05H Enable Advanced Power Management 06H Enable Power up in Standby feature set 07H Power up in Standby feature set device spin up 09H Enable Address Offset mode 42H Enable Automati...

Page 208: ...is 05h Enable Advanced Power Management the Sector Count Register specifies the Advanced Power Management level The idle time to Low power idle mode and Low RPM standby mode vary according to the value in Sector Count register as follows When Low power idle mode is the deepest Power Saving mode DDH Disable release interrupt Write cache Enable ECC bytes 4 bytes Read look ahead Enable Reverting to p...

Page 209: ...ized with a hard soft reset unless Reverting to Power on defaults is disabled and the devise receives a soft reset 12 41 3 1 Low Power Idle mode Additional electronics are powered off and the heads are unloaded on the ramp The spindle is still rotated at the full speed 12 41 3 2 The heads are unloaded on the ramp and the spindle is rotated at the 60 65 of the full speed When Feature register is 85...

Page 210: ...d word 104 for PIO A value of zero indicates that the host interface shall be capable of transferring data at the maximum rate allowed by the selected transfer mode The Typical PIO Mode Host Interface Sector Time includes the host s interrupt service time Sector Count Typical PIO Mode Host Interface Sector Time 7 0 LBA Low Typical PIO Mode Host Interface Sector Time 15 8 LBA Mid Typical DMA Mode H...

Page 211: ...il the next power on or hardware reset The device returns command aborted during Set Max Locked mode or Set Max Frozen mode After a successful command completion Identify Device response words 61 60 shall reflect the maximum address set with this command If the 48 bit Address feature set is supported the value placed in Identify Device response words 103 100 shall be the same as the value placed i...

Page 212: ...de this register is ignored L 0 Cylinder High Low In LBA mode this register contains LBA bits 8 15 Low 16 23 High which is to be set L 1 In CHS mode this register contains cylinder number which is to be set L 0 H In LBA mode this register contains LBA bits 24 27 which is to be set L 1 In CHS mode this register is ignored L 0 Input parameters from the device Sector Number In LBA mode this register ...

Page 213: ... accepts this command the device is in Set_Max_Unlocked state Table 147 Set Max Set Password data contents Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature 0 0 0 0 0 0 0 1 Error see below Sector Count Sector Count Sector Number Sector Number Cylinder Low Cylinder Low Cylinder High Cylinder High Device Head 1 1 D Device...

Page 214: ...ted The device remains in this state until a power cycle or the acceptance of a Set Max Unlock or Set Max Freeze Lock command Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature 0 0 0 0 0 0 1 0 Error see below Sector Count Sector Count Sector Number Sector Number Cylinder Low Cylinder Low Cylinder High Cylinder High Devic...

Page 215: ...itially set to 5 and is decremented for each password mismatch When this counter reaches zero all Set Max Unlock commands are rejected until a hard reset or a power off occurs If the password compare matches the device sets the Set_Max_Unlocked state and all Set Max commands are accepted Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 ...

Page 216: ...ected The following commands are disabled by Set Max Freeze Lock Set Max Address Set Max Set PASSWORD Set Max Lock Set Max Unlock Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature 0 0 0 0 0 0 1 0 Error see below Sector Count Sector Count Sector Number Sector Number Cylinder Low Cylinder Low Cylinder High Cylinder High D...

Page 217: ...nd or the device is in the Set Max Locked or Set Max Frozen state the device shall return command aborted If the device in Address Offset mode receives this command with the nonvolatile option the device returns aborted error to the host The device returns the command aborted for a second non volatile Set Max Address Ext command until next power on or hardware reset Command Block Output Registers ...

Page 218: ... is not valid when the device is in Address Offset mode Sector Number Current Set Max LBA 7 0 Sector Number Previous Set Max LBA 31 24 Cylinder Low Current Set Max LBA 15 8 Cylinder Low Previous Set Max LBA 39 32 Cylinder High Current Set Max LBA 23 16 Cylinder High Previous Set Max LBA 47 40 Input parameters from the device Sector Number HOB 0 Set Max LBA 7 0 Sector Number HOB 1 Set Max LBA 31 24...

Page 219: ...indicates the block size to be used for the Read Multiple and the Write Multiple com mands Valid block sizes can be selected from 0 1 2 4 8 or 16 If 0 is specified then the Read Multiple and the Write Multiple commands are disabled Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Error see below Sector Count V V V V V ...

Page 220: ...set is the only way to recover from Sleep Mode Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Error see below Sector Count Sector Count Sector Number Sector Number Cylinder Low Cylinder Low Cylinder High Cylinder High Device Head 1 1 D Device Head Command 1 1 1 0 0 1 1 0 Status see below Error Register Status Registe...

Page 221: ... T Read Attribute Values subcommand from the host the device saves any updated Attribute Values to the Attribute Data sectors and then transfer the 512 bytes of Attribute Value information to the host Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature V V V V V V V V Error see below Sector Count V V V V V V V V Sector Co...

Page 222: ...command will not change the current Autosave status However the device will respond with the error code specified in Table 166 S M A R T Error Codes on page 220 The S M A R T Disable Operations subcommand disables the Autosave feature along with the S M A R T opera tions of the device Upon the receipt of the subcommand from the host the device asserts BSY enables or disables the Autosave fea ture ...

Page 223: ... Log Sector command the device shall return command aborted 12 46 1 7 S M A R T Write Log Sector subcommand D6h This command writes 512 bytes of data to the specified log sector The 512 bytes of data are transferred at a command and the Sector Count value shall be set to one The Sector Number shall be set to specify the log sector address as shown above If a Read Only log sector is specified the d...

Page 224: ...ny updated Pre failure type Attribute Values to the reserved sector and compares the updated Attribute Values to the Attribute Thresholds If the device does not detect a Threshold Exceeded Condition the device loads 4Fh into the Cylinder Low register and C2h into the Cylinder High register If the device detects a Threshold Exceeded Condition the device loads F4h into the Cylinder Low register and ...

Page 225: ...following defines the 12 bytes that make up the information for each Attribute entry in the Device Attribute Data Structure Table 156 Individual Attribute Data Structure Description Byte Offset Value Data Structure Revision Number 2 00h 0010h 1st Device Attribute 12 02h 30th Device Attribute 12 15Eh Off line data collection status 1 16Ah Self test execution status 1 16Bh Total time in seconds to c...

Page 226: ...testing 1 The attribute value is updated during On line testing or during both On line and Off line testing 2 5 Vendor specific 6 15 Reserved 0 Normalized values The device performs conversion of the raw Attribute Values to transform them into normal ized values which the host can then compare with the Threshold values A Threshold is the excursion limit for a normalized Attribute Value ID Attribut...

Page 227: ...ition 0 Execute Off line Immediate implemented bit 0 S M A R T Execute Off line Immediate subcommand is not implemented 1 S M A R T Execute Off line Immediate subcommand is implemented 1 Enable disable Automatic Off line implemented bit 0 S M A R T Enable disable Automatic Off line subcommand is not implemented 1 S M A R T Enable disable Automatic Off line subcommand is implemented Bit Definition ...

Page 228: ...UTE AUTOSAVE command Bit Definition 0 Pre power mode attribute saving capability If bit 1 the device will save its Attribute Values prior to going into a power saving mode Standby or Sleep mode 1 Attribute Autosave capability If bit 1 the device supports the S M A R T ENABLE DISABLE ATTRIBUTE AUTOSAVE command 2 15 Reserved 0 12 46 2 8 Error logging capability Bit Definition 7 1 Reserved 0 0 The Er...

Page 229: ...idual Threshold Data Structure are in the same order and correspond to the entries in the Individual Attribute Data Structure 12 46 3 3 Attribute ID Numbers Attribute ID Numbers supported by the device are the same as Attribute Values Data Structures 12 46 3 4 Attribute Threshold These values are preset at the factory and are not meant to be changeable 12 46 3 5 Data Structure Checksum The Data St...

Page 230: ...og sector 12 46 5 1 S M A R T error log version This value is set to 01h 12 46 5 2 Error log pointer This points to the most recent error log data structure Only values 1 through 5 are valid 12 46 5 3 Device error count This field contains the total number of errors The value will not roll over Description Byte Offset S M A R T Logging Version 2 00h Number of sectors in the log at log address 1 1 ...

Page 231: ... command data structure 12 18h 4th command data structure 12 24h 5th command data structure 12 30h Error data structure 30 3Ch 90 Description Byte Offset Device Control register 1 00h Features register 1 01h Sector count register 1 02h Sector number register 1 03h Cylinder Low register 1 04h Cylinder High register 1 05h Device Head register 1 06h Command register 1 07h Time stamp ms from Power On ...

Page 232: ...re is capable to contain up to 21 descriptors After 21 descriptors has been recorded the oldest descriptor will be overwritten with the new descriptor The self test log index points to the most recent descriptor When there is no descriptor the value is 0 When there are one or more descriptors the value is 1 through 21 Value State x0h Unknown x1h Sleep x2h Standby x3h Active Idle x4h S M A R T Off ...

Page 233: ...arting LBA for test span 1 8 02h R W Ending LBA for test span 1 8 0Ah R W Starting LBA for test span 2 8 12h R W Ending LBA for test span 2 8 1Ah R W Starting LBA for test span 3 8 22h R W Ending LBA for test span 3 8 2Ah R W Starting LBA for test span 4 8 32h R W Ending LBA for test span 4 8 3Ah R W Starting LBA for test span 5 8 42h R W Ending LBA for test span 5 8 4Ah R W Reserved 256 52h Reser...

Page 234: ...d into the Cylinder High and Cylin der Low registers 51h 04h A S M A R T FUNCTION SET command was received by the device with a subcommand value in the Features Register that is either invalid or not supported by this device 51h 04h A S M A R T FUNCTION SET command subcommand other than S M A R T ENABLE OPERATIONS was received by the device while the device was in a S M A R T Disabled state 51h 04...

Page 235: ...tic power down sequence is enabled The time out interval is shown below When the automatic power down sequence is enabled the device will enter the Standby mode automatically if the time out interval expires with no device access from the host The time out interval will be reinitialized if there is a drive access before the time out interval expires Command Block Output Registers Command Block Inp...

Page 236: ...delay while waiting for the spindle to reach operating speed The Standby Immediate command will not affect the auto power down time out parameter Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Error see below Sector Count Sector Count Sector Number Sector Number Cylinder Low Cylinder Low Cylinder High Cylinder High D...

Page 237: ...tial Write Buffer and Read Buffer commands access the same 512 byte within the buffer Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Error see below Sector Count Sector Count Sector Number Sector Number Cylinder Low Cylinder Low Cylinder High Cylinder High Device Head 1 1 D Device Head Command 1 1 1 0 1 0 0 0 Status ...

Page 238: ... sector to be transferred L 0 In LBA mode this reg ister contains the LBA bits 8 15 Low and bits 16 23 High L 1 H This indicates the head number of the first sector to be transferred L 0 In LBA mode this register contains the LBA bits 24 27 L 1 R This indicates the retry bit This bit is ignored Input parameters from the device Sector Count This indicates the number of requested sectors not transfe...

Page 239: ...es the cylinder number of the last transferred sector L 0 In LBA mode this register contains the current LBA bits 8 15 Low and bits 16 23 High L 1 H This indicates the head number of the last transferred sector L 0 In LBA mode this register contains the current LBA bits 24 27 L 1 ...

Page 240: ...rder bits 15 8 If zero is specified in the Sector Count register 65 536 sectors will be transferred Sector Number Current LBA 7 0 Sector Number Previous LBA 31 24 Cylinder Low Current LBA 15 8 Cylinder Low Previous LBA 39 32 Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low Data Low Data High Data High Feature Current Error see ...

Page 241: ...nrecoverable error Sector Number HOB 1 LBA 31 24 of the address of the first unrecoverable error Cylinder Low HOB 0 LBA 15 8 of the address of the first unrecoverable error Cylinder Low HOB 1 LBA 39 32 of the address of the first unrecoverable error Cylinder High HOB 0 LBA 23 16 of the address of the first unrecoverable error Cylinder High HOB 1 LBA 47 40 of the address of the first unrecoverable ...

Page 242: ...mber or LBA address bits 23 8 H Starting head number or LBA address bits 27 24 Input parameters from the device on bus release Sector Count Bits 7 3 Tag contain the Tag of the command being bus released Bit 2 REL is set to one Bit 1 I O is cleared to zero Bit 0 C D is cleared to zero Sector Number Cylinder High Low H n a SRV Cleared to zero when the device performs a bus release This bit is set to...

Page 243: ...mplete Sector Count Bits 7 3 Tag contain the Tag of the completed command Bit 2 REL is cleared to zero Bit 1 I O is set to one Bit 0 C D is set to one Sector Number Cylinder High Low H Sector address of unrecoverable error applicable only when an unrecoverable error has occurred SRV Cleared to 0 ...

Page 244: ...for the command being delivered Sector Number Current LBA 7 0 Sector Number Previous LBA 31 24 Cylinder Low Current LBA 15 8 Cylinder Low Previous LBA 39 32 Cylinder High Current LBA 23 16 Cylinder High Previous LBA 47 40 Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low Data Low Data High Data High Feature Current V V V V V V V...

Page 245: ...ro Sector Number HOB 0 LBA 7 0 of the address of the first unrecoverable error applicable only when an unrecoverable error has occurred Sector Number HOB 1 LBA 31 24 of the address of the first unrecoverable error applicable only when an unrecoverable error has occurred Cylinder Low HOB 0 LBA 15 8 of the address of the first unrecoverable error applicable only when an unrecoverable error has occur...

Page 246: ...t sector of the log to be written low order bits 7 0 Cylinder Low Previous The first sector of the log to be written high order bits 15 8 If the feature set associated with the log specified in the Sector Number register is not supported or enabled or if the values in the Sector Count Sector Number or Cylinder Low registers are invalid the device shall return com mand aborted If the host attempts ...

Page 247: ...his indicates the cylinder number of the sector to be transferred L 0 In LBA mode this register contains the LBA bits 8 15 Low and bits 16 23 High L 1 H This indicates the head number of the sector to be transferred L 0 In LBA mode this register contains the LBA bits 24 27 L 1 R The retry bit This bit is ignored Input parameters from the device Sector Count This indicates the number of requested s...

Page 248: ...ector to be transferred L 0 In LBA mode this register contains current the LBA bits 24 27 L 1 The drive internally uses 52 bytes of ECC on all data read or writes The 4 byte mode of operation is provided by means of an emulation technique As a consequence of this emulation it is recommended that 52 byte ECC mode be used for all tests to confirm the operation of the ECC hardware of the drive Unexpe...

Page 249: ...r contains the LBA bits 8 15 Low and bits 16 23 High L 1 H This indicates the head number of the first sector to be transferred L 0 In LBA mode this register contains the LBA bits 24 27 L 1 Input parameters from the device Sector Count This indicates the number of requested sectors not transferred The Sector Count will be zero unless an unrecoverable error occurs Sector Number This indicates the s...

Page 250: ...es the cylinder number of the last transferred sector L 0 In LBA mode this register contains the current LBA bits 8 15 Low and bits 16 23 High L 1 H This indicates the head number of the last transferred sector L 0 In LBA mode this register contains current the LBA bits 24 27 L 1 ...

Page 251: ...rent LBA 7 0 Sector Number Previous LBA 31 24 Cylinder Low Current LBA 15 8 Cylinder Low Previous LBA 39 32 Cylinder High Current LBA 23 16 Cylinder High Previous LBA 47 40 Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low Data Low Data High Data High Feature Current Error See below Previous Sector Count Current V V V V V V V V ...

Page 252: ... HOB 1 LBA 31 24 of the address of the first unrecoverable error Cylinder Low HOB 0 LBA 15 8 of the address of the first unrecoverable error Cylinder Low HOB 1 LBA 39 32 of the address of the first unrecoverable error Cylinder High HOB 0 LBA 23 16 of the address of the first unrecoverable error Cylinder High HOB 1 LBA 47 40 of the address of the first unrecoverable error ...

Page 253: ...tes the head number of the first sector to be transferred L 0 In LBA mode this register contains the LBA bits 24 27 L 1 R This indicates the retry bit this bit is ignored Input parameters from the device Sector Count This indicates the number of requested sectors not transferred This will be zero unless an unrecoverable error occurs Sector Number This indicates the sector number of the last transf...

Page 254: ...cates the cylinder number of the last transferred sector L 0 In LBA mode this register contains the current LBA bits 8 15 Low and 16 23 High L 1 H This indicates the head number of the last transferred sector L 0 In LBA mode this register contains the current LBA bits 24 27 L 1 ...

Page 255: ...15 8 Cylinder Low Previous LBA 39 32 Cylinder High Current LBA 23 16 Cylinder High Previous LBA 47 40 Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low Data Low Data High Data High Feature Current Error See below Previous Sector Count Current V V V V V V V V Sector Count HOB 0 Previous V V V V V V V V HOB 1 Sector Number Current...

Page 256: ... HOB 1 LBA 31 24 of the address of the first unrecoverable error Cylinder Low HOB 0 LBA 15 8 of the address of the first unrecoverable error Cylinder Low HOB 1 LBA 39 32 of the address of the first unrecoverable error Cylinder High HOB 0 LBA 23 16 of the address of the first unrecoverable error Cylinder High HOB 1 LBA 47 40 of the address of the first unrecoverable error ...

Page 257: ...he error log to one In all cases the device shall attempt to transfer the amount of data requested within the Command Completion Time Limit event if some data transferred is in error Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low Data Low Data High Data High Feature Current V V V V V V V Error See below Previous V V V V V V V...

Page 258: ...ccording to the Stream ID set by the Write Stream command Feature Previous CCTL 7 0 The time allowed for the current command s completion is calculated as follows Command Completion Time Limit content of the Feature register Previous Identify Device words 99 98 useconds If the value is zero the device shall use the Default CCTL supplied with a previous Configure Stream command for this Stream ID I...

Page 259: ...utive sectors that may contain errors If the WC bit is set to one when the command is issued and an ICRC UNC IDNF ABRT or CCTO error occurs the SE bit shall be set to one the ERR bit shall be cleared to zero and the bits that would normally be set in the Error register shall be set in the error log DWE Status bit 4 DWE Deferred Write Error shall be set to one if an error was detected in a deferred...

Page 260: ... amount of data requested within the Command Completion Time Limit event if some data transferred is in error Output Parameters To The Device Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low Data Low Data High Data High Feature Current V V V V V V V Error See below Previous V V V V V V V V Sector Count Current V V V V V V V V S...

Page 261: ...HSE bit4 HSE Handle Stream Error specifies that this command starts at the LBA of the last reported error for this stream so the device may attempt to continue its corresponding error recovery sequence where it left off earlier Stream ID bit 0 2 Stream ID specifies the stream being written The device shall operate according to the Stream ID set by the Write Stream command Feature Previous The time...

Page 262: ...ed SE Status bit 5 SE Stream Error shall be set to one if an error has occurred during the execution of the command and the WC bit is set to one In this case the LBA returned in the Sector Number registers shall be the address of the first sector in error and the Sector Count registers shall contain the number of consecutive sectors that may contain errors If the WC bit is set to one when the comm...

Page 263: ...1 31 sec Hard Reset Device Busy After Hard Reset Bus RESET Signal Asserted Status Register BSY 1 400 ns Device Ready After Hard Reset Bus RESET Signal Asserted Status Register BSY 0 and RDY 1 31 sec Data In Com mand Device Busy After Com mand Code Out OUT To Command Reg ister Status Register BSY 1 400 ns Interrupt DRQ For Data Transfer In Status Register BSY 1 Status Register BSY 0 and DRQ 1 Inter...

Page 264: ...tribute values 84 Attributes 84 Auto Reassign 95 Automatic Acoustic Management 98 B BSMI mark 65 C Cable noise interference 55 Cabling 43 Capacity formatted 11 Caution 3 CE mark 65 Check Power Mode E5h 98h 115 Command descriptions 111 Command overhead 14 Command protocol 105 Command Register 70 Command table 90 Configure Stream 51h 116 Connector location 23 47 Connector locations 58 Control electr...

Page 265: ...Reset considerations 79 DMA commands 109 DMA Data Transfer commands 109 DMA queued commands 110 Download Microcode 92h 122 Drive Address Register 72 Drive characteristics 11 Drive format 12 Drive ready time 16 E Electrical Interface 23 Electrical interface 23 Electromagnetic compatibility 65 Environment 52 64 Error log 85 Error Register 73 Error reporting 222 Execute Device Diagnostic 90h 123 Exte...

Page 266: ... Host Terminating Write DMA 42 Humidity 52 I Identification labels 63 Identify Device ECh 128 Idle E3h 97h 139 Idle Immediate E1h 95h 140 Initialize Device Parameters 91h 141 Initiating Write DMA 39 Input voltage 53 Interface capability for power modes 83 Interface connector 24 Interface logic signal levels 29 Interface specification 45 J Jumper pin assignment 48 Jumper pin identification 47 Jumpe...

Page 267: ...rientation 59 N Non data commands 108 NOP 00h 142 O Off line read scanning 84 Operating modes 19 description 17 Operating shock 61 Operating vibration 60 Operation example 87 Overlapped and queued feature 80 P Packaging 65 Passwords 87 Performance characteristics 14 Physical dimensions 56 PIO Data In commands 105 PIO Data Out Commands 106 PIO timings 32 Power consumption efficiency 54 Power manage...

Page 268: ...eferences 1 Register set 69 Registers 69 Reliability 55 Reset response 77 Reset timings 31 S S M A R T commands 84 S M A R T Function 84 Set 209 S M A R T Function Set 209 S M A R T Log Directory 218 Safety 64 Secondary circuit protection 64 Sector Addressing 80 Sector Addressing Mode 80 Sector Count Register 73 Sector Number Register 74 Security 86 Security Disable Password F3h 186 Security Disab...

Page 269: ...Standby E2h 96h 223 Standby Immediate 224 Standby timer 82 Start stop cycles 55 Status Register 74 Streaming commands 102 Streaming feature Set 101 Streaming Logs 103 Streaming Performance log 160 T Temperature 52 Terminology 67 Threshold exceeded condition 84 Throughput 18 Time out values 251 Timings multi word DMA 34 reset 31 Ultra DMA 35 U UL approval 64 Urgent bit 102 V Vibration 60 W Weight 5...

Page 270: ...Deskstar 7K400 Hard Disk Drive Specification Write cache 94 Write DMA 226 ...

Page 271: ...tered trade marks of their respective companies References in this publication to Hitachi Global Storage Technologies products programs or services do not imply that Hitachi Global Storage Technologies intends to make these available in all countries in which Hitachi Global Storage Technologies operates Product information is provided for information pur poses only and does not constitute a warran...

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