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Hitachi AP1, Data Book

The Hitachi AP1 Data Book is a comprehensive manual designed to assist users with the correct operation and maintenance of their Hitachi AP1 products. Available for free download from manualshive.com, this user-friendly manual provides detailed instructions and troubleshooting tips, ensuring optimal performance and longevity of your device.

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Summary of Contents for AP1

Page 1: ... HITACHI AP1 4 BIT SINGLE CHIP MICROCOMPUTER DATA BOOK ...

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Page 3: ... AP 1 4 BIT SINGLE CHIP MICROCOMPUTER DATABOOK HITACHI ...

Page 4: ... keep the following in mind 1 This manual may wholly or partially be subject to change without notice 2 All rights reserved No one is permitted to reproduce or duplicate in any form the whole or part ofthis manual without Hitachi s permission 3 Hitachi will not be responsible for any damage to the user that may result from accidents or any other reasons during operation of his unit according to th...

Page 5: ... HMCS46C HD44840 HMCS46CL HD44848 82 HMCS47C HD44860 HMCS47CL HD44868 108 4 bit Single chip Microcomputer HMCS40 Series Liquid Crystal Display Driving Type LCD III HD44790 HD44795 137 LCD IV HD613901 174 4 bit Single chip Microcomputer HMCS400 Series HMCS404C HD614042 221 HD614P080S 258 Evaluation Chip for 4 bit Single chip Microcomputers HD44850E 292 HD44857E 293 HD44797E 294 NEW DEVICES HMCS404A...

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Page 7: ...GENERAL INFORMATION Quick Reference Guide Introduction of Packages Quality Assurance Reliability Test Data Design Procedure and Support Tools for 8 bit Single chip Microcomputers ...

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Page 9: ...ete Input Output 1 x 16 External 2 Interrupts Timer Counter 1 Instructions Number of Instructions 71 Cycle Time u ts 20 10 Built in Clock Pulse Generator Power on Reset No Yes Battery Back up Halt Evaluation Chip HD44850E HD44857E Reference Page 174 Wide Temperature Range 40 to 85 C version is available except LCD IV 2 Pattern Memory 3 LCD DRIVE FUNCTION Common 4 LCD Segment 32 Drive Duty Static 1...

Page 10: ...Vcc 0 3 20to 75 20 to 75 20to 75 20to 75 DP 42 Dp 42S FP 54 DP 64S FP BO FP BO 4 096 x 10 4 096 x 10 2 048 x 10 4 096 x 10 128 X 10d 256x4 256 x 4 160x4 256x4 8 6 6 6 4 4 4 4 4x1 4x1 4x1 4x1 4x1 32 44 32 32 4x4 4 6 4x2 4x 1 x 16 1 x 16 1 x 16 1 x 16 2 2 2 2 1 1 1 1 71 71 71 71 20 5 20 5 20 10 20 5 Yes NolYes NolYes Yes No Halt Halt Halt Halt HD44857E HD44857E HD44797E HD44797E 218 244 273 310 8 ...

Page 11: ...4096 x 10 4096 x 10 o8 192 word x 10 bit with standard EPROM 27128 RAM bits 256x4 256 x 4 256x4 576x4 Registers 7 7 7 7 Stack Registers 16 16 16 16 l 4xl 4xl 4xl 4xl 0 4 Bit Input 2xl 2 xl 2 xl 2xl c 4 Bit Output 4x4 I I O Ports 58 IL 58 4x4 58 4x4 58 4x4 4 Bit Input Output 4x5 4x5 4x5 4x5 l Bit Input Output 1 x 16 1 x 16 1 x 16 1 x 16 External 2 2 2 2 Interrupts Timer Counter 2 2 2 2 Serial Inter...

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Page 13: ...rtion Type Surface Mounting Type Multi function Type DIP DUAL IN LINE PACKAGE S DIP SHRINK DUAL IN LINE PACKAGE PGA PIN GRID ARRAY FLAT DIP FLAT DUAL IN LINE PACKAGE FLAT QUIP FLAT QUAD IN LINE PACKAGE CC CHIP CARRIER SOP SMALL OUTLINE PACKAGE FPP FLAT PLASTIC PACKA GE PLCC PLASTIC LEADED CH1P CARRIER LCC LEADLESS CHIP CARRI ER Plastic DIP Ceramic DIP Shrink Type Plastic DIP Shrink Type Ceramic DI...

Page 14: ...ication follows illustrated in the data sheet of each device When ordering please write the package code next to the type number HDxxxxxS T Package Code Indication Note HDXXXPXXXX stands for Type No of EPROM on the package type microcomputer device Package Classification HMCS40 Series No Indication Plastic DIP S Shrink Type Plastic DIP HMCS400 Series F FPP P Plastic DIP S Shrink Type Plastic DIP D...

Page 15: ...classification Standard outline DIP Pin insertion type Shrink outline S DIP FPP Surface mounting type Flat package FPC Multi function type EPROM on the package type Plntie DIP OP 28 051 h1 51_ 0 15 k O 20 0 31 DP 42 13 4 21 22 H 1l0 1 13 Package material Package code Plastic DP 28 DP 42 DP 28S Plastic DP 42S DP 64S FP 54 Plastic Fp 64 Fp 80 FP 100 Ceramic FC 80 Ceramic DC 64SP Unit mml Unit mm ...

Page 16: ...INTRODUCTION OF PACKAGES Shrink Type PII tic DIP DP 28S B B 5 1 mix 14 Unit mm DP 42S 140 11 1 miX I 0 21 22 Unit mm 14 ...

Page 17: ... INTRODUCTION OF PACKAGES DP 64S Unit mm IFlat Plastic Package I FP 54 Unit mm Unit mml 15 ...

Page 18: ...INTRODUCTION OF PACKAGESs FP IO FP 100 IFlat Package of Ceramic I Fe 80 28 0 0 5 2 9mB 2 5I1111X 0 2 to 0 38 16 Unit mm Unit mm Unit mm ...

Page 19: ...aging material and type Fig 2 lists the adjustment of the reflowing furnace for FPP Pre heat the furnace to 1500 C Sur face temperature of the resin should be kept at 2350 C maximum for JO minutes or less I The temperature of the leads should be kept at 260 for 10 minutes or less 2 The temperature of the resin should be kept at 2350 for 10 minutes or less 3 Below is shown the temperature profile w...

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Page 21: ...g process 4 End user manufacturing techniques 5 Quality control and screening test methods 6 Reliability target of system 2 2 Reliability Design The following steps are taken to meet the reliability targets 1 Design Standardization As for design rules critical items pertaining to quality and reliability are always studied at circuit 19 2 Device Design It is important for the device deSign to consi...

Page 22: ...back of information is used to insure a satis factory level of ability process Quality control is accomplished through division of functions jn manufacturing quality assurance and other related departments The total function flow is shown in Fig 2 The main points are described below 3 2 Quality Appl OVl ll To insure quality and reliability quality approval is carried out at the preproduction stage...

Page 23: ... Inspection on Appaarance and Electrical Characteristics Reliability Test r Quality Information I I Claim Field Experience I General Quality Information I QUALITY ASSURANCE Method Lot Sampling Confirmation of Quality Level Confirmation of Quality Level Lot Sampling Confirmation of Quality Level Telting Inspection Confirmation of Quality Level Lot Sampling Feedback of Information Fig re 2 Flow Char...

Page 24: ...lding Performance Mounting Char_risties 22 3 3 2 Inner Process Quality Control InnerProcessQualityControl performsvery important functions in quality assurance of semiconductor devices The manufacturing Inner Process Quality Control is shown in Fig 3 1 Quality Control of Semi final Products and Final Products Potential failure factors of semiconductor devices are removed in the manufacturing proce...

Page 25: ...ssembling Pac Lot Judgement Sealing pac Level Check Final Electrical Inspection Failure Analysis Appearance Inspection Sampling Inspection on Products Receiving Shipment Wafer Oxidation Photo Resist Diffusion Evapora tion Wafer Chip Characteristics Appearance Appearance Thickness of Oxide Film Dimension Appearance Diffusion Depth Sheet Resistance Gate Width Characteristics of Oxide Film Breakt own...

Page 26: ...irm that the products have met the users requirements but also to consider potential 2 Reliability Assurance Tests Report Quality Assurance Dept Report To assure the reliability of semiconductor devices reliability tests and tests on individual manufac turing lots that are required by the user are peri odically performed Failure Analysis Countermeasure Execution of Countermeasure Follow up and Con...

Page 27: ...ND CHIP STRUCTURE 2 1 Packaging Production output and application ofplastic packaging con tinues to increase expanding to automobile measuring and con trol systems and computer terminal equipment operating under severe conditions To meet this demand Hitachi has significantly improved moisture resistance and operational stability in the plastic manufacturing process Plastic and side brazed ceramic ...

Page 28: ... Table 2 Reliability Test Methods Test Items Test Condition MIL STD 883B Method No Operating Life Test 12SoC 1000hr looS 2 High Temp Storage Tstg max 1000hr 1 008 1 Low Temp Storage Tstg min l000hr Steady State Humidity 6SoC 9S RH l000hr Steady State H midity Biased 8SoC 8S RH l000hr Temperature Cycling SSoC 150 C 10 cycles 1010 4 Temperature Cycling 20 C 12SoC 2oo cycles Thermal Shock O C 100 C 1...

Page 29: ...le 4 High Temperature High Humidity Test Moisture Resistance Test 1 85 C 85 RH Bias Test Package 168 hrs 500 hrs DIP type 0 205 0 205 FP type 0 185 0 185 Condition C MOS VCC 5 5V 2 High Temperature High Humidity Storage Life Test a 65 C 95 RH Package 168 hrs 500 hrs DIP type 0 870 0 870 FP type 0 545 0 545 1000 hrs 1 205 1 185 1000 hrs 1 870 1 545 27 Component Hours Failure 90000 0 90000 0 90000 0...

Page 30: ...cling Test _55 C 150 C Package 10 cycles DIP type 0 1637 FP type 0 1514 500hrs 1000 hrs 0 220 1 220 0 165 1 165 60hrs 100 hrs 0 55 0 55 0 55 0 55 20 cycles 40 cycles 0 50 0 50 0 22 0 22 100 cycles 200 cycles 0 1637 0 1637 0 1514 0 1514 Table 8 High Temperature Low Temperature Storage Life Test Package Temperature 168 hrs 500 hrs DIP type 150 C 0 43 0 43 55 C 0 50 0 50 FP type 150 C 0 53 0 53 _55 C...

Page 31: ...s Soldering Heat 260 C 10 sec 140 0 160 0 Salt Water Spray 35 C NaCI 5 40 0 40 0 24 hrs Solderability 230 C 5 sec 34 0 34 0 Rosin flux Drop Test 75cm maple board 38 0 38 0 3 times Mechanical Shock 1500G 0 5ms 45 0 45 0 3 times X Y Z Vibration Fatigue 60 Hz 20G 120 0 45 0 32hrs X Y Z Vibration Variable Freq 100 2oooHz 45 0 45 0 20G 4 times X Y Z 225g 90 45 0 Lead Integrity Bonding 3 times 225g 90 4...

Page 32: ...belt conveyor is used apply some surface treatment to prevent build up of electrical charge 4 Minimize mechanical vibration and shock when trans porting semiconductor devices or printed circuit boards 30 4 3 Handling for Measurement Avoid static electricity noise and voltage surge when meas uring or mounting devices Precaution should be taken against current leakage through terminals and housings ...

Page 33: ...he RAM before the programming A flow chart is designed to achieve the predetermined functions and the flow chart is coded by using the mnemonic code The coded flow chart is punched into the card or the paper tape or written into the floppy disk to generate a source program The source program is assembled by the evaluation kit or the H68SD5 to generate the object program In this case errors during ...

Page 34: ...ith Evaluation Kit 3 Croll AlI8mbler Is Supplied with Emulator 4 MDS I a regls red trade mark of Mohorwk Data Science Corp ISIS II is a regl red trade mark of Intel Corp CP M I a registered trade mark of Digital Re arch Inc EXORcl r I a regl red trade mark of Motorola Inc H68SD5 Emulator IIt S IBM370 Hardwara Software H68SD5 H40MIX1 S40XAM1 T H68SD5 H40MIX 1 H68SD5 H40MIX2 S40XAM1 T H68SD5 H4OMIX4...

Page 35: ...available Features Supports system development for 8 bit and 4 bit single chip microcomputers System Configuration H68S05 33 DESIGN PROCEDURE AND SUPPORT TOOLS FOR 4 BIT SINGLE CHIP MICROCOMPUTERS 0 isk based low cost system Provides the CRT Editor Assembler Emulator and EPROM Writer controlled by FOOS III 56k byte RAM Allows linking between the H68S05 and the I O devices TTY and Printer Easy to d...

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Page 37: ...DATA SHEETS 4 BIT SINGLE CHIP MICROCOMPUTER HMCS40 SERIES ...

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Page 39: ...n new products Specifications and information are subject to change without notice Advance I formation data sheets herein contain information on a product under development Hitachi reserves the right to change or discontinue these products without notice ...

Page 40: ...s Timer Event Counter Instruction Cycle Time HMCS44C 10 ILs HMCS44CL 20 ILs All Instructions except One Instruction Single Word and Single Cycle BCD Arithmetic Instructions Pattern Generation Instruction Table Look Up Capability Powerful Interrupt Function 3 Interrupt Sources t2 External Interrupt Lines Timer Event Counter Multiple Interrupt Capability Bit Manipulation Instructions for Both RAM an...

Page 41: ... Interrupt NOTEl AS A4 r lJA o A J Instruction Decoder Jj I y Spy ddressillll e 0 AAM j 160 x4 bit 1 2 iii NOTE A4 and AS of the HMCS44C can be used as genaral purpose registen 39 i Irr it r l en CD CD lii L r I I I I I S I I I I I I 0 I it i B B I O Common f A o A I x x Do 0 0 0 0 0 Vee GNO f o r o f o AESET OSC OSC Power on Reset Circuit ACL is not built in HMCS44CL ...

Page 42: ...n pins Maximum Total Output Current 1 IOI 45 f t_ Maximum Total Output Current 2 lo2 45 Operating Temperature Topr 20 to 75 t_ Storage Temperature TSIQ 55 to 125 mA mA C C NOTE 3 NOTE 3 1NOTE 11 Permanent LSI damage may occur if maximum ratings are exceeded Normal operation should be under the conditions of ooELECTRICAL CHARACTERISTICS 1 _2 00 If these conditions are exceeded it could affect relia...

Page 43: ...ternal Clock Operation RIOsciliation Clock Oscillation Frequency RI 91kn 2 Clock Oscillation Frequency Ceramic Filter Circuit Instruction Cycle Time Tinst 4 fosc NOTE 1J All voltages are with respect to GND NOTE 2J This is applied to RESET HLT OSC1 INTo INTl and the With Pull up MOS or CMOS type of I O pins NOTE 3J This is applied to the Open Drain type of I O pins NOTE 4J This is applied to the C...

Page 44: ...All voltages are with respect to GND HMCS44CL ELECTRICAL CHARACTERISTICS Vcc 2 5 to 5 5V eABSOLUTE MAXIMUM RATINGS Item Symbol Value Unit Supply Voltage Vcc 0 3 to 7 0 V Value Unit min max 2 3 V 10 J lA 100 J lS 100 J ls 1000 J ls 1000 J lS 400 J ls 0 1 ms 4 0 1 10 ms 1 ms 1 ms 4 2 J lS Tinst 20 ms 20 ms Remarks Terminal Voltage 1 Vn 0 3 to Vcc 0 3 V Except for terminals specified by VT2 Terminal ...

Page 45: ...scillation R lS0kO 2 130 Clock Oscillation Frequency fose Vec 2 5 to 3 5V RI lS0kO 2 130 Vcc 2 5 to 5 5V Tinst 4 fosc 16 Instruction Cycle Time Tinst Vcc 2 5 to 3 5V Tinst 4 fosc 11 4 Vcc 2 5 to 5 5V INOTE 1 All voltages are with respect to GND INOTE 2 This is applied to RESET RLr OSC INTo INT and the With Pull up MOS or CMOS type of 1 0 pins INOTE 3 This is applied to the Open Drain type of I O p...

Page 46: ...t be connected to Vee Value Unit Test Conditions min max HLT 0 2V 2 0 V Vin Vcc RIT 0 1V 10 IA VOH 2 0V 200 IS 200 Is 1000 Is 1000 IS 800 IS Rf Oscillation External Clock Operation 0 2 ms Vcc 2 5 to 5 5V External Reset Vcc 2 5 to 5 5V RIT Vcc 2 Rf Oscillation External ms Clock Operation External Reset 2 Vcc 2 5 to 5 5V IS HLT Vcc Tinsl HLi vcc 20 ms HLT Vcc 20 ms 44 INTo and INT These pins provide...

Page 47: ... Figure 2 Configuration of Program Counter The address part is a 6 bit polynomial counter and counts up for each instruction cycle time_ The sequence in the decimal and hexa decimal system is shown in Table 1 This sequence is cir culating and has neither the starting nor ending point It doesn t generate an overflow carry Consequently the program on a same page is executed in order unless the value...

Page 48: ... referring to the pattern area The value of the operand p is 0 to 7 The content of the program counter is only modified ap parently and is not changed Then the address is counted up after the execution of the pattern instruction and the next instruction is executed The execution time of this instruction is 2 cycle time Even when interrupt is enable interrupt is disabled in the sec ond cycle of the...

Page 49: ...truction and performed only when the Status is 1 But the Status is unchanged re mains 0 even if it is skipped The operation is shown in Figure 7 ROMI R Figure 6 BR Operation BRL 05 O ROM I P I u I delaYbY 1 cycletime Figure 7 LPU Operation By BRL instruction the program branches to an address in any page This instruction is a macro instruction of LPU and BR in structions which is divided into two ...

Page 50: ...o instruction of LPU and CAL in structions which is divided into two instructions as follows CALL a b LPU a Subroutine jump to b address on a page CAL b CALL instruction is conditional because of characteristics of LPU and CAL instructions and is executed when the Status FIF is 1 Ifthe Status FIF is 0 it is skipped and the Status FIF changes to 1 RAM RAM is a memory used for storing data and savin...

Page 51: ...ss Space REGIS TER The HMCS44C has six 4 bit registers and two I bit registers available to the programmer The I bit registers are the Carry FI F and the Status F F They are explained in the following para graphs Status F F S The Status FIF latches the result of logical or arithmetic oper ations Not Zero Overflow and bit test operations The Status F F affects conditional instructions LPU DR and CA...

Page 52: ...R LBR Instruction One Instruction Cycle Rn Output Instruction Rn Pattern Instruction R2 R3 INPUT OUTPUT 4 bit Data Input Output Channel R The HMCS44C has four 4 bit Data I O Common Channels RO RI R2 R3 The 4 bit registers Data I O Register are attached to RI R2 and R3 channels Each channel is directly addressed by the operand p of input output instruction The data is transferred from the accumulat...

Page 53: ...er overflow output pulse or the input pulse of INTI pin its leading edge is counted The clock input to the counter is selected by the CF F F When the CF F F is 0 the clock input is the prescaler overflow output pulse Timer Mode When the CF F F is I the clock input is the input pulse of INTI pin Counter Mode When the counter reaches zero re turns from 15 to zero the overflow output pulse is generat...

Page 54: ...an interrupt request function 52 Each terminal consists of a circuit which generates leading pulse and the interrupt mask F F lFO IF An interrupt is enabled unmasked when the IFO F F or IFI F F is reset When the INTo or INTI pin changes from 0 to I from Low level to High lev I a leading pulse is generated to produce an interrupt request At the same time the IFO F F or IFI F F is set When the IFO F...

Page 55: ...el Refer to Figure 21 Moreover the HMCS44C has the automatic reset function ACL Built in Reset Circuit The Built in Reset Circuit restricts the rise condition of the power supply Refer to Figure 22 When the Built in Reset Circuit is used RESET should be connected to Vss Program Counter PC is set to 3F address on 31 page 31 3F URI IIRT liE and CF are reset to 0 IFO IFI and TF are set to 1 Reset Set...

Page 56: ...eld Pull up MOS ON Input No relation to Halt Since Pull up MOS is ON Pull up MOS current flows with output 0 Low level in the Halt State NMOS ON When an input signal changes transmission current flows into an input circuit Also current flows into Pull up MOS These cur Vcc ________ m T rents are added to the Stand by Supply Current or Halt Current Disable 1output High Impedance NMOS PMOS OFF Pull u...

Page 57: ...short as possible because the oscillation frequency is modified by capacitance of these terminals b Internal Clock Operation Using Ceramic Filter Circuit Built in CPG Ceramic Filter Oscillator This is not applied to HMCS44Cl Ceramicp C Filter C2 GND OSC Ceramic Filter CSB400P MURATA At lMO 10 C 2200pF 10 ceramic capacitor C2 4 70pF 10 ceramic capacitor F C _ 10SC mic C2 IOSCz Ceramic Filter FCR 40...

Page 58: ...SPX XSPY Y Spy XSPXY X SPX Y SPY LAM XY M A XY SPXY LBM XY M B XY SPXY RAM Register XMA XY M A XY SPXY Instruction XMB XY M B XY SPXY LMAIY X A M Y 1 Y X SPX LMADY X A M Y 1 Y X SPX LMIlYi Immediate Transfer i M Y 1 Y LAI i i A Instruction LBI i i B AI i A i A IB B 1 B DB B 1 B AMC M A C F F A SMC M A C F F A AM M A A DAA Decimal Adjustment Addition DAS Decimal Adjustment Subtraction Arithmetic In...

Page 59: ...r on Status 1 Instruction TBR p Table Branch RTN Return from Subroutine SEIE I E SEIFO IFO SElF IF SETF TF SECF CF REIE 0 I E REIFO 0 IFO REIF 0 IF RETF 0 TF Interrupt Instruction RECF 0 CF TIO Test INTo INTo TI Test INT INT TIFO Test IFO IFO TIF Test IF IF1 TTF Test TF TF lTI i i Timer Counter lTA A Timer Counter lAT Timer Counter A RTNI Return Interrupt SED D Y RED 0 D Y TD Test D Y D Y SEDD n D...

Page 60: ... 1 under judg ment instruction or instruction accompanying the judgem nt NZ ALU Not Z ro C ALU Overflow in Addition that is Carry NB ALU Overflow in Subtraction that is No Borrow Except above Cont nts of the status column affects the Status F F directly 3 The Carry F F C F F is not always affected by executing the instruction which affects the Status F F Instructions which affect the Carry F F ar ...

Page 61: ... Output 2 Oscillator Halt Not Used Oscillator Resistor Ceramic Resonator External Clock Please check one section on the above chart 3 I O State at Halt Mode I O State 0 Enable 0 Disable Mark y in 0 for the selected I O state 4 Supply Voltage Vee Supply Voltage Vee 0 5 O 5V 0 2 5V to 5 5V Mark y in 0 for the selected supply voltage Used Reset is applied when Halt release 59 Date Customer s Name ROM...

Page 62: ...ruction Single Word and Single Cycle BCD Arithmetic Instructions Pattern Generation Instruction Table Look Up Capability Powerful Interrupt Function 3 Interrupt Sources 2 External Interrupt Lines L Timer Event Counter Multiple Interrupt Capability Bit Manipulation Instructions for Both RAM and I O Option of I O Configuration Selectable on Each Pin Pull Up MOS or CMOS or Open Drain Built in Oscilla...

Page 63: ...imer Counter I I Ij Interrupt l y Spy addressing AAM 160 x 4 bit I ri I I H I A6 AS A4 L __ M I 1 J I Instruction Oecoder Jj J 7 r c 0 3 a c i r_ I I I a I I I l L ____ I I I I I c I I I I I I 0 I I I I n j c 0 g II II III III N 1ii II E B I O Common I A A J l l f f f o 0 0 f 0 0 0 VCC GND AESET OSC osc Power on Reset Circuit ACL is not built in HMCS45CL 61 ...

Page 64: ... Storage Temperature Tstg 55 to 125 Unit Remarks V V Except for terminal s specified by VT2 V SI e dC I rro o t pins mA NOTE 3 mA NOTE 3J C C NOTE 1 Permanent LSI damage may occur if maximum ratings are exceeded Normal operation should be under the conditions of ELECTRICAL CHARACTERISTICS 1 2 If these conditions are exceeded it could affect reliability of LSI NOTE 2 All voltages are with respect t...

Page 65: ... 1 10 Internal Clock Operation Rf Oscillation Clock Oscillation Frequency Rf 91kO 2 Clock Oscillation Frequency Ceramic Filter Circuit Instruction Cycle Time Tinst 4 fosc NOTE 1 All voltages are with respect to GND NOTE 2 This is applied to RESET HIT OSC INTo INTt and the With Pull up MOS or CMOS type of I O pins NOTE 3 This is applied to the Open Drain type of I O pins NOTE 4 This is applied to t...

Page 66: ...l voltages are with respect to GND HMCS45CL ELECTRICAL CHARACTERISTICS Vcc 2 5V to 5 5V eABSOLUTE MAXIMUM RATINGS Item Symbol Value Unit Supply Voltage Vee 0 3 to 7 0 V Terminal Voltage 1 VT1 0 3 to Vcc 0 3 V Terminal Voltage 2 VT2 0 3 to 10 0 V Maximum Total Output Current 1 1101 45 mA Maximum Total Output Current 2 1102 45 mA Operating Temperature Top 20 to 75 C Storage Temperature Tstg 55 to 12...

Page 67: ... Rise Time trcp 0 0 2 J lS External Clock Fall Time tfcp 0 0 2 J lS Instruction Cycle Time Tinst Tinst 4 fcp 16 S 20 30 S J lS Internal Clock Operation Rf Oscillation Rf 1S0k l 2 130 Clock Oscillation Frequency fosc Vcc 2 5 to 3 5V 1 Rf 1 SOk l 2 130 Vcc 2 5 to 5 5V Tinst 4 fosc 16 Instruction Cycle Time Tinst Vcc 2 5 to 3 5V Tinst 4 fOSC 11 4 Vcc 2 5 to 5 5V INOTE 11 All voltages are with respect...

Page 68: ...recommendations about these pins RtT This pin is used to place the HMCS45C in the Halt State Refer to HALT FUNCTION for details of tpe Halt Mode TRT This pin is not for user application and must be connected to Vee INTo and INTI These pins provide the capability for asynchronously applying external interrupts to the HMCS45C Refer to INTERRUPTS for additional information 66 Tins 20 ms 20 ms Roo to ...

Page 69: ...Ce Figure 2 Configuration of Program Counter The address part is a 6 bit polynomial counter and counts up for each instruction cycle time The sequence in the decimal and hexa decimal system is shown in Table 1 This sequence is cir culating and has neither the starting nor ending point It doesn t generate an overflow carry Consequently the program on a same page is executed in order unless the valu...

Page 70: ...erand p po p The upper bit 1 2 of the operand is for referring to the pattern area The value of the operand p is 0 to 7 The content of the program counter is only modified ap parently and is not changed Then the address is counted up after the execution of the pattern instruction and the next instruction is executed The execution time of this instruction is 2 cycle time Even when interrupt is enab...

Page 71: ...m counter with a delay of 1 instruction cycle time Therefore the cycle just after the issuing of this instruction is on the same page and the page jump is performed at the next cycle This instruction is a conditional instruction and performed only when the Status is 1 But the Status is unchanged re mains 0 even if it is skipped The operation is shown in Figure 7 BRL 05 _______ 0 ROM I P I u I dela...

Page 72: ...o an address in any page Subroutine jump to any address can be implemented by the subroutine jump to the page specified by LPU instruction This instruction is a macro instruction of LPU and CAL in structions which is divided into two instructions as follows CALL a b LPU a Subroutine jump to b address on a page CAL b CALL instruction is conditional because of characteristics of LPU and CAL instruct...

Page 73: ... Figure 10 RAM Address Space M O M l M 2 M 3 REGISTER The HMCS45C has six4 bit registers and two I bit registers available to the programmer The I bit registers are the Carry FI F and the Status F F They are explained in the following para graphs Status F F 5 The Status F F latches the result of logical or arithmetic oper ations Not Zero Overflow and bit test operations The Status F F affects cond...

Page 74: ... 110 Common Channels RO Rl R2 R3 The 4 bit registers Data 110 Register are attached to Rl R2 and R3 channels Each channel is directly addressed by the operand p of input output instruction The data is transferred from the accumulator and the B regis ter to the Data I O Registers RO to R3 via the bus lines Pattern instruction enables the patterns of ROM to be taken into the Data 110 Registers R2 an...

Page 75: ...struction Rn Sampling Clock Figure 13 4 bit Data I O Timing Set Signal by the reset function Set Instruction Reset Instruction___ I On SED REO SEDO REDO Instruction TO Instruction Latch Figure 14 1 bit Discrete I O Block Diagram One Instruction Cycle I t u set On LSI Din X On Test I Instruction It On Sampling Clock Figure 15 1 bit Discrete I O Timing 73 ...

Page 76: ...s zero re turns from 15 to zero the overflow output pulse is generated and the counter continues to count 14 15 0 1 2 The TF FIF is a flip flop which masks interrupts from the timer counter It can be set and reset by interrupt instruction If the overflow output pulse of the counter is generated when the TF F P is reset 0 an interrupt request occurs and the TF F Data Bus TF Set has priority over th...

Page 77: ...the INTo or INT pin changes from 0 to I from Low level to High level a leading pulse is generated to produce an interrupt request At the same time the IFO F F or IFI F F is set When the IFO F F or IFI F F is set the interrupt masking for the pin will result If a leading pulse is generated no interrupt request occurs An interrupt request generated by the leading pulse is latched into the input inte...

Page 78: ...applied when the operation is in the constant state Figure 21 RESET Timing O 2V Vcc I tOFF specifies the period when the power supply is OFF in the case that a short break of the power supply occurs and the power supply ON OFF is repeated Figure 22 Power Supply Timing for Built in Reset Circuit HALT FUNCTION When the HLT pin is set to 0 Low level the internal clock stops and all the internal statu...

Page 79: ...SI to select either of these two operational modes as shown in Figure 24 There is no need of specifying it by using the mask option a Internal Clock Operation Using Resistor Rf Wiring of OSC and OSC2 terminals should be as short as possible because the oscillation frequency is modified by capacitance of these terminals b Internal Clock Operation Using Ceramic Filter Circuit Built in CPG Ceramic Fi...

Page 80: ...SPX XSPY Y Spy XSPXY X SPX Y SPY LAM XY M A XY SPXY LBM XY M B XY SPXY RAM Register XMA XY M A XY SPXY Instruction XMB XY M B XY SPXY LMAIY X A M Y 1 Y X SPX LMADY X A M Y 1 Y X SPX Immediate Transfer LMIIYi i M Y 1 Y LAI i i A Instruction LBI i i B Ali A i A IB B 1 B DB B 1 B AMC M A C F F A SMC M A C F F A AM M A A DAA Decimal Adjustment Addition Arithmetic Instruction DAS Decimal Adjustment Sub...

Page 81: ...tatus 1 Instruction TBR p Table Branch RTN Return from Subroutine SEIE 1 liE SEIFO 1 IFO SEIF1 1 IF1 SETF 1 TF SECF 1 CF REIE 0 liE REIFO 0 IFO REIF1 0 IF1 RETF 0 TF Interrupt Instruction RECF 0 CF TIO Test INTo INTo TI1 Test INT INT TIFO Test IFO IFO TIF1 Test IF1 IF1 TTF Test TF TF LTI i i TimerICol lnter LTA A TimerICounter LAT TimerICounter A RTNI Return Interrupt SED 1 D Y RED 0 D Y TD Test D...

Page 82: ... 1 under judgement instruction or instruction accompanying the judgement NZ ALU Not Zero C ALU Overflow in Addition that is Carry NB ALU Overflow in Subtraction that is No Borrow Except above Contents of the status column affects the Status F F directly 3 The Carry F F C F F is not always affected by executing the instruction whicll affects the Status F F Instructions which affect the Carry F F ar...

Page 83: ... I O RS3 I O Rso 0 RSI 0 INTo I RS2 0 INTI I RS3 0 Specify the I O composition with a mark of 0 in the applicable composition column A No pull up MOS B With pull up MOS C CMOS Output 2 Oscillator Halt Oscillator Not Used Resistor Ceramic Resonator External Clock t Please check one section on the above chart 3 I O State at Halt Mode I O State 0 Enable 0 Disable l Mark in 0 for the selected I O stat...

Page 84: ...0ps All Instructions except One Instruction Single Word and Single Cycle BCD Arithmetic Instructions Pattern Generation Instruction Table Look Up Capability Powerful Interrupt Function 3 Interrupt Sources 2 External Interrupt Lines L Timer Counter Multiple Interrupt Capability Bit Manipulation Instructions for Both RAM and I O Option of I O Configuration Selectable on Each Pin With Puil up MOS or ...

Page 85: ...er rupt l R5 7 Instruction Decoder Jll 1 J A J A Y Spy ddressin 7 f c 0 RAM 256x 4 bit 0 c R4 and R6 can be used as general purpose registers Power on Reset Circuit ACL is not built in HMCS46CL 83 R4 11 VI OJ t l r rP12L v l j I a J I I a I J I J 0 ii I J U I I 0 I I I Jr J c c VI OJ Vi g ACL B r J l R R R R D 0 0 0 0 0 Vcc NO G HLT T ORESET 0 SC OSC I O Common ____ J ...

Page 86: ... 31 Maximum Total Output Current 2 I02 45 mA NOTE 31 Operating Temperature Top 20 to 75 c Storage Temperature TstII 55 to 125 c NOTE 11 Parmanent LSI damage may occur if Maximum Ratings are exceeded Normal operation should be under the conditions of ELECTRICAL CHARACTER ISTICS 1 2 If these conditions are exceeded it could be cause of malfunction of LSI and affects reliability of LSI NOTE 21 All vo...

Page 87: ...p 0 Instruction Cycle Time Tinst Tinst 4 fcp 4 7 Internal Clock Operation Rt Oscillation Clock Oscillation Frequency Rt 51kU 2 Clock Oscillation Frequency Ceramic Filter Circuit Instruction Cycle Time Tinst 4 fasc NOTE 11 All voltages are with respect to GND NOTE 21 This is applied to RESET HLT OSC INTo INT and the with Pull up MOSorCMOStype of I O pins NOTE 31 This is applied to the Open Drain ty...

Page 88: ... to 6 6V ABSOLUTE MAXIMUM RATINGS Item Symbol Value Unit Supply Voltage Vee 0 3 to 7 0 V Terminal Voltage 1 VT 0 3 to Vee 0 3 V Terminal Voltage 2 Vn 0 3 to 10 0 V Maximum Total Output Current 1 tlo 46 mA Maximum Total Output Current 2 tlo2 46 mA Operating Temperature Topr 20 to 76 c Storage Temperature T_ 66 to 126 c Value Unit min max 2 3 V 12 IlA 100 Ils 100 IJ S 1000 IlS 1000 IJ S 400 IJ S 0 1...

Page 89: ...t 4 fcp 16 S 20 30 S Internal Clock Operation Rf Oscillation At 20Okn 2 fose 130 250 Clock Oscillation Vee 2 5 to 3 5V Frequency fose Rt 200kil 2 130 350 Vee 2 5 to 5 5V Tinst Tlnst 4 fose 16 30 S Vee 2 5 to 3 5V Instruction Cycle Time Tinst 4 fosc Tinst Vee 2 5 to 5 5V 11 4 30 S NOTE 1I All voltages are with respect to GND NOTE 21 This is applied to RESET HLT ose INTo INT and the with Pull up MOS...

Page 90: ...ontrol input for the built in oscillator circuit A resistor ceramic filter circuit or an external oscillator can be connected to these pins to provide a system clock with various degrees of stability cost tradeoffs Lead length and stray capacitance on these two pins should be minimized Refer to OSCILLATOR for recommendations about these pins HLT This pin is used to place the HMCS46C in the Halt St...

Page 91: ... composed of32 pages 64 words page The ROM capacity is 4 096 words 1 word 10 bits in all All addresses can contain both the instructions and the pat terns constants The ROM address space is shown in Figure I 1 64 words i 1FOF _ 3 E 3 F Subroutine Space 11o 1 Page I 1 I I I I I I I I I 30 Page 31 Page 32 Page 33 Page I I I I I I I I 61 Page 62 Page E 63 Page Bank 0 0 Page 0 Page is the Subroutine S...

Page 92: ...lue is 0 the Bank 0 or 1 the Bank 1 for the bank part and 0 to 31 for the page part The address part is a 6 bit polynomial counter and counts up for each instruction cycle time The sequence in the decimal and hexa decimal system is shown in Table 1 This sequence is cir culating and has neither the starting nor ending point It doesn t generate an overflow carry Consequently the program on a same pa...

Page 93: ...he bank part are ORed with the upper 2 bits of B register the Carry F F and the operand p The value of the operand p P2 PI Po is 0 to 7 decimal The bank part of the ROM address to be referenced to is determined by the logical equation PCll P2 P2 the MSB of the operand p If the address where the pattern instruction exists is in the Bank 1 only the pattern of the Bank 1 can be referenced If the addr...

Page 94: ... 01 I0 0 o o 0 0 05 0 4 0 3 O O I Pattern of ROM Loaded into the accumulator and B register I R OT R r R R u r R 30 r R T R 3 r R I sinto the R2 and R3 Figure 5 Correspondence of Each Bit of Pattern Table 3 Example of Pattern Instructions Usage Before Execution Referred ROM ROM After Execution PC p C B A Address Bank 00 3F 1 0 A 0 Bank 010 20 0 3F 10 20 Bank 00 3F 7 1 4 0 Bank 1 29 00 0 3F 61 00 B...

Page 95: ... remain unchanged 0 LPU instruction is used in combination with BR instruction or CAL instruction as the macro instruction of BRL or CALL instruction BRL By BRL instruction the program branches to an address in any bank and page This instruction is a macro instruction of LPU and BR in structions which is divided into two instructions as follows BRL a b LPU a BR b Jump to Bank R70 a Page b Address ...

Page 96: ...d executed only when the Status F F is I If the Status F F is 0 it is skipped and the Status F F changes to 1 CALL By CALL instruction subroutine jump to an address in any bank and page is performed Table 4 Bank Part Truth Table of TBR Instruction Subroutine jump to any address can be implemented by the subroutine jump to the page specified by LPU instruction in the bank designated by the reversed...

Page 97: ... by a matrix of the file No and the digit No The file No is set in the X register and the digit No in the Y register for reading writing or testing Specific digits in RAM can be addressed not via the X register and Y register These digits are called Memory Register MR 0 to 15 l6 digits in all The memory register can be exchanged with the accumu lator by XAMR instruction 95 The RAM address space is...

Page 98: ...11 10 9 8 7 6 5 4 3 13 12 11 10 9 8 7 6 5 4 3 II 0 Ol IX CD It a a a a a a a a a a a E E E E E E E E E E E Figure 12 RAM Address Space 23 22 21 2 n 01 0 M O 0 M 1 0 2 M 2 10 3 M 3 n Bit Assignment No Operand Figure 13 RAM Bit and Operand n 96 2 1 2 1 II a a E E 0 0 0 a E V register Digit No ...

Page 99: ...ctions respectively The con tents of the R4 register are sent to the accumulator and the B register by LAR and LBR instructions respectively R5 Register R5 The contents of the accumulator and the B register are trans ferred by LRA and LRB instructions respectively The contents of the R5 register are sent to the accumulator and the B register respectively INPUT OUTPUT 4 bit Data Input Output Common...

Page 100: ...n To the accumulator and the B register Figure 14 4 bit Data I O Block Diagram one nstructlon C I yce I I I I r l r J r l r L Rn Output Instruction Rn Pattern Instruction second cycle R2 R3 Rn Input Instruction r L Rn Sampling Clock Figure 15 4 bit Data I O Timing Set Signal by the reset function Set Instruction On Reset Instruction t Latch Test IN Figure 16 1 bit Discrete I O Block Diagram 98 ...

Page 101: ...w output pulse of the counter is generated when the TF FIF is reset 0 an interrupt request occurs and the TF F F becomes 1 If the overflow output pulse is generated when the TF FIF is set I no interrupt request occurs The TTF instruction enables the TF F F to be tested The timer counter consists of the 4 bit counter and the 6 bit prescaler as shown in Figure 19 The 4 bit counter may be loaded unde...

Page 102: ...which sets the I E F F simultaneously with the RTN instruc tion The Interrupt Address Input Interrupt Address Bank 0 1 Page 3F Address 1 Page 3F Address Timer Counter Interrupt Address Bank 0 0 Page 3F Address 0 Page 3F Address The input interrupt has priority over the timer counter inter rupt The INTo and INTI pin have an interrupt request function Each terminal consists of a circuit which genera...

Page 103: ...ed into the timer interrupt request F F I RT The succeeding opera tions are the same as an interrupt from the input Only the ex ception is that since an interrupt from the input precedes a timer counter interrupt the input interrupt occurs if both the I RI F F and the I RT F F are I when the input interrupt and the timer counter interrupts are generated simultaneously During this processing the I ...

Page 104: ... Status F F to 0 or 1 before the first execution of the conditional instruc tions LPU CAL and BR instructions Reset State RESET Vee HALT FUNCTION When the HLT pin is set to 0 Low level the internal clock stops and all the internal statuses RAM the Registers the Carry F F the Status F F the Program Counter and all the internal statuses are held Because all internal logic operation stop power consum...

Page 105: ...ock frequency is internally divided by four to produce the internal system clocks The user may exchange the external parts for the same LSI to select either of these two operational modes as shown in Figure 25 There is no need of specifying it by using the mask option The typical value of clock oscillation frequency fose varies with a oscillation resistor Rf as shown in Figure 26 I Halt State vcc ...

Page 106: ...HMC C HMCS CL c External Clock Operation Figure 25 Clock Operation Modes 900 t Vee SV Ta 2SoC r 700 l 9 500 300 r typ so 70 90 110 130 1S0 Figure 26 Typical Value of Oscillation Frequency vs Rf 104 ...

Page 107: ...X XSPY Y Spy XSPXY X SPX Y Spy LAM XY M A XY SPXY LBM XY M B XY SPXY RAM Register XMA XY M A XY SPXY Instruction XMB XY M B XY SPXY LMAIY X A M Y 1 Y X LMADY X A M Y 1 Y X Immediate Transfer LMIIY i i t M Y 1 Y Instruction LAI i i A LBI i i B AI i A i A IB B 1 B DB B 1 B AMC M A C F F A SMC M A C F F A AM M A A DAA Decimal Adjustment Addition Arithmetic Instruction DAS Decimal Adjustment Subtracti...

Page 108: ...NOTE 1 XV after a mnemonic code has four meanings as follows Mnemonic only Mnemonic with X Mnemonic with V Mnemonic with XV Example lAM lAMX lAMY lAMXV Instruction execution only After instruction execution X SPX After instruction execution V SPY After instruction execution X SPX V SPY M A M A X SPX M A V SPY M A X SPX V Spy Status NZ NZ NZ NZ NB NB NB M n 1 1 1 INTo INT IFO IFl TF O V 2 Status co...

Page 109: ...k of 0 in the applicable composition column A No pull up MOS B With pull up MOS C CMOS Output 2 Oscillator Halt Not used Used Reset is applied when Halt release Used Reset is not applied when Halt release Oscillator Resistor Ceramic Resonator External Clock Please check one section on the above chart 3 I O State at Halt mode I O State o Enable o Disable Mark in 0 for the selected I O state 4 Suppl...

Page 110: ...D Arithmetic Instructions Pattern Generation Instruction Table Look Up Capability Powerful Interrupt Function 3 Interrupt Sources 2 External Interrupt Lines LTimer Counter Multiple Interrupt Capability Bit Manipulation Instructions for Both RAM and I O Option of I O Configuration Selectable on Each Pin With Pull up MOS o CMOS or Open Drain HMCS47C HMCS47CL FP 54 HMCS47C HMCS47CL DP 64S Built in Os...

Page 111: ...pt 256x4 bit 109 i 5 a a 1 s rr a 1 r I I R5 I I I I R4 I I I L __ I Instruction Decoder S r ljA l J l c A c c 2r I I I I I I I a I I I I I ii I I I r 0 a 1 r r i I I I I I I ii I I I I r I I I I I I 0 I jf____J C c c I I l l al al en CIl Et B r ____JI O Common J J R o Rll R o R f o f o f o f o Do 0 0 Oil 0 0 Vee GND OR ESET 01OSC OSC f o Power on Reset Circuit ACL is not built in HMCS47CL ...

Page 112: ...TE 3 Maximum Total Output Current 2 l I02 45 mA NOTE 3 Operating Temperature Topr 20 to 75 c Storage Temperature Tstg 55 to 125 c NOTE 1 Permanant LSI damage may occur if Maximum Ratings are exceeded Normal operation should be under the conditions of ELECTRICAL CHARACTERISTICS 1 2 If these conditions are exceeded it could be cause of malfunction of LSI and affects reliability of LSI NOTE 2 All vol...

Page 113: ...e Time Tinst Tinst 4 fcp 4 7 Internal Clock Operation Rt Oscillation Clock Oscillation Frequency Rt 51kn 2 Clock Oscillation Frequency Ceramic Filter Circuit Instruction Cycle Time Tinst 4 f JfK NOTE 1I All voltages are with respect to GND NOTE 21 This is applied to RESET HLT OSC INTo INT and the With Pull up MOS or CMOS type of I O pins NOTE 31 This is applied to the Open Drain type of I O pins N...

Page 114: ... to 5 5V ABSOLUTE MAXIMUM RATINGS Item Symbol Value Unit Supply Voltage Vee 0 3 to 7 0 V Terminal Voltage 1 Vn 0 3 to Vee 0 3 V Terminal Voltage 2 VT2 0 3 to 10 0 V Maximum Total Output Current 1 I lo1 45 mA Maximum Total Output Current 2 I lo2 45 mA Operating Temperature Topr 20 to 75 c Storage Temperature Tstg 55 to 125 c Value min Unit max 2 3 V 1 2 IlA 100 Ils 100 Ils 1000 IlS 1000 IlS 400 IlS...

Page 115: ... 30 S Internal Clock Operation Rf Oscillation fOle Rf 200kil 2 Clock Oscillation Vee 2 5 to 3 5V 130 250 Frequency fosc Rf 2ookil 2 130 350 Vee 2 5 to 5 5V Tinst Tlnst 4 fOlC 16 30 S Vee 2 5 to 3 5V Instruction Cycle Time Tinst 4 fosc Tinst Vee 2 5 to 5 5V 11 4 30 S NOTE 11 All voltages are with respect to GND NOTE 21 This is applied to RESET HLT OSC INTo INT and the With Pull up MOS or CMOS type ...

Page 116: ...e control input for the built in oscillator circuit A resistor ceramic filter circuit or an external oscillator can be connected to these pins to provide a system clock with various degrees of stability cost tradeoffs Lead length and stray capacitance on these two pins should be minimized Refer to OSCILLATOR for recommendations about these pins R T This pin is used to place the HMCS47C in the Halt...

Page 117: ... word which is a unit for writing into ROM The ROM address has been split into two banks Each bank is composed of 32 pages 64 words page The ROM capacity is 4 096 words 1 word 10 bits in all All addresses can contain both the instructions and the pat terns constants The ROM address space is shown in Figure 1 t 64 words l 1F OF _ 3 E 3 F r 0 Page 1 Page 0 l Subroutine Space 1 1 1 Page 1 1 30 Page 3...

Page 118: ...Bank 1 for the bank part and 0 to 31 for the page part The address part is a 6 bit polynomial counter and counts up for each instruction cycle time The sequence in the decimal and hexa decimal system is shown in Table 1 This sequence is cir culating and has neither the starting nor ending point It doesn t generate an overflow carry Consequently the program on a same page is executed in order unles...

Page 119: ... the page part and the bank part are ORed with the upper 2 bits of B register the Carry F F and the operand p The val 1e of the ooerand P P2 PI Po is 0 to 7 decimal The bank part of the ROM address to be referenced to is determined by the logical equation PCll p z P z the MSB of the operand p If the address where the pattern instruction exists is in the Bank 1 only the pattern of the Bank 1 can be...

Page 120: ...d B register Figure 5 Correspondence of Each Bit of Pattern Table 3 Example of Pattern Instructions Before Execution Referred ROM ROM After Execution PC p C B A Address Bank 00 3F 1 0 A 0 Bank 010 20 0 3F 10 20 Bank 00 3F 7 1 4 0 Bank 1 29 00 0 3F 61 00 Bank 1 30 00 4 0 1 0 9 Bank 1 30 09 62 00 62 09 Bank 1 30 00 1 0 1 F 9 Bank 1 31 39 62 00 63 39 means that the value does not change after executi...

Page 121: ...LPU instruction is used in combination with BR instruction or CAL instruction as the macro instruction of BRL or CALL instruction BRL By BRL instruction the program branches to an address in any bank and page This instruction is a macro instruction of LPU and BR instructions which is divided into two instructions as follows BR L a b LPU a BR b Jump to Bank R70 a Page b Address BRL instruction is a...

Page 122: ...f stack STl ST2 ST3 and ST4 which allows the programmer to use up to 4 levels of subroutine jumps including interrupts CAL is a conditional instruction and executed only when the Status F F is 1 If the Status F F is 0 it is skipped and the Status F F changes to 1 CALL By CALL instruction subroutine jump to an address in any bank and page is performed Table 4 Bank Part Truth Table of TBR Instructio...

Page 123: ...trix of the file No and the digit No The file No is set in the X register and the digit No in the Y register for reading writing or testing Specific digits in RAM can be addressed not via the X register and Y register These digits are called Memory Register MR 0 to 15 I6 digits in all The memory register can be exchanged with the accumu lator by XAMR instruction 121 The RAM address space is shown ...

Page 124: ... 9 8 7 6 5 4 3 13 12 11 10 9 8 7 6 5 4 3 M N 0 al co I It or M it it it it a a a a a a a 2 2 2 2 2 2 2 2 2 2 2 Figure 12 RAM Address Space 23 22 21 2 n 01 0 M O 0 I M 1 0 I 2 M 2 10 I 3 M 3 n Bit Assignment No Operand Figure 13 RAM Bit and Operand n 122 2 1 2 1 N a it 2 2 0 0 0 a 2 V register Digit No ...

Page 125: ...Discrete I O in combina tion with the Y register 123 INPUT OUTPUT 4 bit Data Input Output Common Channel R The HMCS47C has five 4 bit Data I O Common Channels RO RI R2 R3 R4 and R5 and one 4 bit Data Output Chan nel R6 The 4 bit registers Data I O Register are attached to these channels Each channel is directly addressed by the operand p of input output instruction The data is transferred from the...

Page 126: ...nction To the accumulator and the B register 2 2 2 2 Output Function r 1 I ___ _ _J All billare set to 0 by the _function Figure 14 4 bit Data I O Block Diagram o Itt C I ne n rue Ion VC e r 1 r l r I Rn Output Instruction Rn Plttern In ructlon econd evelei R2 R3 r 1 Rn Input In truction Rn Sampling Clock Figure 15 4 bit Data I O Timing Set Signel by the reset function Set Instruction On R_t Instr...

Page 127: ...w output pulse of the counter is generated when the TF F F is reset 0 an interrupt request occurs and the TF F F becomes 1 If the overflow output pulse is generated when the TF F F is set 1 no interrupt request occurs The TIF instruction enables the TF F F to be tested The timer counter consists of the 4 bit counter and the 6 bit prescaler as shown in Figure 19 The 4 bit counter may be loaded unde...

Page 128: ...terrupt instruction which sets the I E F F simultaneously with RTN instruction The Interrupt Address Input Interrupt Address Bank 0 1 Page 3F Address 1 Page 3F Address Timer Counter Interrupt Address Bank 0 0 Page 3F Address 0 Page 3F Address The input interrupt has priority over the timer counter inter rupt The INTo and INTI pin have an interrupt request function Each terminal consists of a circu...

Page 129: ...e timer interrupt request F F I RT The succeeding opera tions are same as an interrupt from the input Only the excep tion is that since an interrupt from the input precedes a timer counter interrupt the input interrupt occurs if both the I RI F F and the I RT FIF are 1 when the input interrupt and the timerlcounter interrupts are generated simultaneously During this processing the I RT F F remains...

Page 130: ...the Status F F to 0 or 1 before the first execution of the conditional instruc tions LPU CAL and BR instructions Reset State RESET Vee HALT FUNCTION When the HLT pin is set to 0 Low level the internal clock stops and all the internal statuses RAM the Registers the Carry FIF the Status FIF the Program Counter and all the internal statuses are held Becuase all internal logic operation stop power con...

Page 131: ...rom the status just before the Halt State The user may exchange the external parts for the same LSI to select either of these two operational modes as shown in Figure 25 There is no need of specifying it by using the mask option The halt timing is shown in Figure 24 The typical value of clock oscillation frequency fose varies with a oscillation reSistor Rf as shown in Figure 26 t HaltState vcc ___...

Page 132: ...47C HMC547CL c External Clock Operation Open OSC Figure 25 Clock Operation Mode 900 I Vee SV Ta 2SoC 700 X 600 300 t t t typ y so 70 90 110 130 1S0 Figure 26 Typical Value of Oscillation Frequency vs Rf 130 ...

Page 133: ...SPX XSPY Y Spy XSPXY X SPX Y Spy LAM XY M A XY SPXY LBM XY M B XY SPXY RAM Register XMA XY M A XY SPXY Instruction XMB XY M B XY SPXY LMAIY X A M Y 1 Y X LMADY X A M Y 1 Y X LMIIY i i M Y 1 Y Immediate Transfer LAI i i A Instruction LBI i i B AI i A i A IB B 1 B DB B 1 B AMC M A C F F A SMC M A C F F A AM M A A DAA Decimal Adjustment Addition Arithmetic Instruction DAS Decimal Adjustment Subtracti...

Page 134: ...tion NOTE XVI after a mnemonic code has four meanings as follows Mnemonic only Mnemonic with X Mnemonic with Y Mnemonic with XV Example LAM LAMX LAMV LAMXY Instruction execution only After instruction execution X SPX After instruction execution V SPY After instruction execution X SPX y SPY M A M A X SPX M A y SI V M A X SPX Y Spy Status NZ NZ NZ NZ NB NB NB MinI 1 INTo INT IFO IF TF OIVI 2 Status ...

Page 135: ...y the I O composition with a mark of 0 in the applicable composition column A No pull up MOS B With pull up MOS C CMOS Output 2 Oscillator Halt Not used Used Reset is applied when Halt release Used Reset is not applied when Halt release Oscillator Resistor Ceramic Resonator External Clock Please check one section on the above chart 3 I O State at Halt mode I O State 0 Enable 0 Disable Mark in 0 fo...

Page 136: ...134 ...

Page 137: ...4 BIT SINGLE CHIP MICROCOMPUTER HMCS40 SERIES LIQUID CRYSTAL DISPLAY DRIVING TYPE ...

Page 138: ...136 ...

Page 139: ...dio Static 1 2 1 3 1 4 32 Segments Externally expandable up to 96 Segments using external Drivers HD44100s 32 I O Lines and 2 External Interrupt Lines Timer Event Counter All Instructions except One Instruction Single Word and Single Cycle BCD Arithmetic Instructions Pattern Generation Instruction Table Look Up Capability Powerful Interrupt Function 3 Interrupt Sources 2 External Interrupt Lines L...

Page 140: ... 1 ROM 2 048 x 10 bit program memory 128 x 10 bit pattern memory 4x 11 bit j tp I UU w III III III w w w 00 a III III 138 A o A A o All A lo All Aoo Ao III III J J XI XI N iii Il 0 Vee oGND 0 HLT 0 TEST r 1 0 Common L ____ J ...

Page 141: ... mA Note 3 Operating Temperature Topr 20 to 75 c Storage Temperature TItg 55 to 125 c NOTE 1 Stresses above those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device Normal opera tion should be limited to those conditions specified under ELECTRICAL CHARACTERISTICS 1 and 2 The use beyond these conditions may ceuse LSI s malfunction and at the seme time affects device reli...

Page 142: ...3 mA 5 folC 400 kHz Yin Vee Vee 5V Supply Current 2 lee2 Rf Oscillation folC 400 kHz 0 6 mA 5 12 External Clock Operation fcp 400 kHz Standby I O Leakage Current I Yin 0 to Vee 1 0 IJ A 6 9 ILS HLT 1 0V IVin 0 to 10V 3 IJ A 6 10 Standby Supply Current 1 lecs1 Vin Vee HLT 0 2V 10 IJ A 11 Standby Supply Current 2 ICCS2 Vin Vee HLT 0 2V 40 IJ A 7 n 1 static Frame FreQuency of LCD Drive f F n 2 1 2 Du...

Page 143: ... to CMOS output pins CMOS I O common pins input pins with pull up MaS and I O common pins with pull up MOS among 0 and R terminals 3 Applied to open drain output pins and open drain I O common pins among 0 and R terminals 4 Pull up MaS current is excluded 5 Applied to the supply current when the LCD III is in the reset state and the crystal oscillation for timer doesn t operate Current that flows ...

Page 144: ...e following terminals 1 Input pin O common pins with pull up MOS and CMOS I O common pins among 0 and R terminals 2 RESET HL I OSCI INTo and INTI 10 Applied to open drain I O common pins among 0 and R terminals 11 Current that flows in the input output circuit and in the power supply circuit for LCD is excluded The standby supply current isthe supply current at Vee 5V t 10 in Halt state in the cas...

Page 145: ... Output Current 1 l lo1 45 mA Note 3 Maximum Total Output Current 2 l lo2 45 mA Note 3 Operating Temperature Topr 20 to 75 c Storage Temperature Tlt9 55 to 125 c NOTE 1 Stresses above those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device Normal opera tion should be limited to those conditions specified under ELECTRICAL CHARACTERISTICS and 2 The use beyond these condi...

Page 146: ...Vee HLT 0 1V Vee 2 7 to 3 3V Standby Supply Current 2 Iccs2 Yin Vee HI T 0 1V Vee 2 7 to 3 3V n 1 static Frame Frequency of LCD Drive fF n 2 1 2 Duty n 3 1 3 Duty n 4 1 4 Duty LCD Display Voltage VLeD Vee V3 External Clock Operation System Clock _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ w _ _ External Clock Frequency fcp External Clock Duty Duty External Clock Rise Time trcp External Clock Fall Time...

Page 147: ... MOS and I O common pins with pull up MOS among 0 and R terminals 3 Applied to open irain output pins and open irain I O common pins among 0 and R terminals 4 Pull up MOS currant is axcluded 5 Applied to the supply current when the LCD III is in the reset state and the crystal oscillation for timer doesn t operate ICurrent that flows in the input ouljut circuit and in the power supply circuit for ...

Page 148: ... the following terminall 1 Input pl O common pins with pull up MOS and CMOS I O common pinl among 0 and R terminall 2 RESET HLT OSCI INT and INTI 10 Applied to open rain I O common pins among 0 and R terminall 11 Currant that flows In the input output circuit and in the po_r supply circuit for LCD is axcluded The standby supply current II the supply currant at Vee 3Vt10 in Halt state in the case t...

Page 149: ...g m r high the LCD Ill starts operation from the status just before the halt state Refer to HALT FUNCTION for details ofhalt mode TEST This pin is not for user application and must be connected toVec INTo and INTI These pins provide the capability for asynchronously apply ing an external interrupt to the LCD III Refer to INTERRUPTS for additional information 1 tINT iJ VI V2 andV3 Power for liquid ...

Page 150: ...rent connection methods are shown in Figure 1 1 External Clock Oscillator 2 Resistor VIH h _I_I 1 2 VCC j l r____ _ VIL jtj i4 t trcp tfcp tt SC1 Rf OS 1 Length of the wirings for OSc and OS 1 terminals should be minimized because the oscillation frequency veries depending on the capacitance of these terminals 500 400 N r 300 II 200 100 0 300 200 N r j 100 o Rf 100 100 HD44190 I typo 200 300 400 5...

Page 151: ...ed in this area The area is only used to store patterns constants that are referred in programs by user The instruction used in the LCD III consists of 10 bits The pattern area is in pages 61 and 62 No program can be The program area instructions can be programmed consists of 2 048 words 64 x 32 of pages 0 through 31 In this area either of programs or patterns can be stored I 64 words j 1F OF 07 3...

Page 152: ...gram area and the pattern area Pattern reference is performed by the instruction of pattern P in the program ROM Addressing for the pattern reference is performed by modifying PC with A B C F F and the operand p The modifying scheme is shown in Figure 4 The address part is re placed by the contents of A Accumulator and the lower bits of B The page part is logically ORed with the PC the upper 2 bit...

Page 153: ...use of X and Y These digits are called as memory register MR and the number is 16 MRO to MRlS Memory register can be exchanged for A register By XAMR instruction RAM address space is shown in Figure 6 X i 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 digit No 00 00 10 10 or Ol it it N E E t file No M N it it it E E E i i 0 it Ol a E 00 co 10 or a a a a a E E E E E M N a a a E E E 0 a E The area market as ...

Page 154: ... has exchangeability for Spy register Y register can calculate itself simultaneously with transferring the data by bus lines which is usable for the calculation of two or more digits 4 bits digit Y register addresses the RAM digit and I bit discrete input output common terminals Spy Register Spy Spy register has exchangeability for Y register Spy register is used to stack Y register and expand the...

Page 155: ... register and the set reset instruction is executed for the addressed latch 0 and 1 level can be tested with the addressed terminal and I bit register against the I O common pins and I bit register The test is performed with the wired logic of the output latch and the pin SED RED SEDD REDO Inltruc tlon TO Instruction o I st t C Ie j na n rue Ion ye On SetlRaset Instruction Dn LSI pin X input There...

Page 156: ... to data I O register but the content of data I O register is not output from Rl If LAR or LBR instruction is executed display data is inputted to accumulator A register or B register Data is transferred from the accumulator A register and B One Instruction Cvcle I i i i LRA LRS r I A Output In truc lon l n instruction nHN iO LAA LBR Inltructlon An X Pattern Ganera tion Instruction A2 A3 register ...

Page 157: ...as is operated by On to read the result from Rn an extarna circuit Applied Pins INTo INT Roo to Rn No Pull up MOS VCC I O E tf tos I NMOS I I With Pull up MOS PMOS Figure 12 Configuration of Input Pins Applied Pins R30 to Rn No Pull up MOS Open Drain I O Enable CMOS Output VCC r IroEi b 4 NMO Figure 13 Configuration of Output Pins Applied Pins 0 0 to 0 13 O 4 XO D s XI R o to Ru R20 to Rn No Pull ...

Page 158: ...etween 0 hitifflil hilt itiii terminals of 0 14 and 015 Note 1 In this case the overflow output pulses from the pre scaler are 16Hz These pulses are counted by the 4 bit counter to generate an interrupt from 16Hz to 1Hz Note 2 In this case the part marked with in Figure 15 Timer Counter does not stop even in halt state When using internal halt mode among the halt function internal halt state is ge...

Page 159: ...asically the subroutine jump and the jumping location in memory is flXed as Interrupt of the timer counter 0 page 3F address OO 3F Interrupt of the inputs 1 page 3F address 01 3F In addition The saving operation of PC STl ST2 ST3 ST4 I E reset Interrupt of the Inputs Two pins INTo and INT1 have the interrupt request func tions They have the leading pulse generation circuit and the 157 interrupt ma...

Page 160: ...Instruction Instruction in Addreu in Addreu p in AddrelS q 0 3F I 1 3F P q Instruction Instruction Instruction in Address in Addreu p in AddrelSq 1 3F r Figure 18 Interrupt Timing Chart LIQUID CRYSTAL DISPLAY Liquid Crystal Display Circuit The LCD III can directly drive the liquid crystal display panel of static 1 2 duty factor 1 3 duty factor and 1 4 duty factor 158 The LCD III has 4 common signa...

Page 161: ...egment is read twice at the same time And in the HD44795 scan of common signal is ex ecuted every 128 instruction cycle Therefore 128 segment data is read The serial data read is converted to parallel data by the 159 shift register and latch converted to LCD drive signal by the liqUid crystal driver and the outputted from a segment terminal 32 segment SEG1 to SEGn out of 128 segment serial data is...

Page 162: ...ta Shift Clock Latch Clock fi ______ n Alterneting J Signel M HD44795 1 128 Instruction Cycle I One Instruction Cycle Serial Data Shift Clock Latch Clock Alternating Signal M 1 II u j 1 11 1 III III L __ ___ I Figure 20 Liquid Crystal Display Circuit Time Chart To be continued 160 ...

Page 163: ...M COM 1 2 Duty COM COM2 COM COM 1 3 Duty COM COM2 COM COM 1 4 Duty COM Figure 20 Liquid Crystal Display Circuit Time Chart 161 All outputs are available because of the same waveform outputs J Common Symbol Symbol J Common 1 Common Symbol Common Symbol Both groups are available because of the same waveform outputs ...

Page 164: ...60 1 Segment signals become non selection status blanking regardless of RAM designation for liquid crystal display Rso Rs RAM data for liquid crystal display NOTE LiQuid crystal display mode at resetting Since all bits of registers R4 R5 and R6 are set to 1 by the reset function display mode after resetting becomes as shown below Liquid crystal display duty factor 1 4 duty R40 1 R41 1 d crystal se...

Page 165: ... COM COM2 COM COM2 COM COM2 COM COM2 COM COM2 COM COM2 COM COM2 COM COM2 COM COM2 COM COM2 COM COM2 COM COM2 COM COM2 COM COM2 COM COM2 COM COM2 COM COM2 COM COM2 COM COM2 COM COM2 COM COM2 NOTE The SEG to SEGI2I are extended segments Figure 22 Relation between RAM for LCD Segment Data 1 2 Duty 1 2 Bias 163 ...

Page 166: ...SEG3s 2 SEG 9 SEG99 SEG 9 3 SEG3lI SEG38 SEG3e 3 SEG oo SEG oo SEG oo 4 SEG37 SEG37 SEG37 4 SEG o SEG o SEG o 5 SEG3lI SEG3e SEG3s 5 SEG 02 SEG 02 SEG 02 6 SEG3 SEG39 SEG39 6 SEG 03 SEG 03 SEG 03 4 6 0 SEG SEG SEG 8 SEG t SEG SEG 0 2 4 6 7 SEG 04 SEG 04 SEG 04 8 SEG 05 SEG 05 SEG 05 9 SEG 2 SEG 2 SEG 2 9 SEG 08 SEG 08 SEG 08 10 SEG 3 SEG 3 SEG 3 10 SEG 07 SEG 07 SEG 07 11 SEG SEG SEG 11 SEG 08 SEG...

Page 167: ...SEG SEG 2 SEG SEG SEG SEG 3 SEG oo SEG oo SEG OCI SEG oo 4 SEG o SEG o SEG o SEG o 5 SEG 02 SEG 02 SEG 02 SEG 02 a SEG 03 SEG OI SEG OI SEG OI 0 2 4 a 7 SEG 04 SEG 04 SEG 04 SEG 04 8 SEG OI SEG OI SEG OI SEG OI 9 SEG OI SEG OI SEG OI SEG OI 10 SEG 07 SEG 07 SEG 07 SEG 07 11 SEG OI SEG OI SEG OI SEG OI 12 SEG OI SEG OI SEG OI SEG OI 13 SEG o SEG o SEG o SEG o 14 SEG SEG SEG SEG 15 SEGm SEGm SEGm SE...

Page 168: ... VCC VI V2 SEpl V SEG Static t GND i Vee VI V2 V SE GI SEG 1 2 duty 1 2 bias GND C9MI VCC COM VI V2 S GI V SEG 113 duty 1 3 bias r 4GND 1 Vee VI V2 V 11 4 duty 1 3 bias JM 0 lEO 32 32 Figure 25 LCD Wiring Samples 166 10 Digits with symbols J J ...

Page 169: ...ower Supply Condition Using the Built in Reset Circuit m T Vee Vee tfRST trRST tfRST NOTE 1 tRST Includ the time required from the pow r ON until the operltlon getllnto the conltlnt nltt 2 tRST2 II pplled wh n the operltlon II In the conlt nt It tt Figure 27 Reset Input Condition Using an External Reset Circuit HALT FUNCTION The LCD III is provided with half function The halt function reduces powe...

Page 170: ...ecution restarts from the instruction next to the RED instruc tion Note that external halt caused by the HLT terminal cannot be released by prescaler overflow signals I Becomes halt state after executing RED instruction and the halt is maintained ___ L_V_I_ 15 until a prescaler overflow signal is issued L R ED I TO LVI 0 BR 4 The LCD III returns from halt state by a prescaler overflow signal and o...

Page 171: ...nal performs the LCD III return from internal halt Return from external halt is not possible by the prescaler overflow signaL state Since the input circuit is turned off input change does not cause current other than the standby power supply current or halt current A Without pull up MOS B With pull upMOS With or without Externally Attached Timer Crystal Without timer crystal C CMOS output Note Ext...

Page 172: ...MIIY i LAI i LB I AI IB DB AMC SMC AM DAA DAS NEGA COMB SEC REC TC ROTL ROTR OR i i B A A B Y A SPX A SPY A A MR m A X A Y i X i Y Y 1 Y Y 1 Y Y A Y Y A Y X SPX V Spy Function X SPX Y Spy M A X Y S P X Y M B X Y S P X Y M A XY SPXY M B X Y S P X Y A M Y 1 Y X S P X A M Y 1 Y X SPX i M Y 1 Y i A i B A i A B 1 B B 1 B M A C F F A M A C F F A M A A Decimal Adjustment Addition Decimal Adjustment Subtr...

Page 173: ... p Table Branch RTN Return from Subroutine S E I E 1 I E S ElF a 1 I Fa SEIF1 1 IF 1 SETF 1 T F SECF 1 C F REI E a I E REI Fa a I Fa REI F 1 a IF 1 RETF a T F Interrupt RECF a C F Tla Test I N To INTo T 11 Test I NT INT T I Fa Test IFa I Fo TIF1 Test IF 1 I F TTF Test TF TF LTI i Timer Counter LTA A Timer Counter LAT Timer Counter A RTN I Return Interrupt SED 1 0 Y RED a 0 Y TO Test D Y O Y SEDO n...

Page 174: ...2 Status column shows the factor which affects status by the instruction of status change NZ ALU Not Zeto C ALU Overflow in Addition Carry NB ALU Overflow in Subtraction No Borrow except above Content of status column affects status directly 3 Carry flip flop is not always affected by executing the instruction which affects the Status Instructions which affect Cerry flip flop are eight as follows ...

Page 175: ...cillator External Halt Not used Used Reset is applied when Halt release Used Reset is not applied when Halt release Oscillator Resistor Ceramic Resonator External Clock Please check one section on the above chart 3 Oscillator Internal Halt No RAM contents are No RAM contents are Yes It is provided only Halt not kept by reset kept by reset when the crystal for timer exists Oscillator Resistor Ceram...

Page 176: ...ircuit for LCD 4 Commons Duty Ratio Static 1 2 1 3 1 4 32 Segments Externally expandable up to 96 Segments using external Drivers HD44100Hs 32 I O Lines and 2 External Interrupt Lines Timer Event Counter All Instructions except One Instruction Single Word and Single Cycle BCD Arithmetic Instructions Pattern Generation Instruction Table Look Up Capability Powerful Interrupt Function 3 Interrupt Sou...

Page 177: ... LCD IV BLOCK DIAGRAM ROM 4 096 x 10 bit 14 x 12 bit 1 UU 00 a 8 w w 0000 u u u u 175 en en l l III III N if en r R R R R u R RI Roo R D 0 Vcc GND HLT TEST I O Common L ____ J ...

Page 178: ...o 125 c NOTE Stresses above those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device Normal opera tion should be limited to those conditions specified under ELECTRICAL CHARACTERISTICS and 2 The use beyond these conditions may cause LSI s malfunction and at the seme time affects device reliability 2 All wltages are with respect to GND 3 Maximum Total Output Current is th...

Page 179: ...rrent 2 Ice2 fose 800 kHz 2 mA 5 External Clock Operation fcp 800 kHz Standby I O Leakage Current ILS HLT 1 0V Vin 0 to Vee 1 0 JJ A 6 12 Standby Supply Current 1 leCs1 Vin Vee HLT 0 2V 10 JJ A 15 Standby Supply Current 2 lees2 Vin Vee HLT 0 2V 120 JJ A 7 LCD Display Voltage VLeD Vee V3 2 5 Vce V 11 n 1 static Frame Frequency of LCD Drive n 2 1 2 Duty 1 Hz 13 fF n 3 1 3 Duty 256 x n x Tinst n 4 1 ...

Page 180: ...and R terminals 4 Pull up MOS current is excluded 5 Applied to the supply current when the LCD IV is in the reset state and the crystal oscillation for timer doesn t operate Current that flows in the input output circuit and in the power supply circuit for LCD is exclud d Test Condition RESET HLT TEST Vee Reset State INTo INT Roo to R33 D to DI3 VCC D XO D s XI cD XO D s XI Vee Crystal oscillation...

Page 181: ...liquid crystal display if frame frequency is under 32 Hz Therefore operation frequency should be determined to prevent that frame frequency becomes under 32 Hz The following shows the relation between liquid crystal display frame frequency and operation frequency 1 000 500 f u i Frame Frequency Lower Limit i5 00 50 10 10 V V I 50 100 Vv Static V V 12 duty 3 duty 4 duty V 500 Operation Frequency fc...

Page 182: ...supply circuit for LCD is excluded ELECTRICAL CHARACTERISTICS Vee 2 5 to 5 5V ABSOLUTE MAXIMUM RATINGS Item Symbol Value Unit Note Supply Voltage Vcc 0 3 to 7 0 V Terminal Voltage Vn 0 3 to Vcc 0 3 V Maximum Total Output Current 1 lo1 25 mA Note 3 Maximum Total Output Current 2 lo2 25 mA Note 3 Operating Temperature Topr 20 to 75 C Storage Temperature Tstg 55 to 125 C NOTE 1 Str_ above those lilte...

Page 183: ...xternal Clock Operation fcp 200 kHz Standby I O Leakage Current ILS HLT 0 5V Vin OtoVee 1 IJ A 6 11 Standby Supply Current 1 leCSl Vin Vee HLT O lV 6 IJ A 14 Vee 2 5 to 3 3V Standby Supply Current 2 lecs2 Vin Vee HLT O lV 50 IJ A 7 Vee 2 5 to 3 3V LCD Display Voltage VLeD Vee V3 2 5 Vee V 10 n 1 static Frame Frequency of LCD fF n 2 112 Duty 1 Hz Drive n 3 1 3 Duty 256 x n c Tinst 12 n 4 1 4 Duty E...

Page 184: ...xcluded 5 Applied to the supply current when the LCD IV is in the reset state and the crystal oscillation for timer doesn t operate Current that flows in input o t circuit and in the power supply circuit for LCD is excluded Test Condition RESET HLT Vee Reset State D XO DIS XI L D 4 XO D s XI Vee Crystal oscillation for timer is not selected V V 2 V3 Vee D XO Open 015 XI Vee Crystal oscillation for...

Page 185: ...TI pins 12 Lower limit of operation frequency is determined by liquid crystal display duty Flutter occurs on liquid crystal display if frame frequency is under 32 Hz Therefore operation frequency should be determined to prevent that frame frequency becomes under 32 Hz The following shows the relation between liquid crystal display frame frequency and operation frequency 1000 500 N 100 E f u 50 Fra...

Page 186: ...IPTION The input and output signals for the LCD IV shown in PIN ARRANGEMENT are described in the following paragraphs VccandGND Power is supplied to the LCD IV using these two pins Vee is power and GND is the ground connection RESET The LCD IV can be reset by pulling RESET High Refer to RESET FUNCTION for additional information OSC1 and OS These pins provide control input for the on chip clock osc...

Page 187: ...alt Crystal circuit connecting terminals no internal halt Refer to INPUT OUTPUT for additional infonnation COMI to COM These pins are common tenninals for liquid crystal display Refer to LIQUID CRYSTAL DISPLAY for additional in fonnation SEGI to SEG32 These pins are segment tenninals for liquid crystal display OSCILLATOR The user can specify a resistor or a ceramic filter circuit or an external os...

Page 188: ... 31 Page Bank 00 Page 0 Pagel Is the Subroutine Space Timer Counter Interrupt Address Bank 0 0 Page 3F Address 0 Page 3F Addressl Input Interrupt Ack lress Bank 0 1 Page 3F Address 1 Page 3F Addressl Reset Address Benk 1 31 Page 3F Address 163 Page 3F Addressl Note The parenthesized contents ere expreilions of the Plge combining thl bank part with the page part Figure 1 ROM Address Space 186 ...

Page 189: ...The settable value is 0 the Bank 0 or I the Bank I for the bank part and 0 to 31 for the page part The address part is a 6 bit polynomial counter and counts up for each instruction cycle time The sequence in the decimal and hexa decimal system is shown in Table 1 This sequence is cir culating and has neither the starting nor ending point It doesn t generate an overflow carry Consequently the progr...

Page 190: ... bits 4 bits and 4 bits from the most significant bit 0 10 in order shown in the hexa decimal system The examples are shown in Figure 3 r Page Part Address Part ______ I I I IBank 20 26 Bank 20 Page 26 Address J Decimal I Hexa l 152 26 52 Page 26 Address Binarv He a decimal IDecimal ___ I decimal Example 2 r 1Page Part Bank Part r Page Part r Addre Part 10 1 0 0 10 0 0 Declmal 1L J _ _ _ J Blnlrv ...

Page 191: ...am counter is apparently modified and does not change actually After execution of the pattern instruc tion the program counter counts up and the next instruction is executed The pattern instruction is executed in 2 cycle time Generation The pattern of referred ROM address is generated as the fol lowing two ways i The pattern is loaded into the accumulator and B register ii The pattern is loaded in...

Page 192: ... 1 instruction cycle time At the same time the signal R O the reversed phase signal of the Data 1 0 Register R O is transferred to the bank part of the program counter with a delay of 1 instruction cycle time The operation is shown in Figure 7_ Consequently the bank and page will remain unchanged in the cycle immediately following this instruction In the next cycle a jump of the bank and page is a...

Page 193: ...re 8 BRL Example 0 5 0 Delay by 1 Instruction Cycle Time I I I Bank Part Figure 7 LPU Operation 191 Table 4 Bank Part Truth Table of TBR Instruction PC P2 Bank Part of PC after TBR 1 1 Bank 1 1 Bank 1 0 1 Bank 1 1 1 Bank 1 o Bank 0 0 o Bank 0 SUBROUTINE JUMP There are two types of subroutine jumps They are explained in the following paragraphs CAL By CAL instruction subroutine jump to the Subrouti...

Page 194: ...structions which is divided into two instructions as follows CALL a b LPU a CAL b Subroutine Jump to Bank R70 a Page b Address CALL instruction is conditional because of characteristics of LPU and CAL instructions and is executed when the Status F F is 1 If the Status FIF is 0 the instruction is skipped and the Status FIF changes to 1 The examples of CALL instruc tion are shown in Figure 11 Page P...

Page 195: ...ddressing of RAM is performed by a matrix of the file No and the digit No Normally the file No is set to X and the digit No is set to Y then the matrix of X and Y addresses RAM and performs the Read Write operation Special digits in RAM can be addressed without the use of X and Y These digits are calJed as memory ragister MR and the number is 16 MRO MR15 Memory register can be exchanged for A regi...

Page 196: ... the data tempo rarily and also used as a counter X Regilter X The result of ALU operation 4 bits is put into this register X register has exchangeability for SPX register X register addresses the RAM file SPX Register SPX SPX register has exchangeability for X register SPX register is used to stack X register and expand the addres sing system of RAM in combination with X register V Register V The...

Page 197: ... set by overflow output pulse from the prescaler to return to operat ing state For details of internal halt mode refer to HALT FUNCTION Table 5 Mask Option of DI4 XO and Dis XI Terminals Mask Option a b d Function of Function of DI4 XO c DI4 XO and Dis XI and Dis XI latch 1 Unselectable crystal oscillation for short open discrete I O Output Latch timer no internal halt common terminal open short 2...

Page 198: ...put I I I 2 0 R To I 22 lOR A B I R O Channel Register 2 0 Ro t o Roo I ___ I Output ROM paltern orda r 4 bit register data I O register each is attached to an I O common channel and output channel No register is attached to input channel Addressing to all channels is performed by programs addressed by operands in instructions Figure 16 shows the block diagram of each channel So 1 segment 01 101 L...

Page 199: ... Rl and R2 channels by input instruc tions However in the case of I O common channels R2 and R3 since data I O register outputs are connected to terminals inputs are done to wired logic of register output and terminal input information For this reason to input terminal input signal registers must be set to a state that would not affect the terminal input second cycle Rn Input Instruction I Rn Samp...

Page 200: ... Vee 1 0 __ r Enable MOS I I MOS I L____J With Pull up MOS PMOSI Input Circuit ellll 1 0 Enable NOTE In case that CMOS is chosen external input signal cannot be applied Figure 20 Configuration of Input Output Pins Discrete 1 0 output latch 1 0 n t___I _J Discrete 1 0 output latch ________ 0 1 CL 1 Internal halt release signal 015 output latch set signal L ____ Figure 21 Timer Counter Block Diagram...

Page 201: ...ernal halt mode 0 latch 0 15 by an instruction D15 0 internal halt state 015 1 operating state and aU the operation stop In this case over flow output pulses from the prescaler work as the signals releasing the internal halt state and set the DIS output latch Therefore if an overflow output pulse from the prescaler is generated internal halt state is released and the LSI starts to operate By utili...

Page 202: ...terrupt Mask Signal INT 4 I RT Figure 23 Interrupt Circuit Block Diagram The status is unchanged The interrupt is different from general CAL in regard to this matter Stacking of registers is performed by the program Returning from the interrupt routine is performed in the same way as that from normal subroutine_ But it is convenient to use RTNI Re turn Interrupt which sets the I E simultaneously w...

Page 203: ...terminals of momentary pulse input The interrupt pulse width at both High and Low levels should be more than two cycle Interrupt of the Timer Counter The interrupt request of the timer counter is latched into the interrupt request F F of the timer I RT Then I RT operates in the same way as I RI but the interrupt of the input has priority over that of the timer Therefore the input interrupt is proc...

Page 204: ...ress signal from the display counter and the control circuit Every time common signal is scanned the RAM reads 128 segment data SEGt to SEGt28 which is correspond to common signal selected at the next time Scan of common signal is executed every 256 instruction cycle Therefore the data which is cor respond to 128 segment is read twice at the same time The serial data read is converted to parallel ...

Page 205: ...256 Instruction cycle l I One Instruction Cycle tc I fA 1 1 U U 1 I 1 External latch n n Clock Cl J 1i ___ ______ jI _ _ _ _ 4J______ J Alternating Signal M D Cl Cl M One Instruction Cycle Figure 26 Display Data Timing Chart 203 ...

Page 206: ...2 Duty COM COM1 COM COM 1 3 Duty COM COM1 COM COM 1 4 Duty COM COM1 COM COM All outputs are available because of the same waveform outputs J eommon Symbol Symbol J eommon 1 eommon Symbol Common Symbol Both groups are available because of the same waveform outputs Figure 27 Liquid Crystal Display Circuit Timing Chart 204 ...

Page 207: ... Rso RS1 Function varies with liquid crystal display duty factor R63 R62 R61 R60 Function Selection of 0 0 Do not set in this state halt function and oscillation 0 1 With crystal for timer with internal halt XI XO circuit for 1 0 Without crystal for timer 0 14 and DIS are general I O timer 1 1 With crystal for timer without internal halt XI XO I O state 0 Enable at halt 1 Disable NOTE Liquid cryst...

Page 208: ...nd 1 4 duty can be selected by programs and correspondence between RAM bits and segment data changes according to these duty factors _ shows segment signal output from the LCD IV extended segments Figure 28 Relation between RAM for LCD Segment Data Static 206 Figure 29 Relation between RAM for LCD Segment Data 1 2 Duty 1 2 Bias ...

Page 209: ...15 SEG96 SEG96 SEG96 0 SEG97 SEG97 SEG97 1 SEG98 SEG98 SEG98 2 SEG99 SEG99 SEG99 3 SEG100 SEG100 SEG100 4 SEGlO SEGlO SEG o 5 SEG102 SEG 02 SEG102 6 SEG103 SEG103 SEG103 0 2 4 6 7 SEG104 SEG104 SEG 04 8 SEG105 SEG105 SEG105 9 SEG106 SEG106 SEG106 10 SEG107 SEG 07 SEG107 11 SEG 08 SEGlO SEGlO 12 SEG109 SEG109 SEG 09 13 SEGll0 SEGll0 SEG o 14 SEGll SEGll SEG 15 SEG 2 SEG112 SEG 2 0 SEG 3 SEG113 SEG ...

Page 210: ...6 SEG98 0 SEG97 SEG97 SEG97 SEG97 1 SEG98 SEG98 SEG98 SEG98 2 SEG99 SEG99 SEG99 SEG99 3 SEG 00 SEG 00 SEG100 SEG 00 4 SEGlOl SEG 0 SEG 01 SEG 0 5 SEG102 SEG102 SEG 02 SEG 02 6 SEG103 SEG 03 SEG103 SEG 03 0 2 4 6 7 SEG 04 SEG104 SEG 04 SEG 04 8 SEG105 SEG105 SEG 05 SEG105 9 SEG106 SEG106 SEG 06 SEG 061 10 SEG 07 SEG107 SEG107 SEG107 11 SEG 08 SEG 08 SEG108 SEG 08 12 SEG109 SEG109 SEG109 SEG109 13 S...

Page 211: ...G Vs SEG a Static iGND f Vee V V SE1G L i Vs SEG a 1 2 duty 1 2 bias GND COM I eOMs Vee c V V S G V3 SEG a 1 3 duty 1 3 bias tGND Vee V V V3 S G SEG a 3 1 4 duty 1 3 bias 1M 0 170 32 1 o 32 Figure 32 LCD Wiring Samples 209 10 Digits I with symbols t ...

Page 212: ...t HALT state is kept 16 instruction after receiving halt releas ing signal Internal External The user can select one of the following I O status at the time of halt based on the MASK OPTION LIST when ordering ROM i AU I O status is kept as the state immediately before the halt ii All I O status is held in the high impedance state both PMOS and NMOS are off and pull up MOS is off There are the foll...

Page 213: ...halt 3 Internal and external halt DI4 XO LCD IV D15 XI Rd R With or without timer crystal Externally attached crystal 32 768 kHz Without crystal Internal clock of LSI Externally attached crystal 32 768 kHz c NOTE The crystal oscillator resistor R Rd and load capacitor CI and Ca should be placed as close as possible to the LCD IV Induction of ex ternal noise to D14 XO and D15 XI may disturb normal ...

Page 214: ...h impedance state Since the input circuit is turned off input change does not cause current other than the standby power supply current or halt current With or without externally attached Timer Crystal Without timer crystal The 0 14 and 015 can be used as general I O terminals Select one of A B or C in the 0 14 015 column ofthe I O format speCifications With timer crystal The 0 14 and 015 cannot b...

Page 215: ...0 I O 0 1 I O Ol I O 0 3 I O 04 I O 05 I O 0 6 I O 0 I O 08 I O 09 I O 0 10 I O 0 11 I O 0 12 I O 0 13 I O 0 14 I O 0 15 I O Roo I ROI I ROl I R03 I RIo I O R11 I O Rll I O R13 I O RlO I O Rll I O Rl2 I O R23 I O R30 0 R31 0 Rll 0 R33 0 INTo I INTI I NOTEI Mark 8 selected composition with 8 circle 01 A No Pull up MOS B With Pull up MOS C CMOS Output 213 ...

Page 216: ...ith or without internal o With o Without Internal halt is specified only when crystal for timer is halt specified Power supply voltage o 5 O 5V 0 2 5 to 5 5V Oscillation circuit 0 Rf Oscillation Ceramic filter is specified only when power supply is system clock o Ceramic filter Vee 5 O 5V 0 External clock 0 Not use Halt function 0 Use Return by Reset 0 Use Return by no Reset NOTE Mark I elected I ...

Page 217: ...Y X LM IIY i LA I i L B I i AI IB DB AMC SMC AM DAA DAS NEGA COMB SEC REC TC ROTL ROTR OR Function B A A B Y A SPX A SPY A A M R m A X A Y i X i Y Y 1 Y Y 1 Y Y A Y V A Y X SPX V Spy X SPX Y Spy M A X Y S P X YT M B X Y S P X Y M A XY SPX Y M B X Y S P X Y A M Y 1 Y X S P X A M Y 1 Y X SPX i M Y 1 Y i A i B A i A B 1 B B 1 B M A C F F M A C F F M A A A A Decimal Adjustment Addition Decimal Adjustm...

Page 218: ...T F Interrupt RECF 0 C F TIO Test INTo INTo TI1 Test I NT INT TI FO Test IF 0 I Fo TIF1 Test I F 1 I F TTF Test TF TF l TI i i Timer Counter lTA A Timer Counter lAT Timer Counter A RTNI Return Interrupt SED 1 0 Y RED o 0 Y TO Test D Y D Y SEDD n 1 0 n Input Output REDO n o 0 n Display Control lAR p R p A lBR P R p B lRA p A R p lRB p B R p Pp Pattern Generation NOP No Operation NOTE 1 XY after a m...

Page 219: ...ted by Mask Note But when program evalua OPtion list or by program using internal tion with HD44797E set register R6 up the option with the Mask Option List Program register as LCD IV 5 Crystal for R6 0 No crystal for timer Timer R6 1 With crystal for timer Internal R62 0 With internal halt Halt R62 1 No internal halt I O Condition R63 0 Enable at Halt state R63 1 Disable Refer to the manual as fo...

Page 220: ...uction at Reset HALT state is released when system clock keeps it 64 clock after receiving halt release HALT Release I HALT signal I 12 HALT Executes immediately after releasing H64 CIOCk HALT I HALT state 1 Operating state Maximum Total 13 Output Current 1 45mA 25mA I01 Vee 5 0 5V Vee 5 0 5V Rf Oscillation 1 ms Rf Oscillation 10ms Reset Pulse External Clock Operation 4 ms External Clock Operation...

Page 221: ...4 BIT SINGLE CHIP MICROCOMPUTER HMCS400 SERIES ...

Page 222: ...220 ...

Page 223: ...on Execution Time 2 IlS Two Low Power Dissipation Modes Standby Stops instruction execution while keeping clock oscillation and interrupt functions in operation Stop Stops instruction execution and clock oscil lation while retaining RAM data On Chip Oscillator External Connection of Crystal Ceramic Filter or Resistor externally drivable SOFTWARE FEATURES Instruction Set Similar to and More Powerfu...

Page 224: ... R R Roo R1J R Rn R o R R lsa R St Vee _____ r R o SCK Top View BLOCK DIAGRAM r RA L __ _____ J R R A JA so S SCK r RuAnAuA R RIIRIIA I ________ 1 L _______ _ J High Voltage Pins 222 Top View 03 02 D Do GNO OSC csc mT RESET RI3 Ru RII RIO Ru Ru RII AIO Ru A72 AESET flSf osc oSCI Icc GND _ _ _ _ _ _ r l l r i I I I I I AI A R R I 10 0 0 1 Ou 011 0 1 D O o O D O 0 0 0 0 I________ JL ______ _________...

Page 225: ... conditions are exceeded it may cause the malfunction and affect the reliability of LSI Note 21 Note 31 Note 41 Note 5 Note 61 Note 71 Note S Note 91 Note 10 Note 111 Note 121 All voltages are with respect to GNO Applied to standard pins Applied to high voltage pins Total allowanca of input current is the total sum of input current which flow in from all I O pins to GNO simultaneously Total allowa...

Page 226: ...RESET IIILI TNT i NI Vin OV to Vee 1 A 1 Leakage Current SI SO OSCI Crystal or Ceramic Filter Current Oscillator 2 0 mA 2 6 Dissipation in Icc Vee Vee 5V Option tOle 4MHz Active Mode sistor Oscillator Option foe 4MHz 2 4 mA 2 6 Crystal or Ceramic Filter Maximum Oscillator 1 2 mA 3 6 ISBYl Vee Logic Option Operation tOle 4MHz Vee 5V I esistor Oscillator 1 6 mA 3 6 Option Current foe 4MHz Dissipatio...

Page 227: ...terface Stop Pin state RESET GND voltage TEST VfX voltage D 03 R3 R9 VfX voltage 0 0 RO R2 AAO AA1 Vdisp voltage Note 5 Pull down MOS current is excluded Note 6 When fosc x MHzl the Current Dissipation in Operation mode and Standby mode are estimated as follows max value fosc x MHz x max value fosc 4 MHz INPUT OUTPUT CHARACTERISTICS FOR STANDARD PIN Vee 4Vto 6V GND OV VdilP Vee 40V to Vee Ta 20 to...

Page 228: ... RO R2 Output Low Voltaye VOL 04 015 RO R2 150kn to Vcc 4OV Input Output IIILI 04 015 Leakage RO R2 Vin Vee 40V to Vee Current RAO RA1 Pull Oown MOS 04 015 VdilP Vee 35V Id RO R2 125 Current RAO RA1 V in Vee Note 11 Applied to I O pins with with Pull down MOS selected by mask option Note 21 Applied to I O pins with without Pull down MOS PMOS Open Drainl selected by mask option Note 31 Pull down MO...

Page 229: ...NTo 2 tcyc TNTo Low Level Width tlOl INTo 2 tcyc INTI High Level Width tllH INTI 2 tcyc INTI Low Level Width till INTI 2 tcyc RESET High Level Width tRSTH RESET 2 tcyc Input Capacitance Cin all pins f lMHz 15 pF Vin OV RESET Fall Time tRSTf 20 ms Note 1 Oscillator stabilization time is the time until the oscillator stabilizes after VCC reaches 4 0V at Power on or after RESET input level goes to Hi...

Page 230: ...p Transfer Clock Cycle Time tScyc SCK 1 Transfer Clock High tSCKH SCK 0 5 Level Width Transfer Clock Low tSCKL SCK 0 5 Level Width Transfer Clock Rise Time tSCKr SCK Transfer Clock Fall Time tSCKf SCK Serial Output Data toso SO Note 2 Delay Time Serial Input Data Set up Time tSSI SI 500 Serial Input Data Hold Time tHSI SI 150 Note 11 Timing Diagram of Serial Interface SCK Vee 2 0V 0 7Vee 0 8V O 22...

Page 231: ...75 C Vcc 5V ISBY1 max ISBY2 max y V 2 3 4 5 fosdMHz ISBY vs folc Characteristics Crystal Ceramic Filter Oscillator Option 229 4 3 o 4 3 E U2 E 0 2 0 1 6 E 1 2 0 8 J 0 4 o Ta 20 75 C fosc 4MHz max V 2 3 VcC V 4 5 lee vs Vee Characteristics 6 Crystal Ceramic Filter Oscillator Option Ta 20 75 C m ax fosc 4MHz V 2 3 4 5 6 Vcc V lee vs Vee Characteristics Resistor Oscillator Option Ta 20 75 C I BY1 fos...

Page 232: ...acteristics Ta 20 75 C V V I V V IV 7 2 3 VOL V IOL min vs VOL Characteristics Standard Pin Vcc 6V Vcc 5V Vcc 4V 230 2 0 1 6 0 4 o 500 400 Ta 20 75 C fosc 4MHz 2 3 VcdV v V ISBY1 x lAma ISBY2 vax 4 5 6 ISBY vs Vee Characteristics Resistor Oscillator Option Ta 20 75 C 1 max I I I II J I 300 c 200 100 o I V I V L LV r L 10 20 30 40 Vcc Vdisp V Id Pull down MOS Current vs Vee VdisP Characteristics 4 ...

Page 233: ...A are input ports and Rl to RS are Input Output common ports RO to R2 and RA are the high voltage ports R3 to R9 are the standard ports Each pin has the mask option to select its cir cuit type R32 R33 R40 R4 and R42 are also available as 6 Ta 20 75 C 5 V 4 J VV V J V o 2 3 VCC VOHeV V V I 10 V 10 I 4 5 Vcc 6V Vcc 4 5V Vee 4V IOH min vs Vee VOH Characteristics RO R2 Pins INTo INT SCK SI and SO resp...

Page 234: ...he data area and stack area In addition to these areas interrupt control bits o 31 32 47 48 223 224 959 960 1023 RAM mapped Registers Memory Registers MR Data 192Digits Not Used Stack 64Digits 000 OlF 020 02F 030 ODF OEO 3BF 3CO 3FF and special registers are also mapped on the RAM memory space RAM memory map is illustrated in Fig 2 and described in the following paragraph 0 1 2 3 4 5 6 7 8 9 10 11...

Page 235: ... These registers are classified into 3 types Write only Read only and Read Write as shown in Fig 2 These registers cannot be accessed by RAM bit manipulation instruction Memory Registers Stack Area MA O 020 960 level 16 3CO MR 1 021 level 15 MR 2 022 level 14 MR 3 023 level 13 MR 4 024 level 12 MR 5 025 Level 11 MR 6 026 level 10 MR 7 027 level 9 MR 8 028 level 8 Data Area 020 to ODF 16 digits of ...

Page 236: ...ointer is initialized to locate 3FF on the RAM address and is decremented by 4 as data pushed into the stack and incremented by 4 as data restored back from the stack INTERRUPT The MCU can be interrupted by five different sources the external signals INTo INTd timer counter TIMER A TIMER B and serial interface SERIAL In each sources the Interrupt Request Flag Interrupt Mask and interrupt vector ad...

Page 237: ...gram Table 1 Vector Addresses and Interrupt Priority Reset Interrupt Priority Vector addresses RESET 0000 INTo 0002 INT 2 0004 TIMER A 3 0006 TIMER B 4 0008 SERIAL 5 OOOC Table 2 Conditions of Interrupt Service Interrupt source INTo INT TIMER A TlMER B control bits I E IFO IMO 1 0 0 0 IF1 IM1 0 0 IFTA IMTA 1 0 IHS IMTB 1 IFS IMS 235 SERIAL 1 0 0 0 0 1 Don t care ...

Page 238: ...ternal Interrupt Mask IMI has to be set so that the interrupt request by INTI will not be accepted External Interrupt Request Flag lFO 000 2 IF1 001 0 The External Interrupt Request Flags IFO IFI are set at the falling edges of INTo inputs respectively External Interrupt Mask lMO 000 3 IM1 001 1 The External Interrupt Mask is used to mask the external interrupt requests Table 4 External Interrupt ...

Page 239: ... HMCS404C No Yes Yes PC S 0002 PC S 0004 PC S 0006 PC 0008 PC OOOC Fig 8 Interrupt Servicing Flowchart 237 I E O Stack PC Stack CA Stack ST SERIAL Interrupt ...

Page 240: ...interface The Write Signal to the Serial Mode Register stops the transfer clock applied to the Serial Data Register and the Octal Counter And it also reset the Octal Counter to 0 simul taneously When the Serial Interface is in the Transfer State the Write Signal to the Serial Mode Register causes to quit the data transfer and to set the SERIAL Interrupt Request Flag Contents of the Serial Mode Reg...

Page 241: ...ght transfer clock signals or transmit receive discontinued operation by resetting the Octal Counter SERIAL Interrupt Mask lMS 003 1 The SERIAL Interrupt Mask masks the interrupt request Table 8 SERIAL Interrupt Request Flag SERIAL Interrupt Request Flag Interrupt Request o No Yes Table 9 SERIAL Interrupt Mask SERIAL Interrupt Mask Interrupt Request o Enable Disable mask Selection of the Operation...

Page 242: ...in Then reset the SERIAL Interrupt Request Flag and make STS waiting state by writing to the Serial Mode Register SERIAL Inter rupt Request Flag is set again in this procedure and it shows that the transfer clock was invalid and that the transmit receive data were also invalid Table 10 Serial Interface Operation Mode SMR PMR Bit 3 Bit 1 Bit 0 Serial Interface Operating Mode 1 0 0 Clock Continuous ...

Page 243: ...ext clock signal is applied to TIMER B after TIMER B is set to FF TIMER B will be initio alized again and generate overflow output In this case if the auto reload function is selecled TIMER B is initialized accord ing to the value of the Timer Load Register Else if the auto reload function is not selected TIMER B goes to 00 TIMER B Interrupt Request Flag IFTB 002 0 will be set at this overflow out...

Page 244: ...of low order digit is latched at the time when the high order digit is read TIMER A Interrupt Request Flag lFTA 001 2 The TIMER A Interrupt Request Flag is set by the overflow output of TIMER A TIMER A Interrupt Mask lMTA 001 3 TIMER A Interrupt Mask prevents an interrupt request generated by TlMER A Interrupt Request Flag Table 13 TIMER A Interrupt Request Flag TIMER A Interrupt Request Flag o In...

Page 245: ... pull down MOS option When any Input Output common pin is used as input pin it is necessary to select the mask option and output data as shown in Table 18 Output Circuit Operation of Standard Pins with With pull up MOS Option Fig 15 shows the circuit used in the standard pins with with pull up MOS option 8y execution of the output instruction the write pulse will be generated and be applied to the...

Page 246: ...output output output data data data Vee InpiJt H pins input HLT input R90 R93 data data Without pull down MOS With pull down MOS E Applied pins PMOS open drain D Vee HLT HLT I O 0 output o output 04 0 1S common data data RIO R l3 pins Vee RlO Rl3 HL input Vdisp HLT input data data Vee c Vee Q KJ HLT III cJK HLT 0 output Output output data g data pins Roo R03 s Vee 21 I Vdisp Input input IO RAO dat...

Page 247: ...I o e input o e input SI data data HlT HlT Note In the stop mode HlT signal is 0 HlT signal is and I O pins are in high impedance state Table 18 Data Input from Input Output Common Pins I O pin circuit type Possibi Iity Available pin condition of Input for input CMOS No Standard Without pull up pins MOS Yes 1 NMOS open drain With pull up MOS Yes 1 Without pull down High MOS Yes 0 voltage PMOS open...

Page 248: ...0000 Execute program from the top of ROM address Status ST 1 Enable to branch with conditional branch instructions Stack pointer SP 3FF Stack level is O A Without pull 1 Enable to input upMOS Standard pin B With pull up 1 Enable to input MOS C CMOS 1 I O pin 0 Without pull output register 0 Enable to input High voltage down MOS pin E With pull 0 Enable to input down MOS Interrupt Enable Flag I E 0...

Page 249: ...r Table 20 Examples of Oscillator Circuit Circuit configuration Oscillator D OSC Open OSC e sc Rf OSC cerami1 OSC filter T F f L OSC2 C2 _______ GND ATcut parallel resonance crystal O f 2 IOsC Co Remarks Rf 20kn 2 Ceramic filter CSA4 00MG Murata Af 1MO 2 C 30pF 20 C 30pF 20 Wiring between these pins and elements should be as short as possible and never cross the other wirings Refer to Fig 17 Af 1M...

Page 250: ...s is the additional current to the current dissipation in Standby Mode lSBY1 ISBY2 Fig 18 MCU Operation Mode Transition Standby Mode The SBY instruction puts the MCU into the Standby mode In the Standby mode the oscillator circuit is active and timer 248 counter and serial interface continue working On the other hand the CPU stops since the clock related to the instruction execution stops Register...

Page 251: ...t Processor Clocks A Reset MCU Fig 19 MCU Operating Flowchart Stop mode 11 IIITI I I IIIIIITI I I IIIIIITI I I IIIIIITI I TI III ITI I TIII II 000 _ t I Oscillator RESET STOP instruction execution more than stabilization time tAcl Fig 20 Timing Chart of Recovering from Stop Mode 249 ...

Page 252: ...dressing The direct addressing instruction consists of two words and the second word 10 bits following Op code the first word is used as the RAM address Memory Register Addressing The Memory Register Addressing can access 16 digits Memory Register MR from 020 to 02F by using the LAMR and XMRA instruction W Register X Register Y Register r r a Register Indirect Addressing Instruction 1st Word Instr...

Page 253: ... Page Addressing Mode The program branches to the zero page subroutine area which is located on the address from 0000 to 003F using CAL instruction When CAL instruction is executed 6 bit immediate data is placed in low order six bits of program counter PCs to PCo and O s are placed in high order ei lt bits pCl3 to PCe The branch destination by BR instruction on the broundary between pages is given...

Page 254: ...r and B Register When bit 9 is I 8 bits of referred ROM data are written into the RI and R2 port output register When both bit 8 and 9 are I ROM data are written into the accumulator and B Register and also to the Rl and R2 port output register at a same time The P instruction has no effect on the program counter INSTRUCTION SET The HMCS400 series provide 99 instructions These instruc tions are cl...

Page 255: ...1 000 1 0 b i2 i io i X 1 1 Load V from Immediate LVI i 1 0000 1 b i2 i io i V 1 1 Load X from A LXA 0011101000 A X 1 1 Load Y from A LYA 0011011000 A Y L 1 Increment Y IY 0001011100 Y 1 Y NZ 1 1 Decrement Y DY 001 101 1 1 1 1 Y 1 Y NB 1 1 Add A to Y AYY 0001010100 Y A Y OVF 1 1 Subtract A from Y SYY 0011010100 Y A Y NB 1 1 Exchange X and SPX XSPX 0000000001 X SPX 1 1 Exchange Y and SPY XSPY 00000...

Page 256: ...ment B COMB 0101000000 8 B 1 1 Rotate Right A with Carry ROTR 0010100000 1 1 Rotate Left A with Carry ROTL 0010100001 1 1 Set Carry SEC 0011 101111 1 CA 1 1 Reset Carry REC 0011101100 O CA 1 1 Test Carry TC 0001 101111 CA 1 1 Add A to Memory AM 0000001000 M A A OVF 1 1 Add A to Memory AMD d 9Ja 6 5 4J3 2 1 o M A A OVF 2 2 Add A to Memory with Carry AMC 0000011000 M A CA A OVF 1 1 Add A to Memory w...

Page 257: ... 1 n no M n 1 1 Test Memory Bit TMD n d q 1 1 000 1 1 n no dg da d7 d6 ds d d3 d2 d do M n 2 2 Table 29 ROM Address Instruction IMNEMONIC OPERATION OPERATION CODE FUNCTION STATUS CYCL Branch on Status 1 BR b 1 1 b7b6b5b4bJb2b bo 1 1 1 Long Branch on Status 1 BRL u o 1 0 1 1 1 PJP2P PO 1 2 2 dg da d7 d6 d5 d d3 d2 d do Long Jump Unconditionally JMPL u o1 0 1 0 1 PJP2P PO dgdsd7d6d5d d3d2d do 2 2 Su...

Page 258: ...nl IOMI B TBR C XMB XY I l E 1 o LMAoY Xi Isvvl E TO SEDI F LWI 0 LBI 1 LYI 2 LXI 3 LAI 4 LBR S LAR 6 REDO 7 LAMR S AI 9 LMIIY A TOO B ALEI C LRB 0 LRA E SEOO F XMRA D 1 word 2 cycle Instruction IAMI IORMI IAMCI IEORMI 4 4 ILABI liB I IIA9 t1 IIY I I I TC 4 1 REM n 2 I TM n 2 ISMCI IANMI IDASI ILAY p 4 ILBAI I DB I LYAl lOY LXAI IRECI ISEC i 4 4 4 4 4 m 4 I m 4 I m 4 m 4 4 4 m 4 4 m 4 I m 4 I m 4 ...

Page 259: ... A91 r a A9 R i Input Output r A2 RlI Input Output i Input Output I AAO AA Date of Order Customer Dept Name AOM Code Name LSI Type Numbef Hitachi s entry I O OPTION INPUT OUTPUT A B C D E Input Output Input Output Input Output Input Output Input Output Input Output Input Output Input Output Input Output Input Output Input Output c Input Output Output 0 Output c en Output Output Output Output Outpu...

Page 260: ...clock genera tion while retaining RAM data Clock Generator External Connection of Crystal Resonator or Ceramic Filter Resonator externally drivable Power Voltage Range 5V 10 I O Pin Circuit Form All standard pins are without pull up MOS All high voltage pins are without pull down MOS Shrink Type 64 Pin EPROM On package SOFTWARE FEATURES Software Compatible with HMCS404C 404AC Instruction Set Simil...

Page 261: ... ____ L L i I I I I SP EPROM HN482764 HN27C64 HN4827128 PC n rl n n l l l n T r r l r r r r rrrrl rTT n R43R42 R4 R40 R32 R3fbo R23R22R2 R20j R 3R12R R o R03 R02 Ro Roo p SO 0130120 OI00S0S0106 D 0 03 02 0 Do SO SI SCi INT iNTo _________ J i ________ J L ________ J r L ___ High Voltage Pins g o n c G a I C 0 en ...

Page 262: ...e 21 Note 31 Note 41 Note 51 Note 61 Note 71 Note SI Note 91 Note 101 Note 111 Note 121 All voltages are with respect to GND Applied to standard pins Applied to high voltage 1 0 pins Total allowance of input current is the total sum of input current which flow in from all 1 0 pins to GND simultaneously Total anowance of output current is the total sum of the output current which flow out from Vee ...

Page 263: ...n Voltage Note 1 Note 2 Output buffer current are excluded The MCU is in the reset state The input output current does not flow Test Conditions MCU state Reset state in Operation Mode Pin state RESET TEST Vee voltage Do 0 R3 R9 Vee voltage min 0 7Vee 0 7Vee Vee O S 0 3 0 3 0 3 Vee 1 O Vee 0 3 2 0 Note 3 O 0 RO R2 RAIJ RA1 Vec Vee 40V The timer counter with the fastest clock and input output curren...

Page 264: ...Input Output IIILI Do D3 Vin OV Vee Leakage Current R3 R9 Note 11 Output buffer current are excluded INPUT OUTPUT CHARACTERISTICS FOR HIGH VOLTAGE PIN Vee 4 5V to 5 5V GND OV Ta 20 to 75 C if not specified Item Symbol Pin Name Test Conditions Input High VIH D4 DI5 R1 Voltage R2 RAO RA1 Input Low VIL 04 015 R1 Voltage R2 RAO RA1 D4 015 lnH 15mA Output High IOH 9mA Voltage VOH IOH 3mA RO R2 I OH 1 B...

Page 265: ...Io High Level Width tlOH INTO 2 tcyc INTo Low Level Width tlOl TNTo 2 tcyc INTI High Level Width tllH lNTi 2 tcyc INTI Low Level Width till INTi 2 tcyc RESET High Level Width tRSTH RESET 2 tcyc Input Capacitance Cin all pins f 1MHz 15 pF Vin OV Reset Fall Time tRSTf 20 ms Note 1 Oscillator stabilization time is the time until the oscillator stabilizes after VCC reaches 4 SV at Power on or after RE...

Page 266: ...sfer Clock Cycle Time tScvc SCK 1 Transfer Clock High tSCKH SCK 0 5 Level Width Transfer Clock Low tSCKL SCK 0 5 Level Width Transfer Clock Rise Time tSCKr SCK Transfer Clock Fall Time tSCKf SCK Serial Output Data toso SO Note 2 Delay Time Serial Input Data Set up Time tSSI SI 300 Serial Input Data Hold Time tHSI SI 150 INote 11 Timing Diagram of Serial Interface 5CK Vcc 2 0VI0 7Vccl 0 8VI0 22Vcc ...

Page 267: ...mic resonator Ta 20 75 e 5 Veej5 5 x V VC6 4 5V r V V V V E V 2 VOLIV IOL min VS VOL characteristics Standard Pin 3 6 265 4 3 E U2 2 o 2 0 1 6 E 1 2 j 0 8 0 4 o E c E J 9 Ta 20 75 C fosc 4MHz 2 3 Vcc V 4 Icc vs Vec characteristic crystal ceramic resonator Ta 20 75 C fosc 4MHz max V 5 6 ISBY1 30 20 10 o max V V ISBY2 max 2 3 4 5 VcC V ISBY VS Vee characteristics crystal ceramic resonator TaT o _I 7...

Page 268: ...put ports and RI to RS are Input Output common ports RO to R2 and RA are the high voltage ports R3 to R9 are the standard ports iU2 R33 R40 R41 and R42 are also available as INTo INTI SCK SI and SO respectively For details see INPUT OUTPUT INTo INTI These are the input pins to interrupt MCU operation exter nally INTI can be used as an external event input pin for TIMER B INTo and INTI are also ava...

Page 269: ... J S3FF Interrupt Control Bits SOOO SOOl S002 1 _______ _ S003 I Po_rt_M o d_e Re g_ _ _PM_R_ _W S004 Se ria I M o de R e g SM R W SS00005 6 6 Serial Data Reg lower SRl R W Serial Data Reg Upper SRU R W S007 Timer Mode Reg A TMA W S008 9 Timer Mode Reg 8 TM8 W S009 10 TIMER B TCBl TlRl R W SOOA 11 TCBU TlRU R W SOOB 12 SOOC Not Used 3 1 SOIF Two registers are mapped on same address Read Only W Wri...

Page 270: ...se registers are classified into 3 types Write only Read only and Read Write as shown in Fig 2 These registers cannot be accessed by RAM bit manipulation instruction Date Are 020 to 21 F Memory Registers Stack Area MR O 020 960 Level 16 S3CO MR l 021 Level 15 MR 2 022 Level 14 MR 3 023 Level 13 MR 4 024 Level 12 MR 5 025 Level 11 MR 6 026 Level 10 MR 7 027 Level 9 MR 8 028 Level 8 16 digits of 020...

Page 271: ...r is initialized to locate 3FF on the RAM address and is decremented by 4 as data pushed into the stack and incremented by 4 as data restored back from the stack INTERRUPT The MCU can be interrupted by five different sources the external signals INTo INl timer counter TIMER A TIMER B and serial interface SERIAL In each sources the Interrupt Request Flag Interrupt Mask and interrupt vector address ...

Page 272: ...sses and Interrupt Priority Reset Interrupt Priority Vector addresses RESET 0000 INlo 1 0002 INTI 2 0004 TIMER A 3 0006 TIMER B 4 0008 SERIAL 5 OOOC Table 2 Conditions of Interrupt Service Vector Addr ss Interrupt source INTo INTI TIMER A TIMER B control bits I E 1 1 1 1 IFO IMO 1 0 0 0 IF1 IM1 1 0 0 IFTA IMTA 1 0 IFTB IMTB 1 IFS IMS 270 SERIAL 1 0 0 0 0 1 Don t care ...

Page 273: ...nal Interrupt Mask IMl has to be set so that the interrupt request by INTI will not be accepted External Interrupt Request Flag lFO 000 2 IF1 001 0 The External Interrupt Request Flags IFO IF l are set at the falling edges of INT0 INTI inputs respectively External Interrupt Mask lMO 000 3 IM1 001 1 The External Interrupt Mask is used to mask the external interrupt requests Table 4 External Interru...

Page 274: ...HD614P080S No Yes Yes PC 0002 PC 0004 PC 0006 PC 0008 PC OOOC Fig 8 Interrupt Servicing Flowchart 272 I E O Stack PC Stack CA Stack ST SERIAL Interrupt ...

Page 275: ...rial interface The Write Signal to the Serial Mode Register stops the transfer clock applied to the Serial Data Register and the Octal Counter And it also reset the Octal Counter to 0 simul taneously When the Serial Interface is in the Transfer State the Write Signal to the Serial Mode Register causes to quit the data transfer and to set the SERIAL Interrupt Request Flag Contents of the Serial Mod...

Page 276: ...t after the eight transfer clock signals or transmit receive discontinued operation by resetting the Octal Counter SERIAL Interrupt Mask OMS 003 1 The SERIAL Interrupt Mask masks the interrupt request Table 8 SERIAL Interrupt Request Flag SERIAL Interrupt Request Flag Interrupt Request o No Yes 274 Table 9 SERIAL Interrupt Mask SERIAL Interrupt Mask Interrupt Request o Enable Disable masks Selecti...

Page 277: ...gain Then reset the SERIAL Interrupt Request Flag and make STS waiting state by writing to the Serial Mode Register SERIAL Inter rupt Request Flag is set again in this procedure and it shows that the transfer clock was invalid and that the transmit receive data were also invalid Table 10 Serial Interface Operation Mode SMR PMR Bit 3 Bit 1 Bit 0 Serial Interface Operating Mode 1 0 0 Clock Continuou...

Page 278: ... next clock signal is applied to TIMER B after TIMER B is set to SFF TIMER B will be initio alized again and generate overflow output In this case if the auto reload function is selected TIMER B is initialized accord ing to the value of the Timer Load Register Else if the auto reload function is not selected TIMER B goes to SOO TIMER B Interrupt Request Flag IFTB S002 O will be set at this overflo...

Page 279: ...he count value oflow order digit is latched at the time when the high order digit is read TIMER A Interrupt Request Flag lFTA 001 2 The TIMER A Interrupt Request Flag is set by the overflow output of TIMER A TIMER A Interrupt Mask lMTA 001 3 TIMER A Interrupt Mask prevents an interrupt request generated by T1MER A Interrupt Request Flag Table 13 TIMER A Interrupt Request Flag TIMER A Interrupt Req...

Page 280: ... pMOS open d am tioutput common Pshown in Table 18 When any mput the output data as it is necessary to se t Forms I O Pin Circul MOS W thout pull up NMOS open dram lT n t HlT output data o s output HlT I data HLT 1 h input data 278 Note Vee HLT outPut o r data 1 and I O 0 HLT signal IS mode HLT signal IS In the stop dance high Impe S pins are In II up MO Without pu NMOS open dram SO input data HlT...

Page 281: ...nter PC 0000 Execute program from the top of ROM address Status ST 1 Enable to branch with conditional branch instructions Stack pointer SP 3FF Stack level is O Standard pin Without pull up 1 Enable to input I O output MOS register High voltage Without pull down pin MOS 0 Enable to input Interrupt Enable Flag I E 0 Inhibit all interrupts Interrupt flag Interrupt Request Flag I F 0 No interrupt req...

Page 282: ...r Crystal resonator Table 20 Oscillator Circuit Example Circuit configuration Oscillator OSCI Open OSC CI ceramicfc l filter C2 GND OSCI OSC2 GND ATcut parallel resonance crystal OS OSC2 Co Remarks Ceramic filter CSA 4 00MG Murata Rf lMn 2 Cl 33pF 20 C 33pF 20 Ceramic filter CSA 6 00MG Murata Rf lMn 2 Cl 30pF 20 C2 30pF 20 Wiring between these pins and elements should be as short as possible and n...

Page 283: ...e Standby mode In the Standby mode the oscillator circuit is active and timer 281 counter and serial interface continue working On the other hand the CPV stops since the clock related to the instruction execution stops Registers RAM and Input Output pins retain the state they had just before going into the Standby mode The Standby mode is canceled by the MCV reset or interrupt request When cancele...

Page 284: ...HD614P080S Oscillator Active Peripheral Clocks Active All Other Clocks Stop Fig 18 MCU Operating Flowchart 282 ...

Page 285: ... X Register and Y Register is used as the RAM address in this mode RAM Address Direct Addressing The direct addressing instruction consists of two words and the second word l0 bits following Op code the first word is used as the RAM address Memory Register Addressing The Memory Register Addressing can access 16 digits Memory Register MR from 020 to 02F by using the LAMR and XMRA instruction W Regi...

Page 286: ...de Program Counter 8 bit immediate data Zero Page Addressing Mode The program branches to the zero page subroutine area which is located on the address from 0000 to 003F using CAL instruction When CAL instruction is executed 6 bit immediate data is placed in low order six bits of program counter PC5 to PCO and D s are placed in high order eight bits pC 13 to PC6 The branch destination by BR instru...

Page 287: ...ritten into the Rl and R2 port output register When both bit 8 and 9 are 1 ROM data are written into the acc umulator and B register and also to the Rl and R2 port output register at a same time The P instruction has no effect on the program counter INSTRUCTION SET The HMCS400 series provide 99 instructions These instruc tions are classified into 10 groups as follows I Immediate Instruction 2 Regi...

Page 288: ...diate LXI i 1 000 1 0 iJ i2 i io i X 1 1 Load Y from Immediate LYI i 1 0000 1 i3 i2 i io i Y 1 1 Load X from A LXA 0011101000 A X 1 1 Load Y from A LYA 0011011000 A Y 1 1 Increment Y IY 0001011100 Y 1 Y NZ 1 1 Decrement Y DY 0011011111 Y 1 Y NB 1 1 Add A to Y AYY 0001010100 Y A Y OVF 1 1 Subtract A from Y SYY 0011010100 Y A Y NB 1 1 Exchange X and SPX XSPX 0000000001 X SPX 1 1 Exchange Y and SPY X...

Page 289: ...0 A 1 A 1 1 Complement B COMB 0101000000 13 B 1 1 Rotate Right A with Carry ROTR 0010100000 1 1 Rotate Left A with Carry ROTL 0010100001 1 1 Set Carry SEC 001 1 101 1 1 1 1 CA 1 1 Reset Carry REC 001 1 101 100 O CA 1 1 Test Carry TC 0001 101 111 CA 1 1 Add A to Memory AM 0000001000 M A A OVF 1 1 Add A to Memory AMD d 9Je 6 s J3 2 M A A OVF 2 2 Add A to Memory with Carry AMC 0000011000 M A CA A OVF...

Page 290: ... 1 00 0 1 1 nIno M n 1 1 Test Memory Bit TMD n d 9 7 6 3 2 Jg M n 2 2 Table 29 ROM Address Instruction OPERATION MNEMONIC OPERATION CODE FUNCTION STATUS CYCL Branch on Status 1 BR b 1 1 b7bebeb Jb2b bo 1 1 1 long Branch on Status 1 BRL u 7 1 2 2 Long Jump Unconditionally JMPl u 7 l3tJ2it 2 2 Subroutine Jump on Status 1 CAL a o 1 1 1 a5a4a3a2a aO 1 1 2 long Subroutine Jump on Status 1 CAll u IJ 7JI...

Page 291: ...T Tll 10MI B TBR C XMB XY jllEMj o LMADY Xj ISYVI E TOj 15EOI F LWI 0 LBI LYI 2 LXI 3 LAI 4 LBR 5 LAR 6 REDO 7 LAMR 8 AI 9 LMIIY A TOO B ALEI C LRB 0 LRA E SEOO F XMRA 1 word 2 cycle Instruction IAMI IORMI IAMCI IEORMI i 4 i 4 ILABI 1 18 1 IlA9 Ij IIYJ I I TC i 4 I REM n 2 I TM n 2 ISMCI IANMI 10ASI ILAY p 4 jLBAj I DB I LYAI lOY IlXAI IRECI 15EC 4 i 4 i 4 i 4 i 4 m 4 I m 4 I m 4 m 4 i 4 i 4 m 4 i...

Page 292: ...ty It is recommended to use new one when applied in production Table 33 Difference between the HD614P08OS and HMCS404C HMCS404AC Item HD614P080S HMCS404C HMCS404AC Minimum instruction 1 33p s 2p s 1 33p s execution time Power supply voltage 4 5 to 5 5 V 4 t06 V 4 5 to 6 V 04 096 words x 10 bits 4 096 words x 10 bits ROM using standard EPROM 2764 08 192 words x 10 bits Mask ROM using standard EPROM...

Page 293: ...EVALUATION CHIP FOR 4 BIT SINGLE CHIP MICROCOMPUTERS ...

Page 294: ... DIE pins for selecting applicable chips APPLICABLE CHIPS HMCS42C 43C 44C 45C FUNCTION Instruction Characteristics etc Same as the HMCS45C Address Extemal ROM 2k Address Output Direct interface with EPROM Ao to A Instruction Input EPROM or CMOS RAM or NMOS RAM 0 to 0 01 Direct interface with TTL CMOS PMOS Selecting Input Pin Timer Halt Input I O Enable Disable Selecting Pin at Halt Output Pins exc...

Page 295: ...cess pins for user program external memory Divide 1 instruction cycle by two The first half is the address from Ao to At and the latter half is instruction 2 A oIA inputs from 0 to 0 o Access pins for external user program memory Divide 1 instruction cycle by two The first half is Al 0 and the latter half Is A I 3 A I Unusable Be open always 4 X1 S2 to X S u Access pins for data RAM Divide 1 in st...

Page 296: ...IN NAME V l V2 V3 OSC 1 m Power Supply for LCD External Clock Input Pin Halt Pin Roo to R03 Input Port RIO to R23 I O Port R30 to R33 Output Port Do to 0 13 I O Port D1 XO D 1JXI I O Port or Clock Input Pin for Timer INT o INT 1 Interrupt COM 1 to COM Common Signal Pin SEG 1to SEG32 Segment Signal Pin Ao to All Program Memory Access Pin 0l Oe to 0J010 Instruction Input Pin 4 1 2 Clock Signal TSTP ...

Page 297: ...NEW DEVICES ...

Page 298: ...296 ...

Page 299: ... interrupts High Speed Operation Minimum Instruction Execution Time 1 33 Ls Two Low Power Dissipation Modes Standby Stops instruction execution while keeping clock oscillation and interrupt functions in op eration Stop Stops instruction execution and clock oscilla tion while retaining RAM data On Chip Oscillator External Connection of Crystal or Ceramic Filter externally drivable SOFTWARE FEATURES...

Page 300: ... L _____ 1 Ru Ru R RIO R R RT RT Roo R RI Ro R Ru R Rs 0 D O 01 0 D D D 0 02 D D GND OSC osc mT RESET R 3 R02 Ro Roo Ru RI2 RI RIO R Rn R7I R R R SO R 51 R ffi Re J l r R R J High Voltage Pins 298 RESg m I OSC Osc Vee Nl ROM O D D o GNO osc osc Tm RESET RII Roo RI R R RIO R73 Rn tOt8xlObil PC r r Ro RotRo Roo DtlD D IDIlDa D D D D D D D D D D D _______ J L __________________ J ...

Page 301: ...s If these conditions are exceeded it may cause the malfunction and affect the reliability of LSI Note 2 Note 3 Note 4 Note 5 Note 6 Note 7 Note 8 NoteS Note 10 Note 11 Note 12 All voltages are with respect to GND Applied to standard pins Applied to high voltage pins Total allowance of input current is the total sum of input current which flow in from all I O pins to GND simultaneously Total allow...

Page 302: ...ut High IOH 1 0 rnA Vee 1 O V Voltage VOH SCK SO IOH 0 01 rnA Vee 0 3 V Output Low VOL SCK SO IOL 1 6 rnA 0 4 V Voltage Input Output RESET SCR IIILI INTo INTI Vin 0 V to Vee 1 IlA 1 Leakage Current SI SO OSCI Current Vee 5 V Dissipation in lee Vee 3 0 rnA 2 6 Active Mode fosc 6 MHz Maximum Logic Operation ISBY1 Vee Vee 5 V 1 8 rnA 3 6 Current fosc 6 MHz Dissipation in Minimum Logic Operation Stand...

Page 303: ...Interface Stop Pin state RESET GND voltage TEST Vee voltage D 0 R3 R9 V cc voltage D DIS RO R2 RAQ RA1 Vdisp voltage Note 5 Pull down MOS current is excluded Note 6 When fosc x MHz the Current Dissipation in Operation mode and Standby mode are estimated as follows max value fosc X MHz x max value fosc 6 MHz INPUT OUTPUT CHARACTERISTICS FOR STANDARD PIN Vee 4 5V to 6V GND OV Vdisp Vee 40V to Vee Ta...

Page 304: ...lp Vee 40V Output Low RO R2 Volta ge VOL 04 015 RO R2 150kn to Vcc 4OV Input Output HILI 04 015 Leakage RO R2 Yin Vee 40V to Vee Current RAO RA1 Pull Down MOS 04 015 Vdisp Vee 35V Id RO R2 125 Current RAO RA1 Yin Vee Note 1 Applied to I O pins with Pull down MOS selected by mask option Note 2 Applied to I O pins without Pull down MOS PMOS Open Drain selected by mask option Note 3 Pull down MOS cur...

Page 305: ...1 L INT 2 tcyc 3 RESET High Level Width tRSTH RESET 2 tcyc 4 Input Capacitance Cin all pins f 1 MHz 15 pF Vin 0 V RESET Fall Time tRSTf 20 ms 4 Note 1 Oscillator stabilization time is the time until the oscillator stabilizes after VCC reaches 4 5V at Power on or after RESET input level goes High by resetting to quit the stop mode by MCU reset The circuits used to measure the value are described be...

Page 306: ...ame Conditions min typ Transfer Clock Cycle Time tSCYC SCK 1 Transfer Clock High tSCKH SCK 0 5 Level Width Transfer Clock Low tscKL SCK 0 5 Level Width Transfer Clock Rise Time tSCKr SCK Transfer Clock Fall Time tSCKf SCK Serial Output Data toso SO Note 2 Delay Time Serial Input Data Set up Time tSSI SI 300 Serial Input Data Hold Time tHSI SI 150 Note 1 Timing Diagram of Serial Interface 5CK Vee 2...

Page 307: ...min 6 Vcc 6V Vcc SV V V Vcc 4 SV E J E S o V JV V 2 VOL V IOL min vs VOL Characteristics Standard Pin 3 305 2 4 2 0 1 6 0 4 o SOO 400 300 200 100 o Ta 20 7S C SBY 1 x fosc 6MHz mar V ISBY2 max 2 3 VcdV 4 V S ISBY vs Vee Characteristics Crystal Ceramic Filter Oscillator 6 I Ta 20 7SoC max I lL J I 1 I V ILV V tyP min 10 20 30 40 50 Vcc Vdisp V Id Pull down MOS Current vs Vee VdiSP Characteristics 4...

Page 308: ...rts RO to R2 and RA are the high voltage ports R3 to R9 are the standard ports Each pin has the mask option to select its cir cuit type R32 R33 R40 R41 and R42 are also available as 306 6 T 26 75 C Vcc 6V 5 V Vcc 4 5V 4 V o 2 3 4 5 VCC VOH V IOH min vs Vee VOH Characteristics RO R2 Pins INTo INTI SCK SI and SO respectively For details see INPUT OUTPUT INTo INTI These are the input pins to interrup...

Page 309: ...control bits and special registers are also mapped on the RAM memory space RAM memory map is illustrated in Fig 2 and described in the following paragraph o 31 32 RAM mapped Registers Memory Registers MR 000 01F 020 0 1 Interrupt Control 8its 2 3 4 Port Mode Reg PMR W 47 48 02F 030 000 001 002 003 004 005 006 007 008 009 OOA 008 OOC 223 224 959 960 1023 Data 192Digits Not Used Stack 64Digits R Rea...

Page 310: ...egisters are classified into 3 types Write only Read only and Read Write as shown in Fig 2 These registers cannot be accessed by RAM bit manipulation instruction Memory Registers Stack Area MR O 020 960 Level 16 3CO MR l 021 Level 15 MR 2 022 Level 14 MR 3 023 Level 13 MR 4 024 Level 12 MR 5 025 Level 11 MR 6 026 Level 10 MR 7 027 Level 9 MR 8 028 Level 8 Data Area 020 to ODF 16 digits of 020 to 0...

Page 311: ...16 levels The Stack Pointer is initialized to locate 3FF on the RAM address and is decremented by 4 as data pushed into the stack and incremented by 4 as data restored back from the stack INTERRUPT The MCU can be interrupted by five different sources the external signals INTo INTd timer counter TIMER A TIMER B and serial interface SERIAL In each sources the Interrupt Request Flag Interrupt Mask an...

Page 312: ...ector Addresses and Interrupt Priority Reset Interrupt Priority Vector addresses RESET 0000 INTo 1 0002 INTI 2 0004 TIMER A 3 0006 TIMER B 4 0008 SERIAL 5 OOOC Table 2 Conditions of Interrupt Service Address Interrupt source INTo INTI TIMER A TIMER B control bits I E 1 1 1 1 IFO IMO 1 0 0 0 IF1 IM1 1 0 0 IFTA IMTA 1 0 IFT B IMTB 1 IFS IMS 310 SERIAL 1 0 0 0 0 1 Don t care ...

Page 313: ...rnal Interrupt Mask 1M has to be set so that the interrupt request by INTI will not be accepted External Interrupt Request Flag I FO 000 2 IF1 001 0 The External Interrupt Request Flags IFO 1Ft are set at the falling edges of INTo INT1 inputs respectively External Interrupt Mask lMO 000 3 IM1 001 1 The External Interrupt Mask is used to mask the external interrupt requests Table 4 External Interru...

Page 314: ...HMCS404AC No Yes PC 0002 PC 0004 PC 0006 PC 0008 PC OOOC Fig 8 Interrupt Servicing Flowchart 312 I E O Stack PC Stack CA Stack ST No SERIAL Interrupt ...

Page 315: ...rating state of serial interface The Write Signal to the Serial Mode Register stops the transfer clock applied to the Serial Data Register and the Octal Counter And it also reset the Octal Counter to 0 simul taneously When the Serial Interface is in the Transfer State the Write Signal to the Serial Mode Register causes to quit the data transfer and to set the SERIAL Interrupt Request Flag Contents...

Page 316: ...fter the eight transfer clock signals or transmit receive discontinued operation by resetting the Octal Counter SERIAL Interrupt Malk lMS 003 1 The SERIAL Interrupt Mask masks the interrupt request Table 8 SERIAL Interrupt Request Flag SERIAL Interrupt Request Flag Interrupt Request o No Yes 314 Table 9 SERIAL Interrupt Mask SERIAL Interrupt Mask Interrupt Request o Enable Disable mask Selection o...

Page 317: ... Then reset the SERIAL Interrupt Request Flag and make STS waiting state by writing to the Serial Mode Register SERIAL Inter rupt Request Flag is set again in this procedure and it shows that the transfer clock was invalid and that the transmit receive data were also invalid Table 10 Serial Interface Operation Mode SMR PMR Bit 3 Bit 1 Bit 0 Serial Interface Operating Mode 1 0 0 Clock Continuous Ou...

Page 318: ... signal is applied to TIMER B after TIMER B is set to FF TIMER B will be initio alized again and generate overflow output In this case if the auto reload function is selected TIMER B is initialized accord ing to the value of the Timer Load Register Else if the auto reload function is not selected TIMER B goes to 00 TIMER B Interrupt Request Flag IFTB 002 0 will be set at this overflow output 316 T...

Page 319: ...er digit The count value of low order digit is latched at the time when the high order digit is read TIMER A Interrupt Request Flag IFTA 001 2 The TIMER A Interrupt Request Flag is set by the overflow output of TIMER A TIMER A Interrupt Mask IMTA 001 3 TIMER A Interrupt Mask prevents an interrupt request generated by TIMER A Interrupt Request Flag Table 13 TIMER A Interrupt Request Flag TIMER A In...

Page 320: ...e pin is selected as With pull down MOS option When any Input Output common pin is used as input pin it is necessary to select the mask option and output data as shown in Table 18 Output Circuit Operation of Standard Pins with With pull up MOS Option Fig 15 shows the circuit used in the standard pins with with pull up MOS option By execution of the output instruction the write pulse will be genera...

Page 321: ...ci output output ut data data Vee Input H pins input HLT input R90 R93 data data Without pull down MOS With pull down MOS E Applied pins PMOS open drain 0 Vee HLT kCJ HLT 1 0 0 output o output 0 4 015 data data common RIO R 13 pins Vee Rlo Rn HIT input Vdisp HLT input data data II Vee c Vee a KJ HLT Gl o S3ret H LT output CI output l Output data 5 data pins Vee Roo Ro3 oJ I Vdisp Input input P RAO...

Page 322: ...TI o e i n p u t o e i n p u t SI data data HLT HLT Note In the stop mode HLT signal is 0 HLT signal is 1 and I O pins are in high impedance state Table 18 Data Input from Input Output Common Pins I O pin circuit type Possibi lity Available pin condition of Input for input CMOS No Standard Without pull up pins MOS Yes 1 NMOS open drain With pull up MOS Yes 1 Without pull down High MOS Yes 0 voltag...

Page 323: ... 0000 Execute program from the top of ROM address Status ST 1 Enable to branch with conditional branch instructions Stack pointer SP 3FF Stack level is O A Without pull 1 Enable to input upMOS Standard pin B With pull up 1 Enable to input MOS C CMOS 1 I O pin 0 Without pull output register 0 Enable to input High voltage down MOS pin E With pull 0 Enable to input down MOS Interrupt Enable Flag I E ...

Page 324: ... Oscillator Circuit Circuit configuration Oscillator Open OSC2 Cl cerami1 filter C2 GND OSCl GND ATcut parallel resonance crystal OS C2 Co Remarks Ceramic filter CSA6 00MG Murata Rf lMn 2 C 30pF 20 Cz 30pF 20 Wiring between these pins and elements should be as short as possible and never cross the other wirings Refer to Fig 17 Rf lMn 2 C 1O 22pF 20 Cz 10 22pF 20 Crystal ATcut parallel resonance cr...

Page 325: ...the additional current to the current dissipution in Standby Mode lSBY1 ISBY2 Fig 18 MCU Operation Mode Transition counter and serial interface continue working On the other hand the CPU stops since the clock related to the instruction execution stops Registers RAM and Input Output pins retain the state they had just before going into the Standby mode The Standby mode is canceled by the MCU reset ...

Page 326: ...l Clocks Active All Other Clocks Stop Restart Processor Clocks A Reset MCU Fig 19 MCU Operating Flowchart Stop mode I tres I STOP instruction execution more than stabilization time tRcl Fig 20 Timing Chart of Recovering from Stop Mode 324 ...

Page 327: ...Direct Addressing The direct addressing instruction consists of two words and the second word IO bits following Op code the first word is used as the RAM address Memory Register Addressing The Memory Register Addressing can access 16 digits Memory Register MR from 020 to 02F by using the LAMR and XMRA instruction W Register X Register V Register a Register Indirect Addressing Instruction 1st Word ...

Page 328: ... JMPL BRL CALL Instruction 1st Word instruction on the boundary between pages is in the next page Refer to Fig 24 Zero Page Addressing Mode The program branches to the zero page subroutine area which is located on the address from 0000 to 003F using CAL instruction When CAL instruction is executed 6 bit immediate data is placed in low order six bits of program counter PCs to PCo and O s are placed...

Page 329: ...nto the accumulator and B Register When bit 9 is I 8 bits of referred ROM data are written into the RI and R2 port output register When both bit 8 and 9 are I ROM data are written into the accumulator and B Register and also to the RI and R2 port output register at a same time The P instruction has no effect on the program counter INSTRUCTION SET The HMCS400 series provide 99 instructions These in...

Page 330: ...ate LXI i 1 000 1 0 b i2 i io i X 1 1 Load Y from Immediate LYI i 1 0 0 0 0 1 b i2 i io i Y 1 1 Load X from A LXA 0011101000 A X 1 1 Load Y from A LYA 0011011000 A Y 1 1 Increment Y IY 0001011100 Y 1 Y NZ 1 1 Decrement Y DY 0011011 1 1 1 Y 1 Y NB 1 1 Add A to Y AYY 0001010100 Y A Y OVF 1 1 Subtract A from Y SYY 0011010100 Y A Y NB 1 1 Exchange X and SPX XSPX 0000000001 X SPX 1 1 Exchange Y and SPY...

Page 331: ... 1 Complement B COMB 0101000000 e B 1 1 Rotate Right A with Carry ROTR 0010100000 1 1 Rotate Left A with Carry ROTL 0010100001 1 1 Set Carry SEC 0011 1011 1 1 1 CA 1 1 Reset Carry REC 0011101100 O CA 1 1 Test Carry TC 0001 101111 CA 1 1 Add A to Memory AM 0000001000 M A A OVF 1 1 Add A to Memory AMD d 9J8 7 6 s 4J3 2 1 o M A A OVF 2 2 Add A to Memory with Carry AMC 0000011000 M A CA A OVF 1 1 Add ...

Page 332: ...000 1 1 n no M n 1 1 Test Memory Bit TMD n d q 1 1 00 q 1 1 n no dg ds d7 ds ds d d3 d2 d do M n 2 2 Table 29 ROM Address Instruction I MNEMONIC 2 OPERATION OPERATION CODE FUNCTION STATUS CYCL Branch on Status 1 BR b 1 1 b7b6bsb4b3b2b bo 1 1 1 Long Branch on Status 1 BRL u o 1 0 1 1 1 P3P2P1PO 1 2 2 dgda d7 dsds d da d2dl do Long Jump Unconditionally JMPL u o 1 0 1 0 1 P3P2P1PO dgdsd7dsdsd dad2d d...

Page 333: ...MI B T8R C XM8 XY BlEMI D LMADY Xi SYVI E TOL SEOI F LWI i 2 0 LBI 1 LYI 2 LXI 3 LAI 4 LBR 5 LAR 6 REDD 7 LAMR 8 AI 9 LMIIY A TDD B ALEI C LRB D LRA E SEDD F XMRA D l word 2 ycle Instruction IAMI JOR IAMcl IEORMI i 4 i 4 ILABL JIBJ j IVJ I TC i 4 L REM n 2 J TM n 2 ISMCI JANMJ IOAS ILAY p 4 ILBAI I DB ILYAI lOY ILXAI IREel ISEe i 4 i 4 i 4 i 4 m 4 I m 4 I m 4 m 4 i 4 i 4 m 4 i 4 m 4 I m 4 I m 4 m ...

Page 334: ...tput R Input Output R o f R7I R7 Output Output Output Rso f Output RSI R8 f Input Output Rs Input Output Input Output R o f Input Output R I R9 f Input Output R t Input Output R 3 Input Output RAO RA t Input Output RA1 INPUT OUTPUT Input Output Input Output Input Output Input Output Input Output Input Output Input Output Input Output Input Output Input Output Input Output on Input Output c a Outpu...

Page 335: ... HMCS404AC PACKAGE DIMENSIONS Unit mm o I I Q I ci I C I I 2 I U 0 2 DP 64S FP 64 333 ...

Page 336: ...334 ...

Page 337: ...pply Voltage Range 2 7V to 6V Minimum Instruction Execution Time 4 IJ s Two Low Power Dissipation Modes Standby Stops instruction execution while keeping clock oscillation and interrupt functions in op eration Stop Stops instruction execution and clock oscilla tion while retaining RAM data On Chip Oscillator External Connection of Crystal or Ceramic Filter externally drivable SOFTWARE FEATURES Ins...

Page 338: ... Vdiop I t RAO L ___ J R R RIO Roo R R R RIo R R R R o 0 0 0 O O 0 O O De 0 0 0 Do GNO OSC OSC mT RESET RI3 Rt2 R RIO R Ru R RIO Rn Rn R R o Ru R SO Re SI Reo SCi I oLRool Ru Sl SO Ro i R Rao J High Voltage Pins 336 OJ 0 0 Do GNO osc osc Tm RESET Ro RIO Ril R R RIO Rn 33 Rn RESgr Tm OSC OSc Vee Nl ROM PC r r I I I IIloaRotRo Roo I ID D D D D D D D D D D D D D Do _______ J L __________________ J ...

Page 339: ...ese conditions are exceeded it may cause the malfunction and affect the reliability of LSI Note 2 Note 3 Note 4 Note 5 Note 6 Note 7 Note 8 Note 9 Note 10 Note 11 Note 12 All voltages are with respect to GND Applied to standard pins Applied to high voltage pins Total allowance of input current is the total sum of input current which flow in from all I O pins to GND simultaneously Total allowance o...

Page 340: ... 0 3 0 3 V Output High VOH SCK so IOH 0 1 rnA Voltage Vee 0 5 V Output Low VOL SCK SO IOL O 4mA 0 4 V Voltage Input Output RESET SCK IIILI INTo INTI Vin 0 V to Vee 1 p A 1 Leakage Current SI SO ascI Current Vee 3 V Dissipation in lee Vee 0 6 rnA 2 6 Active Mode fasc 2 MHz Maximum Logic Operation ISBY1 Vee Vee 3 V 0 5 rnA 3 6 Current fasc 2 MHz Dissipation in Minimum Logic Operation Standby Mode IS...

Page 341: ... RESET GND voltage TEST Vee voltage D 03 R3 R9 V cc voltage 0 0 RO R2 RAe RA1 Vdisp voltage Pull down MOS current is excluded Note 5 Note 6 When fosc X MHz the Current Dissipation in Operation mode and Standby mode are estimated as follows When Divide by 8 0 8 option is selected max value fosc x MHz 1 x max value fosc 2 MHz INPUT OUTPUT CHARACTERISTICS FOR STANDARD PIN Vee 2 7V to 6V GND OV Vdisp ...

Page 342: ...isp Vee 4OV Output Low RO R2 Voltage VOL 04 015 RO R2 150kil to Vee 40V Input Output IIILI 04 015 Leakage RO R2 Vin Vee 40V to Vee Current RAO RA1 Pull Down MOS 04 015 Vdisp Vee 35V Id RO R2 125 Current RAO RA1 V in Vee Note 1 Applied to I O pins with Pull down MOS selected by mask option Note 2 Applied to I O pins without Pull down MOS PMOS Open Drain selected by mask option Note 3 PUll down MOS ...

Page 343: ... INTI 2 tCYC 3 RESET High Level Width tRSTH RESET 2 tCyc 4 Input Capacitance Cin all pins f 1 MHz 15 pF Vin 0 V RESET Fall Time tRSTf 15 ms 4 Note 1 Oscillator stabilization time is the time until the oscillator stabilizes after VCC reaches 2 7V at Power on or after RESET input level goes High by resetting to quit the stop mode by MCU reset The circuits used to measure the value are described belo...

Page 344: ...Fall Time tSCKf Serial Output Data toso Delay Time Serial Input Data Set up Time tSSI Serial Input Data Hold Time tHSI Note 1 Timing Diagram of Serial Interface SCK VCC O 5V O 85VcC OAV O 15VcC so Pin Name Test Conditions min SCK Note 2 1 SCK Note 2 0 5 SCK Note 2 0 5 SCK Note 2 SCK Note 2 SO Note 2 SI 1000 SI 500 Test Pin Name Conditions min SCK 1 SCK 0 5 SCK 0 5 SCK SCK SO Note 2 SI 1000 SI 500 ...

Page 345: ... A Vee 5 X VI V7 Ve 7 V V V vee 2 7V Ar l I 6 2 VOL V 3 IOL min vs VOL Characteristics Standard Pin 343 t E N a 1 0 0 5 o 500 Ta 20 _I 75 e fosc 2MHz V 3 Vee V 4 5 ISBY vs Vee Characteristics Crystal Ceramic Filter Oscillator Ta 20 75 e 6 I ISBY1 max ISBY2 max max 400 300 2 200 I I I I I typo I I min _ II V 100 f o 10 20 30 40 Vee Vdisp V Id Pull down MOS Current vs Vee Vdisp Characteristics 4r r ...

Page 346: ...and RA are the high voltage ports R3 to R9 are the standard ports Each pin has the mask option to select its cir cuit type R32 R33 R40 R41 and R42 are also available as INTo INTI SCK SI and SO respectively For details see 344 6 5 c E 3 x o I 2 o Ta 20 75 C V V V v V f7V l V V t 0V I l I v I lotV 2 3 4 VCC VOH V 1 VCC 6V V VCC 5V f VCC 4V VCC 2 7V 5 IOH min vs VCC VOH Characteristics RO R2 Pins INP...

Page 347: ...In addition to these areas interrupt control bits and special registers are also mapped on the RAM memory space RAM memory map is illustrated in Fig 2 and described in the following paragraph o 31 32 RAM mapped Registers Memory Registers MR 000 01F 020 0 1 Interrupt Control Bits 2 3 4 Port Mode Reg PMR W 47 48 02F 000 001 002 003 004 005 006 007 008 009 OOA OOB OOC 223 224 959 960 1023 Data 192Dig...

Page 348: ...ssified into 3 types Write only Read only and Read Write as shown in Fig 2 These registers cannot be accessed by RAM bit manipulation instruction Memory Registers Stack Area MR O 020 960 level 16 S 3CO MR l 021 level 15 MR 2 022 level 14 MR 3 023 level 13 MR 4 024 level 12 MR 5 025 level 11 MR 6 026 level 10 MR 7 027 level 9 MR 8 028 level 8 Data Area 020 to ODF 16 digits of 020 to 02F are called ...

Page 349: ... is initialized to locate 3FF on the RAM address and is decremented by 4 as data pushed into the stack and incremented by 4 as data restored back from the stack INTERRUPT The MCU can be interrupted by five different sources the external signals INTo INTd timer counter TIMER A TIMER B and serial interface SERIAL In each sources the Interrupt Request Flag Interrupt Mask and interrupt vector address ...

Page 350: ... Vector Addresses and Interrupt Priority Reset Interrupt Priority Vector addresses RESET 0000 INTo 1 0002 INT 2 0004 TIMER A 3 0006 TIMER B 4 0008 SERIAL 5 OOOC Table 2 Conditions of Interrupt Service Interrupt source INTo INT TIMER A TlMER B control bits I E 1 1 1 1 IFO IMO 1 0 0 0 IF1 IM1 1 0 0 IFTA IMTA 1 0 IFTB IMTB 1 IFS IMS 348 SERIAL 1 0 0 0 0 1 Don t care ...

Page 351: ...rnal Interrupt Mask 1M has to be set so that the interrupt request by INTI will not be accepted External Interrupt Request Flag I FO 000 2 IF1 001 0 The External Interrupt Request Flags lFO IFl are set at the falling edges of INT0 INT1 inputs respectively External Interrupt Mask lMO 000 3 IM1 001 1 The External Interrupt Mask is used to mask the external interrupt requests Table 4 External Interru...

Page 352: ...HMCS404CL No Yes Yes No PC 0002 PC 0004 PC 0006 PC 0008 PC OOOC Fig 8 Interrupt Servicing Flowchart 350 I E O Stack PC Stack CA Stack ST No SERIAL Interrupt ...

Page 353: ...erating state of serial interface The Write Signal to the Serial Mode Register stops the transfer clock applied to the Serial Data Register and the Octal Counter And it also reset the Octal Counter to 0 simul taneously When the Serial Interface is in the Transfer State the Write Signal to the Serial Mode Register causes to quit the data transfer and to set the SERIAL Interrupt Request Flag Content...

Page 354: ...ight transfer clock signals or transmit receive discontinued operation by resetting the Octal Counter SERIAL Interrupt Mask lMS 003 1 The SERIAL Interrupt Mask masks the interrupt request Table 8 SERIAL Interrupt Request Flag SERIAL Interrupt Request Flag Interrupt Request o No Yes 352 Table 9 SERIAL Interrupt Mask SERIAL Interrupt Mask Interrupt Request o Enable Disable mask Selection of the Oper...

Page 355: ...n Then reset the SERIAL Interrupt Request Flag and make STS waiting state by writing to the Serial Mode Register SERIAL Inter rupt Request Flag is set again in this procedure and it shows that the transfer clock was invalid and that the transmit receive data were also invalid Table 10 Serial Interface Operation Mode SMR PMR Bit 3 Bit 1 Bit 0 Serial Interface Operating Mode 1 0 0 Clock Continuous O...

Page 356: ...al When the next clock signal is applied to TIMER 8 after TIMER B is set to FF TIMER B will be initi alized again and generate overflow output In this case if the auto reload function is selec ted TIMER B is initialized accord ing to the value of the Timer Load Register Else if the auto reload function is not selected TIMER B goes to 00 TIMER B Interrupt Request Flag IFTB 002 0 will be set at this...

Page 357: ...count value of low order digit is latched at the time when the high order digit is read TIMER A Interrupt Request Flag lFTA 001 2 The TIMER A Interrupt Request Flag is set by the overflow output of TIMER A TIME R A Interrupt Mask lMTA 001 3 TIMER A Interrupt Mask prevents an interrupt request generated by TIMER A Interrupt Request Flag Table 13 TIMER A Interrupt Request Flag TIMER A Interrupt Requ...

Page 358: ... least one high voltage pin is selected as With pull down MOS option When any Input Output common pin is used as input pin it is necessary to select the mask option and output data as shown in Table 18 Output Circuit Operation of Standard Pins with With pu up MOS Option Fig 15 shows the circuit used in the standard pins with with pull up MOS option By execution of the output instruction the write ...

Page 359: ... en output output ut data data Vee Input H pins input HLT input R90 R93 data data Without pull down MOS With pull down MOS E Applied pins PMOS open drain 0 Vee HLT HLT I O 0 output o output 0 4 015 data data common R10 R I3 pins Vee R10 R13 HIT input Vdisp HLT input data data Vee c Vee 0 kO HLT Q 03r O HLT en output Output output data 0 data pins Vee Roo R03 r 2 J Vdisp Input input P RAO data data...

Page 360: ...NT o e i n p u t o e i n p u t SI data data HLT HLT Note In the stop mode HLT signal is 0 HLT signal is 1 and I O pins are in high impedance state Table 18 Data Input from Input Output Common Pins I O pin circuit type Possibi lity Available pin condition of Input for input CMOS No Standard Without pull up pins MOS NMOS open drain Yes 1 With pull up MOS Yes 1 Without pull down High MOS Yes 0 voltag...

Page 361: ...C 0000 Execute program from the top of ROM address Status ST 1 Enable to branch with conditional branch instructions Stack pointer SP 3FF Stack level is O A Without pull 1 Enable to input upMOS Standard pin B With pull up 1 Enable to input MOS C CMOS 1 I O pin 0 Without pull output register 0 Enable to input High voltage down MOS pin E With pull a Enable to input down MOS Interrupt Enable Flag I E...

Page 362: ...uration Oscillator D OSC Open OSC f OSC It 4 OSC2 C2 _______ GND CI t rysta L OSCI Sf ff J r VlY OSC2 C2 _______ GND GT cut parallel resonance crystal OS C2 Co Remarks Ceramic filter CSA2 000MK Murata Rf lMn 2 C 30pF 20 C 30pF 20 Wiring between these pins and elements should be as short as possible and never cross the other wirings Refer to Fig 17 Rf 2Mn 2 C 10 22pF 20 C 10 22pF 20 Crystal GT cut ...

Page 363: ...is is the additional current to the current dissipation in Standby Mode lSBY1 ISBY2 Fig 18 MCU Operation Mode Transition counter and serial interface continue working On the other hand the CPU stops since the clock related to the instruction execution stops Registers RAM and Input Output pins retain the state they had just before going into the Standby mode The Standby mode is canceled by the MCU ...

Page 364: ...ks Stop Restart Processor Clocks A Reset MCU Fig 19 MCU Operating Flowchart _ rm IIIII IIII1 III I III IIIII ___4I _ Jr I n n 1 t I tres I Oscillator RESET STOP instruction execution more than stabilization time tRcl Fig 20 Timing Chart of Recovering from Stop Mode 362 ...

Page 365: ...t Addressing The direct addressing instruction consists of two words and the second word 10 bits following Op code the first word is used as the RAM address Memory Register Addressing The Memory Register Addressing can access 16 digits Memory Register MR from 020 to 02F by using the LAMR and XMRA instruction W Register X Register Y Register r __ a Register Indirect Addressing Instruction st Word I...

Page 366: ...Instruction 1st Word instruction on the boundary between pages is in the next page Refer to Fig 24 Zero Page Addressing Mode The program branches to the zero page subroutine area which is located on the address from 0000 to 003F using CAL instruction When CAL instruction is executed 6 bit immediate data is placed in low order six bits of program counter PCs to PCo and O s are placed in high order ...

Page 367: ...gister When bit 9 is 1 8 bits of referred ROM data are written into the Rl and R2 port output register When both bit 8 and 9 are 1 ROM data are written into the accumulator and B Register and also to the Rl and R2 port output register at a same time The P instruction has no effect on the program counter INSTRUCTION SET The HMCS400 series provide 99 instructions These instruc tions are classified i...

Page 368: ...i 1 0 0 0 1 0 i3 i2 i io i X 1 1 Load Y from Immediate LYI i 1 0 0 0 0 1 i3 i2 i io i Y 1 1 Load X from A LXA 0011101000 A X 1 1 Load Y from A LYA 0011011000 A Y 1 1 Increment Y IY 0001011100 Y 1 Y NZ 1 1 Decrement Y DY 001 101 1 1 1 1 Y 1 Y NB 1 1 Add A to Y AYY 0001010100 Y A Y OVF 1 1 Subtract A from Y SYY 0011010100 Y A Y NB 1 1 Exchange X and SPX XSPX 0000000001 X SPX 1 1 Exchange Y and SPY X...

Page 369: ...B 0101000000 B B 1 1 Rotate Right A with Carry ROTR 0010100000 1 1 Rotate left A with Carry ROTl 0010100001 1 1 Set Carry SEC 0011 101 1 1 1 l CA 1 1 Reset Carry REC 0011 101100 O CA 1 1 Test Carry TC 0001 101111 CA 1 1 Add A to Memory AM 0000001000 M A A OVF 1 1 Add A to Memory AMD d gd8 6 s 4J 3 2 1 o M A A OVF 2 2 Add A to Memory with Carry AMC 0000011000 M A CA A OVF 1 1 Add A to Memory with C...

Page 370: ...ry Bit TM n 00 1 000 1 1 n no M n 1 1 Test Memory Bit TMD n d s S I 6 5 4 3 2 M n 2 2 Table 29 ROM Address Instruction IMNEMONIC WZ OPERATION OPERATION CODE FUNCTION STATUS CYCL Branch on Status 1 BR b 1 1 b7babsb4bJb2b bo 1 1 1 Long Branch on Status 1 BRL u B 8 1 s s 4 1 2 2 Long Jump Unconditionally JMPL u o 1 0 1 q 1 3 2P IPO ds dB dl dB ds d4 d3 d2 d do 2 2 Subroutine Jump on Status 1 CAL a o ...

Page 371: ...B TBR C XMB XY 8lEMj o LMADYIXi SYYI E TO SED F LWI i 2 0 LBI 1 LYI 2 LXI 3 LAI 4 LBR 5 LAR 6 REDO 7 LAMR S AI 9 LMIIY A TOO B ALEI C LRB 0 LRA E SEOO F XMRA D 1 word 2 cyc e Instruction IAMI lORMJ lAMS lEORM l 4 4 ILABj liB I I IIY I lA9 I TC 4 l REM n 2 J TM n 2 JSMS lANMj jOASL ILAY p 4 ILBAJ IDB I LYAI j DY ILXAI jRECj j SEC 4 4 4 4 m 4 I m 4 I m 4 m 4 4 4 m 4 4 m 4 I m 4 I m 4 m 4 D 1 word 3 ...

Page 372: ...Input Output L I Input Output mr tm E Input Output r 1 Input Output I Y I Input Output I I Input Output 1 Input Output 2 f Input Output S b 2 Input Output I Input Output 1 3 t Input Output c Input Output a Output tl Output en Output I Output v 1 Output I Output k I C Output i Output I Output I Output Output b It Output I k Input F F t Input r k Input 1 t Input k L tt 5 Input I rIH I toQ Input Plea...

Page 373: ... HMcS 4CL PACKAGE DIMENSIONS Unit mm o I I CD I I q I I I u o__ 1 _2 DP 64S FP 64 371 ...

Page 374: ......

Page 375: ...tSingl Chip Microc omputers A re lisecjUS editioni now in production scheduledforpublicoiionin May 1985 I Ify6uwQuidlike to reserve GOpyof theUS editi orl pl aSe complete thepostdge pqi d replycard belowond mail today I Please Print Nome Title Address City State ZIP HU7 6 Please Print Nar ne Moil Stop Adc lress City ZIP HU76 ...

Page 376: ...lN9 41 Glei1View Il 09 5 poSTAGE V lILl BEPAtDBY ADDRE SSEE LITERATUREJ iFIL1M ENTCiN ER Hita bi Arnerica lfd P o Box 11 l7 GleF1vieWi IL 60Q2S _ 1_ _ N o p o s T A 8 NE ESSARY IF MArLEo l i INTHE UNITEDSTATES _tl 1 f i I ...

Page 377: ......

Page 378: ... HITACHI A World Leader in Technology Hitachi America Ltd Semiconductor and Ie Sales and Service Division 2210 O Toole Avenue San Jose CA 95131 1 408 942 1500 FEBRUARY 1985 Printed in U S A ...

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