Hioki SS7081-50, Instruction Manual, Page: 38 / 71

35

Standard Event Status Enable Register (SESER)
Setting any bit of the Standard Event Status Enable Register to “1” enables access to the corresponding bit of
the Standard Event Status Register.
Standard Event Status Register (SESR) and Standard Event Status Enable Register (SESER)
Status Byte Register (STB)
bit6 bit5 bit4
MSS ESB MAV
Standard Event Status Register (SESR)
↑
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
PON URQ CME EXE DDE QYE RQC OPC
↓ ↓ ↓ ↓ ↓ ↓ ↓ ↓
Logical sum ← & & & & & & & &
↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
PON URQ CME EXE DDE QYE RQC OPC
Standard Event Status Enable Register (SESER)

Instrument-specific Event Status Register
The instrument provides one Event Status Register for controlling events. The Event Status Register is a 16-bit
register.
When any bit in one of these Event Status Registers enabled by its corresponding Enable Register is set to
“1”, the following happens:
•
For Status Query Register: Bit 3 (ESB0) of the Status Byte Register is set to “1”.
The contents of Event Status Register 0 are cleared in the following situations.
• When a
*
CLS
or *
RST
command is executed
•
When an Event Status Register query is executed
(
:STATus: QUEStionable: EVENt?
)
Status Query Register
Bit 15 - Unused
Bit 14 - Unused
Bit 13 - Unused
Bit 12 - Unused
Bit 11 - Unused
Bit 10 OVER_RANGE Overrange (100 μA ran ge)
Bit 9 MEAS_ERR1 Measurement error
Bit 8 MEAS_ERR2
Measurement error
Bit 7 MEAS_ERR3
Measurement error
Bit 6 MEAS_ERR4
Measurement error
Bit 5 VOLT_ERR Output voltage error
Bit 4 CRR_ERR Overcurrent error
Bit 3 FRQ_ERR Power supply frequency error
Bit 2 TEMP_ERR Temperature error
Bit 1 FAN_ERR Fan stop
Bit 0 HW_ERR Hardware error
HIOKI SS7081C961-00