hilscher netX 50 Migration Manual Download Page 17

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Package, Pinning, Pad Cells

17/56

2012-2013

Pin

Pad

Out

Signal

Group

Description

A09

IOU9

DPM_D24

DPM

Dual-Port Memory Data 24

A08

IOU9

DPM_D25

DPM

Dual-Port Memory Data 25

A06

IOU9

DPM_D26

DPM

Dual-Port Memory Data 26

B07

IOU9

DPM_D27

DPM

Dual-Port Memory Data 27

A02

IOU9

DPM_D28

DPM

Dual-Port Memory Data 28

A04

IOU9

DPM_D29

DPM

Dual-Port Memory Data 29

D03

IOU9

DPM_D30

DPM

Dual-Port Memory Data 30

H17

IOU9

DPM_D31

DPM

Dual-Port Memory Data 31

D16 IOU9

IO DPM_DIRQn

DPM

Dual-Port Memory Data Interrupt

B15

IOU9

DPM_RDn

DPM

Dual-Port Memory Read

C15

IOU9

DPM_WAITn

DPM

Dual-Port Memory Wait

C08

IOD9

DPM_SIRQn

DPM

Dual-Port Memory Sync Interrupt

B16

IOU9

DPM_WRHn/BE3n

DPM

Dual-Port Memory Byte Enable 3

B14

IOU9

DPM_WRn/WRLn

DPM

Dual-Port Memory Write

E03 IDS

BSCAN_TRST

GENERAL Reset Boundary Scan Controller

V07

PLL power supply

OSC_VDDC

GENERAL

Oscillator Power Supply Core 1.5V

U07

PLL power supply

OSC_VSS

GENERAL

Oscillator Power Supply Ground

U08

Ocsillator pad

OSC_XTI

GENERAL

25 MHz Crystal Input

V08

Ocsillator pad

OSC_XTO

GENERAL

25 MHz Crystal Output

C01

IUS

PORn

GENERAL

Power on Reset

F01

IOD6

RDYn

GENERAL

RDY-LED / Boot start option

D01 OZ6

RSTOUTn

GENERAL Reset

Output

F02

IOD6

RUNn

GENERAL

RUN-LED / Boot start option

G02

IDS

TACT_TRST

GENERAL

Reset Test Controller

B10

TEST

GENERAL

Activate Test Mode (left open)

F03

Internal Test pin, tmc1

TMC1

GENERAL

Test Mode 1 (left open)

G03

Internal Test pin, tmc2

TMC2

GENERAL

Test Mode 2 (left open)

H18

IOZUS9 (5K pull up)

I2C_SCL

I2C

I2C Serial Clock Line

H16

IOZUS9 (5K pull up)

I2C_SDA

I2C

I2C Serial Data Line

H01 IUS

JT_TCLK

JTAG

Test

Clock

J03

IUS

JT_TDI

JTAG

JTAG Test Data Input

M03

OZ6

JT_TDO

JTAG

JTAG Test Data Output

K03

IUS

JT_TMS

JTAG

JTAG Test Mode Select

H03 IDS

JT_TRSTn

JTAG

Test

Reset

T13 -

Reserved

T10

1,5V Core Power

VDDC

POWER

Power Supply Core 1.5V

T12

1,5V Core Power

VDDC

POWER

Power Supply Core 1.5V

T11

3,3V IO Power

VDDIO

POWER

Power Supply IO 3.3V

U14

3,3V IO Power

VDDIO

POWER

Power Supply IO 3.3V

U10 -

Reserved

V10 -

Reserved

U12 -

Reserved

V12 -

Reserved

U11 -

Reserved

V11 -

Reserved

U13 -

I-

Reserved

Summary of Contents for netX 50

Page 1: ...Migration Guide netX 50 to netX 51 52 Hilscher Gesellschaft f r Systemautomation mbH www hilscher com DOC120109MG05EN Revision 5 English 2013 08 Released Public...

Page 2: ...22 3 3 netX 51 24 3 3 1 Differences in Pinning and Pad Cells 24 3 4 MMIO Signals 32 4 General Changing 34 4 1 CPUs 34 4 1 1 Core CPU 34 4 1 2 Additional CPU 34 4 2 Memory 35 4 2 1 Layout 35 4 3 Perip...

Page 3: ...This can be placed on already existing netX 50 PCBs without modifications It also supports IO Link version 1 1 and includes much more RAM and an additional 32 Bit Risc Controller CAN controller and a...

Page 4: ...Price netX 52 Network Controller Hilscher 10 00 W25Q32VSSIG QSPI Flash Windbond 0 70 MAX811SEUS T Reset Generator Maxim 0 20 EN5312Q DC DC Converter 3 3 V 1 5 V Enpirion 1 20 25 MHz Crystal div 0 30...

Page 5: ...ace added 4 2013 03 26 HH 2 1 1 2 1 2 Correction 1x I2C for netX 50 4 6 Section Host Interface Modes updated Table 22 revised 5 2013 08 26 HH 4 5 Correction 10 Kbyte to 10 kOhm Table 2 List of Revisio...

Page 6: ...T_TMS JTAG Test Mode Select JT_TCLK JTAG Test Clock JT_TDI JTAG Test Data Input JT_TDO JTAG Test Data Output SPI SPI0_CLK SPI 0 Clock SPI0_CS0n SPI 0 Chip Select 0 SPI0_CS1n SPI 0 Chip Select 1 SPI0_M...

Page 7: ...MAC Rx Clock MII_RXD0 3 Ethernet MAC Rx Data 0 3 MII_RXDV Ethernet MAC Rx Data Valid MII_RXER Ethernet MAC Rx Error MII_TXCLK Ethernet MAC Tx Clock MII_TXD0 3 Ethernet MAC Tx Data 0 3 MII_TXEN Ethern...

Page 8: ...Transmit Output positive FO0_RD Fiberoptic Ethernet channel 0 Receive Data FO0_TD Fiberoptic Ethernet channel 0 Transmit Data FO0_EN Fiberoptic Ethernet channel 0 Enable FO0_SD Fiberoptic Ethernet cha...

Page 9: ...ynchronization ETM_DRQ ETM Debug request ETM_DACK ETM Debug acknowledge ETM_PSTAT0 ETM Pipe status 0 ETM_PSTAT1 ETM Pipe status 1 ETM_PSTAT2 ETM Pipe status 2 ETM_TPKT00 ETM Trace packet 0 ETM_TPKT01...

Page 10: ...documentation were created for the use of the products by qualified experts however errors cannot be ruled out For this reason no guarantee can be made and neither juristic responsibility for erroneo...

Page 11: ...n weapon systems for the design construction maintenance or operation of nuclear facilities in air traffic control systems air traffic or air traffic communication systems in life support systems in s...

Page 12: ...tion Guide DOC120109MG05EN Revision 5 English 2013 08 Released Public 2012 2013 2 Comparison netX 50 with netX 51 52 2 1 Overview 2 1 1 Block Diagrams Block Diagram netX 50 Figure 3 Block Diagram of n...

Page 13: ...Ethernet MAC Very often these communication lines were the reason to use the more expensive three channel controller netX 100 To increase the over all performance of the netX 51 52 and to allow real...

Page 14: ...ce RTE systems as PROFINET IRT with Dynamic Frame Packing or Fast Track Switching xPIC as additional 100 MHz RISC CPU for time critical tasks Separate CAN Controller in addition to two communication c...

Page 15: ...s the netX 50 has It is designed to replace the netX 50 without changing the PCB drop in replacement The netX 52 comes in a smaller 244 pin PBGA package with 0 8mm grid 3 1 netX 52 3 1 1 netX 52 Packa...

Page 16: ...M Dual Port Memory Address 9 A16 IOU9 IO DPM_BHEn BE1n DPM Dual Port Memory Byte Enable 1 A15 IOU9 IO DPM_CSn DPM Dual Port Memory Chip Select A01 IOU9 IO DPM_D0 DPM Dual Port Memory Data 0 C02 IOU9 I...

Page 17: ...I OSC_VSS GENERAL Oscillator Power Supply Ground U08 Ocsillator pad I OSC_XTI GENERAL 25 MHz Crystal Input V08 Ocsillator pad O OSC_XTO GENERAL 25 MHz Crystal Output C01 IUS I PORn GENERAL Power on Re...

Page 18: ...atrix IO 19 T05 IODS6 IO MMIO20 MMIO Multiplex Matrix IO 20 V03 IODS6 IO MMIO21 MMIO Multiplex Matrix IO 21 T06 IODS6 IO MMIO22 MMIO Multiplex Matrix IO 22 U05 IODS6 IO MMIO23 MMIO Multiplex Matrix IO...

Page 19: ...ower VDDC POWER Power Supply Core 1 5V K13 1 5V Core Power VDDC POWER Power Supply Core 1 5V L06 1 5V Core Power VDDC POWER Power Supply Core 1 5V L13 1 5V Core Power VDDC POWER Power Supply Core 1 5V...

Page 20: ...H11 Ground VSS POWER Power Supply Ground H12 Ground VSS POWER Power Supply Ground J01 Ground VSS POWER Power Supply Ground J07 Ground VSS POWER Power Supply Ground J08 Ground VSS POWER Power Supply Gr...

Page 21: ...ound VSS POWER Power Supply Ground V16 IOD6 IO SPI0_CLK QSPI_CLK SPI SPI Clock QSPI Clock U15 IOU6 IO SPI0_CS0n QSPI_CSn SPI SPI Chip Select 0 QSPI Chip Select T15 IOD6 IO SPI0_MISO QSPI_SIO1 SPI SPI...

Page 22: ...OU9 IO SD_D14 SD SDRAM Data 14 H17 IOU9 IO SD_D15 SD SDRAM Data 15 A03 IOU9 IO SD_A0 SD SDRAM Address 0 B06 IOU9 IO SD_A1 SD SDRAM Address 1 C06 IOU9 IO SD_A2 SD SDRAM Address 2 C07 IOU9 IO SD_A3 SD S...

Page 23: ...R MII MII Receive Error C11 IOU9 IO MII_TXD0 MII MII Transmit Data 0 A11 IOU9 IO MII_TXD1 MII MII Transmit Data 1 C10 IOU9 IO MII_TXD2 MII MII Transmit Data 2 A09 IOU9 IO MII_TXD3 MII MII Transmit Dat...

Page 24: ...w also be configured as additional MMIO Input 3 3 1 2 Test Ball Pos Signal Pad Type netX netX netX 50 51 52 50 51 52 50 51 52 G5 E3 TEST BSCAN_TRST ID IDS A12 B10 MEM_IF_OM TEST IUS ID Table 10 Differ...

Page 25: ...nning and Pad Cells Memory Interface All Memory Signals without the SDRAM Clock and the Data lines can be used as inputs with a default value of zero because internal pull down resistors This allows r...

Page 26: ..._A19 IOD6 QSPI_SIO3 Table 12 Differences in Pinning and Pad Cells SPI If a Quad SPI flash is used for fast start up at netX 50 the already published workaround via the communication controller is work...

Page 27: ...ces in Pinning and Pad Cells USB In USB device mode the netX 50 requires an external resistor to connect USB hosts This resistor is activated either using a MMIO in software or via jumper during boots...

Page 28: ..._A10 IOU9 MII_TXD2 A17 A14 DPM_A11 IOU9 MII_TXD3 B15 B13 DPM_A12 IOU9 MII_TXEN A16 A13 DPM_A13 IOU9 MII_TXCLK B14 A12 DPM_A14 IOU9 A15 B11 DPM_A15 IOU9 E14 A17 VDDC DPM_A16 PWR IOU9 D14 A18 VSS DPM_A1...

Page 29: ..._WRn WRLn IOU9 B11 C8 TCLK DPM_SIRQn IOU9 Table 14 Differences in Pinning and Pad Cells Host Interface Note Only the name of these signals changed to be consistent with the configuration as active low...

Page 30: ...6 MII_RXD2 R1 R2 MMIO12 IODS6 MII_RXD3 U1 U2 MMIO13 IODS6 MII_RXDV T1 T2 MMIO14 IODS6 MII_RXER V1 R3 MMIO15 IODS6 MII_TXCLK U2 T4 MMIO16 IODS6 MII_TXD0 V2 V1 MMIO17 IODS6 ETM_TCLK MII_TXD1 V3 U4 MMIO1...

Page 31: ...he MMIO 48 is shared with CLKOUT pin Note In addition the MII interface of the third MAC controller can be multiplexed with the MII signals The MMIO can not be changed Symbol Description I Input O Out...

Page 32: ...ways driven output INT_PHY0 X X PHY1_LED0 Always driven output INT_PHY1 X X PHY1_LED1 Always driven output INT_PHY1 X X PHY1_LED2 Always driven output INT_PHY1 X X PHY1_LED3 Always driven output INT_P...

Page 33: ...Tristate able output UART 0 2 X X USB_ID_DIG Input USB X USB_ID_PULLUP_CTRL Non tristate able output USB X USB_RPD_ENA Non tristate able output USB X USB_RPU_ENA Non tristate able output USB X CCD_DAT...

Page 34: ...M if not used by XC channels or external host External memories via extension bus SDRAM interface Internal SRAM External memories via extension bus SDRAM interface Serial flash via QSPI Execution in P...

Page 35: ...MByte ARM xPIC 0x64000000 HIF_EXTSRAM2 64 MByte ARM xPIC 0x68000000 HIF_EXTSRAM3 64 MByte ARM xPIC 0x6c000000 SDRAM 256 MByte ARM 0x80000000 256 MByte ARM xPIC 0x80000000 EXTSRAM0 64 MByte ARM 0xc000...

Page 36: ...bit timers systime read and compare IRQ support Systime IEEE1588 No differences New netX 51 includes 2nd independent systime unit systime_uc FMMU SyncManager BufferManager No differences 8 FMMUs 8 Syn...

Page 37: ...LEXED INTEL_16BIT_SRAM INTEL_16BIT_BYTE_WRITE INTEL_16BIT_MUL_NO_BES INTEL_32BIT_SRAM MOTOROLA_8BIT_MULTIPLEXED MOTOROLA_16BIT MOTOROLA_16BIT_68000 Following netX 50 compatible DPM Modes INTEL_8BIT_SR...

Page 38: ...52 is that full internal SRAM can be reached by TCM channels Furthermore ARM can run accesses in parallel now Access can be performed on both TCM channels e g instruction fetch and data store and even...

Page 39: ...to the pins to fit in a smaller housing and reduce the component costs For netX 51 and netX 52 the firmware must be updated in any case The netX 51 provides all signals from the die The pinning is id...

Page 40: ...SDRAM on Host Interface with 16 bit data bus and up to 4MByte address range 0 open 0 open 1 pull up SRAM on Host Interface with 16 bit data bus and 22 address lines on chip select 0 1 2 and 3 0 open...

Page 41: ...bd Power consumption with PHYs enabled 1 3 W tbd tbd Table 23 Operating Conditions 4 7 2 Effects to existing Software Due the netX 51 52 is not software compatible to the netX 50 different memory and...

Page 42: ...inverted when read Yes 5 I2C Signal timing can cause problems with some components Yes 6 Reset Control Register Register not protected by netX locking mechanism Yes 8 SPI Master Transmit FIFO may loo...

Page 43: ...active Boot Loader Due a bug in the Boot Loader the signals for controlling the SYS LED are inverted This happens only if there is no firmware on the netX 51 board or during the boot phase till the fi...

Page 44: ...l Flash memory to the Memory Interface when using SDRAM memory Operating one or more parallel flash memories given that at the same time no SDRAM memory is connected is possible at the Memory Interfac...

Page 45: ...mples 45 56 netX 50 to netX 51 52 Migration Guide DOC120109MG05EN Revision 5 English 2013 08 Released Public 2012 2013 6 Design Examples 6 1 Design Example netX 51 Figure 6 Design Example netX 51 COM...

Page 46: ...Design Examples 46 56 netX 50 to netX 51 52 Migration Guide DOC120109MG05EN Revision 5 English 2013 08 Released Public 2012 2013 Figure 7 Design Example netX 51 Core Memory...

Page 47: ...Design Examples 47 56 netX 50 to netX 51 52 Migration Guide DOC120109MG05EN Revision 5 English 2013 08 Released Public 2012 2013 Figure 8 Design Example netX 51 Ethernet Diagport...

Page 48: ...Design Examples 48 56 netX 50 to netX 51 52 Migration Guide DOC120109MG05EN Revision 5 English 2013 08 Released Public 2012 2013 Figure 9 Design Example netX 51 2 Port Ethernet...

Page 49: ...Design Examples 49 56 netX 50 to netX 51 52 Migration Guide DOC120109MG05EN Revision 5 English 2013 08 Released Public 2012 2013 Figure 10 Design Example netX 51 Power Supply...

Page 50: ...Design Examples 50 56 netX 50 to netX 51 52 Migration Guide DOC120109MG05EN Revision 5 English 2013 08 Released Public 2012 2013 6 2 Design Example netX 52 Figure 11 Design Example netX 52 Top View...

Page 51: ...Design Examples 51 56 netX 50 to netX 51 52 Migration Guide DOC120109MG05EN Revision 5 English 2013 08 Released Public 2012 2013 Figure 12 Design Example netX 52 Host Interface...

Page 52: ...Design Examples 52 56 netX 50 to netX 51 52 Migration Guide DOC120109MG05EN Revision 5 English 2013 08 Released Public 2012 2013 Figure 13 Design Example netX 52 CPU Core...

Page 53: ...Design Examples 53 56 netX 50 to netX 51 52 Migration Guide DOC120109MG05EN Revision 5 English 2013 08 Released Public 2012 2013 Figure 14 Design Example netX 52 Ethernet Interface...

Page 54: ...Design Examples 54 56 netX 50 to netX 51 52 Migration Guide DOC120109MG05EN Revision 5 English 2013 08 Released Public 2012 2013 Figure 15 Design Example netX 52 Power Supply...

Page 55: ...Pad Type Explanation 31 Table 17 Multiplex Matrix Signals 33 Table 18 Core CPU Comparison 34 Table 19 Memory Layout 35 Table 20 Peripheral Comparison 37 Table 21 Memory Access Performance Results 38...

Page 56: ...t Phone 33 0 4 72 37 98 40 E Mail fr support hilscher com India Hilscher India Pvt Ltd New Delhi 110 065 Phone 91 11 26915430 E Mail info hilscher in Italy Hilscher Italia S r l 20090 Vimodrone MI Pho...

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