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18
INPUT
OUTPUT
MPUGPIO1
MPUGPIO0
MPUCS0N
*CS1N
MPUGPIO2
MPUGPIO3
0
0
0
1
1
1
0
1
1
0
1
1
1
0
1
1
0
1
1
1
1
1
1
0
HAIER ATSC EX62 V2.0
Title
HDA008A_2.0
Size
B
D oc ument Number
SVP-EX62_1
Rev
A
D ate:
Tuesday , February 28, 2006
Sheet
6
of
24
D PIO0
5
D
PIO1
6
5
VO_R[
0..7]
5
4
6
3
4
5
3
6
D PIO1
6
VO_G1
D
PIO1
VO_R2
7
2
VO_G7
2
7
VO_R7
D PIO3
7
VO_G3
D
PIO1
VO_R1
8
1
VO_G6
1
8
VO_R5
D PIO2
8
VO_G2
D
PIO2
VO_R7
RN72 33
S
S
RN7 33x4
VO_G2
RN8 33x4
VO_R2
D PIO7
5
D
PIO2
2
5
5
6
4
3
D PIO20
5
D PIO19
6
D PIO5
6
VO_G5
D
PIO2
VO_R5
7
2
VO_G3
D PIO22
7
VO_R4
D PIO6
7
VO_G6
D
PIO1
VO_R3
8
1
VO_G5
D PIO21
8
VO_R3
D PIO4
8
VO_G4
D PIO20
8
VO_R4
RN45 33
VO_B[0..7
]
18
RN9
33x4
VO_B6
VO_B[0..7]
18
R
D1
8
D QM[0..3]
D QS[0..3]
8
RAS#
8
8
MA[0..11]
C AS#
8
8
MD [0..31]
W E#
8
MC LK0
8
MC LK0#
8
C LKE
8
BA0
8
BA1
8
D IN[0..23]
U9A
5,16
SD A_EX
R95
68
D IN0
Y5
SC L_EX
R96
68
SD A_MST
5,9,11,16,18,20,21
D IN1
Y6
D P
SC L_MST
5,9,11,16,18,20,21
D IN2
W 6
D
PIN1
B 16
C 77
C 78
D IN3
V6
D PIN2
C S0#
C S0#
68pF
D IN4
U6
D PIN3
C S1#
C S1#
8
D IN5
U7
D IN6
V7
D PIN4
D PIN5
MVREF
A 14
MVREF
8
5V_SB
D IN7
W 7
D
PIN6
U2
R98
4.7K
D IN8
W 3
D PIN7
TESTMODE
U3
VD 3_3
VD 3_3
D IN9
Y3
D IN10
Y4
D PIN8
D PIN9
R
V5SF
V
1
RESET
11,20,21
99
0
D IN11
W 4
D
PIN10
V2
SD A_EX
C 79
D IN12
V4
D PIN11
SDA
U4
SC L_EX
R100
R101
D IN13
U5
D IN14
V5
D IN16
Y7
D PIN12
D PIN13
D PIN15
SVP-EX62 [BGA320]
SCL
V3
PW M_EX
R102 0
E2
0.1uF
MPU has Multiplex
Data/Address
MPUGPIO4
10K
I2C Address:7E/7F
MPUC S0N
10K_D NS
D IN15
W 5
D PIN14
D PIN16
PW M
ADD R7
D IN17
Y8
D IN18
W 8
D
PIN17
ADD R6
E1
D IN20
D PIN19
(1 of 2)
ADD R4
MPU has Separared
D IN19
V8
D PIN18
U8
ADD R5
D2
D3
R103
I2C Address:7C/7D
R104
D IN21
U9
D IN22
V9
D PIN20
D PIN21
ADD R3
D4
ADD R2
C4
Address/data
1K_D NS
1K
D IN23
W 9
D
PIN22
D PIN23
Y10
ADD R1
C3
ADD R0
C2
RN60
1
8
10x4
8051_D7
8051_D [0..7] 11
5,10,17
5,10,17
HS_EX
VS_EX
W 10
Y9
D PIN_H
D PIN_V
AD7
C1
AD6
B1
2
7
8051_D6
3
6
8051_D5
5,10
C LK_EX
D PIN_C LK
AD5
10
D E_EX
V10
D PIN_DE
AD4
A1
4
5
8051_D4
10
FLD _EX
U10
D PIN_FLD
A2
AD3
RN61
1
8
10x4
8051_D3
VD 3_3
B2
AD2
B3
AD1
A3
2
7
8051_D2
3
6
8051_D1
4
5
8051_D0
MPUGPIO1
MPUGPIO0
R27
0
R105 0 D NS
8051_PS
11
AD0
RD#
W R#
ALE
E3
R106
0
E4
R107
0
F1
R108
0
8051_RD
11
8051_W R
11
8051_ALE
11
R109
8051_PS=1: Select SVP-EX
(HIDTV)
1K
8051_PS=0: Do Not Select SVP-EX
18 FLD OUT_EX
18 D EOUT_EX
18 C LKOUT_EX
18 VSOUT_EX
18 HSOUT_EX
SVP-EX_BGA320
MPUC S0N
R110
100
MPUGPIO4
R111
0
R112
0
MPUGPIO1
MPUGPIO0
LX_INT2
5,11
AGND
RN70 33x4_D NS
VO_G0
VO_G[0..7]
18
RN71 33x4_D NS
VO_R0
RN5 33x4
VO_G0
VO_G1
VO_G[0..7]
18
RN6 33x4
VO_R6
VO_R0
VO_R[0..7]
Configuration A: MCU_ADD_CNTRL pulles HIGH
4_D N
VO_G7
x4_D N
VO_R6
VO_G4
VO_R1
RN10 33x4
*CS1N is not a input or output pin
D PIO11
5
D PIO10
6
D PIO8
7
D PIO9
8
S
4
VO_B3
3
VO_B2
2
VO_B0
1
VO_B1
D PIO8
5
D PIO9
6
D PIO10
7
D PIO11
8
4
3
VO_B7
2
VO_B0
1
VO_B1
5
D PIO_RT1
6
D PIO_RT0
7
8
4
3
VO_R0_0
2
VO_R0_1
1
VO_R0_0
18
VO_R0_1
18
CS1N=0: SVP-EX CPU access enabled
CS1N=1:SVP-EX CPU access disabled
RN11 33x4
RN12 33x4
RN46 33x4_D NS
D PIO13
5
4
VO_B3
D PIO_RT5
5
4
VO_G0_0
VO_G0_0
18
D PIO13
4
D PIO12
3
D PIO14
2
D PIO15
1
5
VO_B5
6
VO_B4
7
VO_B6
8
VO_B7
OPTIONAL, LVDS MAPPING
D PIO12
6
D PIO14
7
D PIO15
8
3
VO_B2
2
VO_B4
1
VO_B5
D PIO_RT4
6
D PIO_RT3
7
D PIO_RT2
8
3
VO_G0_1
2
VO_B0_0
1
VO_B0_1
VO_G0_1
18
VO_B0_0
18
VO_B0_1
18
FOR DS90C385
DNS
Summary of Contents for 42EP25BAT - ANNEXE 685
Page 1: ...42EP25BAT 42HP25BAT...
Page 4: ...Safety Precautions...
Page 5: ......
Page 7: ...b Printed Circuit Audio Board 8...
Page 8: ...Key IC Description Trouble Shooting Guide 1 SVP_EX62 9...
Page 9: ...2 HiDTV 10...
Page 10: ...3 MSP 4450 11...
Page 17: ...2 Others...
Page 18: ......
Page 19: ......
Page 20: ......
Page 24: ......
Page 27: ......