GDM-8246 MULTIMETER
PROGRAMMER MANUAL
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46
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7. STATUS AND ERROR REPORTING
A set of status registers allows the user to quickly determine the
DMM’s internal processing status. The status register, as well as the
status and event reporting system, adhere to SCPI recommendations.
Structure of System
The sketch of the status and event reporting system is showed as
figure 7. Each component of the sketch represents a set of registers and
queues that can read, report, or enable the occurrence of certain events
within the system.
If a specific event in the DMM sets a bit in a
status register
, reading
which can tell you what types of events have occurred.
Each bit in the status register corresponds to a bit in an
enable register;
the enable bit must be high for the event to be reported to the Status Byte
Register.
A Service Request (SRQ) is the last event to occur. The SRQ requests an
interrupt on the GPIB to report events to the system controller.
Status Registers
There are two kinds of status registers are included to the DMM.
z
OPERation Status Registers ( CONDition, EVENt, and ENABle)
z
QUEStionable Status Registers (CONDition, EVENt, and ENABle)
The lower level nodes: QUEStionable and OPERation each have three 16
bits registers: CONDition, EVENt, and ENABle. Figure 8 shows the
sequential relationship between these three types of registers and the
commands that relate to each register.
GDM-8246 MULTIMETER
PROGRAMMER MANUAL
⎯
47
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Frequency Null Sense
Not Used
Not Used
Limit Test Fail HI
Limit Test Fail LO
Capacitance Overload
Ohm Overload
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Voltage Overload
Current Overload
QUEStionable Status
0
1
2
3
9
15
14
13
12
11
10
8
7
6
5
4
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
OPERation Status
Not Used
2
3
0
1
14
13
12
11
10
9
8
7
6
5
4
15
Command Error
Power On
User
Request
Execution Error
Device Dependent
Error
Query Error
Not Used
Standard Event Status Registers
Operation Complete
ESB
RQS/MSS
MA
V
Not Used
Status Byte Register
Not Used
Summary of IEEE 488.2 Status Structure Registers
2
3
0
1
7
6
5
4
2
3
0
1
7
6
5
4
E/E
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
QUES
OPER
SRQ
Error/Event Queue
Output Queue
Figure 7. A graphic representation of the status registers and their connections.
