KM 13
Platinenabbildungen und Schaltpläne / Layout of PCBs and Circuit Diagrams
GRUNDIG Service
3 - 25
PORT0
PORT1
PORT2
PORT3
PORT4
PORT5
PORT6
PORT7
P00-P03
P10-13
P20-23
P30-33
P40-43
P50-53
P60-63
P70-73
S0-S23
S24/BP0-
S31/BP7
COM0-COM3
V
LC0
-V
LC2
BIAS
LCDCL/P30
SYNC/P31
LCD
CONTROLLER
DRIVER
CPU CLOCK
IC V
DD
V
SS
RESET
X2
X1
XT1 XT2
SUB
MAIN
STAND BY
CONTROL
SYSTEM CLOCK
GENERATOR
CLOCK
DIVIDER
CLOCK
OUTPUT
CONTROL
PCL/PT02/P22
ROM *2
PROGRAM
MEMORY
DECODER
AND
CONTROL
GENERAL REG.
RAM
DATA
MEMORY
1024 X 4 BITS
BANK
SBS
SP (8)
CY
ALU
PROGRAM
COUNTER *1
TIMER/EVENT
COUNTER *1
TIMER/EVENT
COUNTER *2
TOUT0
INTT2
INTT1
PT01/P21
PT02/P22/PCL
TI1/TI2/
P12/INT2
BASIC
INTERVAL
WATCHDOG
TIMER
TIMER/
EVENT
COUNTER
P0
WATCH
TIMER
CLOCKED
SERIAL
INTERFACE
INTERRUPT
CONTROL
BIT SEQ
BUFFER (16)
TI0/P13
PTO0/P20
BUZ/P23
SWSB1/P03
SO/SB0/P02
SCK/P01
INT0/P10
INT1/P11
INT2/P12
INT4/P00
KR0/P60
KR7/P73
8
INTCSI
TOUT0
INTW
f
LC0
INTT0
TOUT0
INTBT
fx/2
4
4
4
4
4
4
4
4
8
4
3
24
*1.
µ
PD753012, 753016, 753017
*2. ROM
f
LCD
IC601
µ
PD753017AGC-E03
IC602 TC74HC237AP
A
B
C
SELECT
G1
G2
GL
ENABLE
INPUTS
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
DATA
OUTPUTS