GRASS VALLEY 1200, Installation And Service

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Section 3 Ñ Functional Description
Sync Pulse Generator Circuit
The reference black signal is first buffered and low pass filtered to remove
the subcarrier. From the resulting signal the clamp pulse generator creates
burst flag and sync. Signals from the clamp generator are then used as
control signals on a sample and hold.
The sample and hold has the low pass reference video on its inputs. When
the clamp pulse generator outputs sync, the sample and hold outputs a DC
level equal to the video during sync (sync tip) on one output. When the
clamp pulse generator outputs burst flag, the sample and hold outputs a
DC level equal to the video during back porch on another output. The two
signals are averaged to create the sync slicer (50% of sync). The back porch
level is sent to the input buffer to set the input back porch to ground.
Burst flag is also used to create a video presence signal which keeps the
clamp loop working when there is no video present. This signal is also fed
back to the Control Processor Module.
The Reference low pass video and the 50% of sync level are sent to a
comparator which strips sync off the input reference to create composite
sync. The composite sync is sent to three places: a sync separator, a
standard ID circuit, and a reset generator. The sync separator generates H
sync. This H sync is sent to the phase detector which locks the clock to the
input reference video. The standard ID circuit decides whether the
reference is 525 or 625 line video. The reset generator circuit generates
vertical sync (reset) and a field ID pulse which time the sync pulse
generators. There are programmable delays in the reset path to allow
adjustment of system timing.
The sync pulse generators and many of the counters are duplicated in the
Sync Pulse Generator Submodule.
Clock Pulse Generator
Clock generation starts with a 4.5 MHz VCO. The output of the VCO is sent
to a multiplier/divider circuit which multiplies the clock frequency and
then divides it down to either 13.5 MHz or 18 MHz. This clock is then split
into 3 phases for TX (transmit clock), BD (board clock), and RX (receive
clock). These clocks are sent off the Sync Pulse Generator Submodule to the
Control Processor Module, which has all of the clock fanouts.
Some of the clocks re-enter the Clock Pulse Generator Submodule. One of
the reentered clocks is sent to a counter which divides the clock down to an
H rate. This H signal is compared with the H signal generated by the sync
pulse generator. An error signal is sent back to the Clock generator to
correct for any timing error between the two H signals.