3 Development Board Circuit
3.9 MIPI/LVDS
DBUG388-1.0E
17(22)
3.9
MIPI/LVDS
3.9.1
Overview
Two 10P double columns with 2 mm pitch are reserved on the
development board for MIPI/LVDS input/output testing and high speed data
communication.
3.9.2
MIPI/LVDS Circuit
Figure 3-8 LVDS Circuit
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F_LVDS_A1_P
F_LVDS_A2_P
F_LVDS_A3_P
F_LVDS_A4_P
F_LVDS_A1_N
F_LVDS_A2_N
F_LVDS_A3_N
F_LVDS_A4_N
J15
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F_LVDS_B1_P
F_LVDS_B2_P
F_LVDS_B3_P
F_LVDS_B4_P
F_LVDS_B5_P
F_LVDS_B1_N
F_LVDS_B2_N
F_LVDS_B3_N
F_LVDS_B4_N
F_LVDS_B5_N
J16
