GOWIN DK START GW1NSR-LV4CQN48PC7I6 V User Manual Download Page 12 | Manualshive

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2 Development Board Introduction

2.3 PCB Components

DBUG388-1.0E

5(22)

2.3

PCB Components

Figure 2-3 PCB Components

2.5V

1.2V

3.3V

1.8V

LVDS/MIPI Input

5V IN

Download

Key

OSC

GPIO

UA

RT

LVDS/MIPI Output

J-Link

(MCU Debug)

USB/J-Link Select

FPGA

Reset

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Summary of Contents for DK START GW1NSR-LV4CQN48PC7I6 V

Page 1: ...DK_START_GW1NSR LV4CQN48PC7I6_V 1 1 User Guide DBUG388 1 0E 01 21 2021 ...

Page 2: ... identified as trademarks or service marks are the property of their respective holders as described at www gowinsemi com GOWINSEMI assumes no liability and provides no warranty either expressed or implied and is not responsible for any damage incurred to your hardware software data or property resulting from usage of the materials or intellectual property except as outlined in the GOWINSEMI Terms...

Page 3: ...Revision History Date Version Description 01 21 2021 1 0E Initial version published ...

Page 4: ...back 2 2 Development Board Introduction 3 2 1 Overview 3 2 2 A Development Board Suite 4 2 3 PCB Components 5 2 4 System Block Diagram 6 2 5 Features 6 2 6 Development Board Specification 7 3 Development Board Circuit 9 3 1 FPGA Module 9 3 2 Download Debug 9 3 2 1 Overview 9 3 2 2 USB 10 3 2 3 J LINK 10 3 2 4 Procedure 10 3 2 5 Pins Distribution 11 3 3 Power Supply 11 3 3 1 Overview 11 3 3 2 Power...

Page 5: ...tion 14 3 6 Switches 14 3 6 1 Overview 14 3 7 Key 14 3 7 1 Overview 14 3 7 2 Key Circuit 15 3 7 3 Pins Distribution 15 3 8 GPIO 15 3 8 1 Overview 15 3 8 2 GPIO Circuit 16 3 8 3 Pins Distribution 16 3 9 MIPI LVDS 17 3 9 1 Overview 17 3 9 2 MIPI LVDS Circuit 17 3 9 3 Pins Distribution 18 3 10 RS232 20 3 10 1 Overview 20 3 10 2 RS232 Circuit 20 3 10 3 Pins Distribution 20 4 Precautions 21 5 Gowin Sof...

Page 6: ...mponents 5 Figure 2 4 System Block Diagram 6 Figure 3 1 Connection Diagram for FPGA USB 10 Figure 3 2 FPGA J LINK Connection Diagram 10 Figure 3 3 Power System Distribution 12 Figure 3 4 Clock Reset 13 Figure 3 5 LED Circuit 14 Figure 3 6 Key Circuit Diagram 15 Figure 3 7 GPIO Circuit 16 Figure 3 8 LVDS Circuit 17 Figure 3 9 RS232 Download Connection 20 ...

Page 7: ...load Pins Distribution 11 Table 3 2 FPGA Power Pins Distribution 12 Table 3 3 FPGA Clock and Reset Pins Distribution 13 Table 3 4 LED Pins Distribution 14 Table 3 5 Key Circuit Pins Distribution 15 Table 3 6 J17 GPIO Pins Distribution 16 Table 3 7 J15 FPGA Pin Distribution 18 Table 3 8 J16 FPGA Pin Distribution 19 Table 3 9 RS232 Pins Distribution 20 ...

Page 8: ...evelopment software 1 2 Supported Products The information in the guide applies to GW1NS GW1NSR GW1NSER series of FPGA products GW1NSR 4 GW1NSR 4C GW1NSER 4C 1 1 Related Documents You can find the related documents at www gowinsemi com 1 DS861 GW1NSR series FPGA Products Data Sheet 2 DS881 GW1NSER series FPGA Products Data Sheet 3 UG864 GW1NSR 4 Pinout 4 UG865 GW1NSR 4C Pinout 5 DS881 GW1NSER seri...

Page 9: ...GPIO Gowin Programmable Input output MCU Microprogrammed Control Unit USB Universal Serial Bus SoC System On Chip JTAG Joint Test Action Group SRAM Static Random Access Memory RS232 Recommend Standard 232 ARM Advanced RISC Machines B SRAM Block SRAM SPI Serial Peripheral Interface PLL Phase locked Loop QN48 QFN48 1 3 Support and Feedback Gowin Semiconductor provides customers with comprehensive te...

Page 10: ...C the GW1NS 4 has no built in Cortex M3 processor and the GW1NSER 4C offers one time programming and authentication code features 2 1 Overview Figure 2 1 DK_START_GW1NSR LV4CQN48PC7I6_V1 1 The development board adopts the GW1NS 4 SoC FPGA SoC FPFA is embedded with an ARM Cortex M3 hard core processor When the ARM Cortex M3 hard core processor is employed as the core the needs of the Min memory can...

Page 11: ...ng other benefits The development board offers abundant external interfaces including MIPI LVDS interfaces GPIO interfaces etc There are also button LED and other resources for developers or fans to learn to use 2 2 A Development Board Suite A development board suite includes the following items DK_START_GW1NSR LV4CQN48PC7I6_V1 1 USB Cable Quick Start Guide Figure 2 2 A Development Board Suite 2 3...

Page 12: ...roduction 2 3 PCB Components DBUG388 1 0E 5 22 2 3 PCB Components Figure 2 3 PCB Components 2 5V 1 2V 3 3V 1 8V LVDS MIPI Input 5V IN Download Key OSC GPIO UA RT LVDS MIPI Output J Link MCU Debug USB J Link Select FPGA Reset ...

Page 13: ... 4 SWITCH 5V 5 Pairs LVDS MIPI INPUT 4Pairs LVDS MIPI OUTPUT 1 UART 1 SPI Flash FPGA 2 5 Features The structure and feature of the development board are as follows 5 FPGA Adopts QN48 package Up to 38 user I O Embedded flash data not easily lost if power down Abundant LUT4 resources Multiple modes and capacities of B SRAM 6 FPGA Configuration Modes JTAG AUTO BOOT 7 Clock resource 50MHz Clock Crysta...

Page 14: ... 3 3 V 2 5V 1 8V and1 2V supported 2 6 Development Board Specification Table 2 1 Development Board Specification No Item Functional Description Technical Condition Remarks 1 FPGA Core chip 2 Download Support an USB interface Support JTAG AUTOBOOT USB to JTAG chip integrated on board 3 Power Supply 3 3 V 2 5V 1 8V and 1 2 V output via LDO circuit Input power 5V Provide power for FPGA download circu...

Page 15: ... Flash 64Mbit external SPI FLASH 9 GPIO I O convenient for user extension and test 3 10 MIPI LVDS MIPI LVDS used for testing Five pairs of input Four pairs of output 11 RS232 Used for testing One RS232 12 Protection USB interface ESD protection Power interface Inverse current and over current protection USB interface ESD protection 15kV non contact discharge 8kV contact discharge Schottky diode is...

Page 16: ...kage and pinout information please refer to UG861 GW1NSR series of FPGA Products Package and Pinout User Guide and UG884 GW1NSER series of FPGA Products Package and Pinout User Guide 3 2 Download Debug 3 2 1 Overview The development board provides a USB interface and a J Link interface The fs file can be downloaded to the internal SRAM or internal FLASH as needed Note When downloaded to SRAM the d...

Page 17: ...NK Connection Diagram TMS TCK TDI TDO 20PIN_2 54mm间距双列排针 7 6 3 4 U1 J8 GW1NS4 GW1NSR4 GW1NSER4 3 2 4 Procedure 1 FPGA and MCU Download Mode Plug the USB cable to the development board USB interface J6 Note Before downloading switch the SW3 SW4 SW5 and SW6 on the development board to FT232 side 2 MCU Debugging Mode Connect to J8 with the J Link simulator Note Before Debugging switch the SW3 SW4 SW...

Page 18: ... 3 V 2 5 V 1 2V TDI 3 0 JTAG Signal 3 3 V 2 5 V 1 2V TDO 4 0 JTAG Signal 3 3 V 2 5 V 1 2V MODE0 10 0 Mode selection pin 3 3 V 2 5 V 1 2V JTAGSEL_N 8 0 JTAGSEL_N 3 3 V 2 5 V 1 2V DONE 9 0 One DONE indicator 3 3 V 2 5 V 1 2V 3 3 Power Supply 3 3 1 Overview DC5V is input by USB interface The TI LDO power supply chip is used to step down voltage from 5V to 3 3V 2 5V 1 8V and 1 2V which can meet the po...

Page 19: ...CCO2 LVDS FPGA VCCO0 1 LVDS FPGA VCC FPGA VCCO2 VCCO0 1 MIPI TPS7A7001 LDO 1 8V FPGA VCCO3 FPGA VCCO0 1 Flash 3 3 3 Pins Distribution Table 3 2 FPGA Power Pins Distribution Signal Name Pin No BANK Description I O Level VCCO0 5 0 I O Bank Voltage 2 5V 1 8V 1 2V VCCO1 38 1 I O Bank Voltage 2 5V 1 8V 1 2V VCCO2 36 2 I O Bank Voltage 2 5V 1 2V VCCO3 12 24 3 I O Bank Voltage 1 8V VCCX 25 Auxiliary volt...

Page 20: ...W1NSER4 SN74 AVC4 T245 U26 3 4 3 Pins Distribution Table 3 3 FPGA Clock and Reset Pins Distribution Signal Name Pin No BANK Description I O Level FPGA_CLK 22 3 50MHz crystal oscillator Input 1 8V FPGA_RST_N 23 3 Reset Signal Active Low 1 8V 3 5 LED 3 5 1 Overview There is one green LED in the development board and users can display the required status through the LED There are two LEDs left to fac...

Page 21: ...o BANK Description I O Level F_LED1 33 2 LED1 2 5V 1 2V 3 6 Switches 3 6 1 Overview There are four slide switches in the development board to control program downloading and MCU debugging Please refer to PCB board screen printing for specific operation instructions 3 7 Key 3 7 1 Overview There is one key switch in the development board Users can manually input low level to the corresponding FPGA p...

Page 22: ...VCC3P3 21 F_KEY1 U1 GW1NS4 GW1NSR4 GW1NSER4 SN74A VC4T2 45 U26 3 7 3 Pins Distribution Table 3 5 Key Circuit Pins Distribution Signal Name Pin No BANK Description I O Level F_KEY1 21 2 KEY1 1 8V 3 8 GPIO 3 8 1 Overview One 6P double column pins with 2 54mm pitch is reserved on the development board for user testing ...

Page 23: ...2 4 6 H_B_IO7 H_B_IO9 H_B_IO8 J17 3 8 3 Pins Distribution Table 3 6 J17 GPIO Pins Distribution Signal Name Pin No Socket Pin No BANK Description I O Level H_B_IO7 8 1 0 General I O 2 5V 1 8V 1 2V H_B_IO8 1 2 0 General I O 2 5V 1 8V 1 2V H_B_IO9 2 3 0 General I O 2 5V 1 8V 1 2V 4 GND GND 5 GND GND 6 GND GND ...

Page 24: ...d high speed data communication 3 9 2 MIPI LVDS Circuit Figure 3 8 LVDS Circuit 1 3 5 7 9 2 4 6 8 10 11 13 15 17 19 12 14 16 18 20 F_LVDS_A1_P F_LVDS_A2_P F_LVDS_A3_P F_LVDS_A4_P F_LVDS_A1_N F_LVDS_A2_N F_LVDS_A3_N F_LVDS_A4_N J15 1 3 5 7 9 2 4 6 8 10 11 13 15 17 19 12 14 16 18 20 F_LVDS_B1_P F_LVDS_B2_P F_LVDS_B3_P F_LVDS_B4_P F_LVDS_B5_P F_LVDS_B1_N F_LVDS_B2_N F_LVDS_B3_N F_LVDS_B4_N F_LVDS_B5_...

Page 25: ...S 1 2V MIPI GND 3 GND 4 F_LVDS_A2_P 30 5 2 Differential output channel 2 2 5V LVDS 1 2V MIPI F_LVDS_A2_N 29 6 2 Differential output channel 2 2 5V LVDS 1 2V MIPI GND 7 GND 8 F_LVDS_A3_P 32 9 2 Differential output channel 3 2 5V LVDS 1 2V MIPI F_LVDS_A3_N 31 10 2 Differential output channel 3 2 5V LVDS 1 2V MIPI GND 11 GND 12 F_LVDS_A4_P 35 13 2 Differential output channel 4 2 5V LVDS 1 2V MIPI F_L...

Page 26: ...2 5V 1 2V LVDS MIPI F_LVDS_B2_N 45 6 1 Differential input channel 2 2 5V 1 2V LVDS MIPI GND 7 GND 8 F_LVDS_B3_P 44 9 1 Differential input channel 3 2 5V 1 2V LVDS MIPI F_LVDS_B3_N 43 10 1 Differential input channel 3 2 5V 1 2V LVDS MIPI GND 11 GND 12 F_LVDS_B4_P 42 13 1 Differential input channel 4 2 5V 1 2V LVDS MIPI F_LVDS_B4_N 41 14 1 Differential input channel 4 2 5V 1 2V LVDS MIPI GND 15 GND ...

Page 27: ...e with PC or the other devices 3 10 2 RS232 Circuit Figure 3 9 RS232 Download Connection UART_TXD UART_RXD DB9 UART_TX UART_RX 19 20 J2 U1 GW1NS4 GW1NSR4 GW1NSER4 MAX3232 U4 3 10 3 Pins Distribution Table 3 9 RS232 Pins Distribution Signal Name Pin No BANK Description I O Level UART_TXD 19 3 Serial data Sends from FPGA 1 8V UART_RXD 20 3 Serial data Sends to FPGA 1 8V ...

Page 28: ...rve as LVDS Bank voltage needs to be set as 1 2V via changing J9 jumper position when Bank0 differential pairs serve as MIPI I 6 GW1NSER 4C is GOWIN SecureFPGA with Secure Mode and Authentication Code 7 Gowin version1 9 5 and above is required to develop the GW1NSER 4C device 8 Carefully use the Secure Mode of one time programming for product delivery During factory debugging it is recommended not...

Page 29: ...5 Gowin Software DBUG388 1 0E 22 22 5 Gowin Software Please refer to SUG100 Gowin Software User Guide for details ...

Page 30: ......

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