Goodix GR551 Series Hardware Design Manuallines Download | Manualshive

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Minimal Design for GR551x SoC

Figure 3-11 Openings on PCB pad for clock crystal of GR5515RGBD

3.2.5 RFIO Port

The GR551x provides a single-ended RFIO port. A copper RFIO trace with a characteristic impedance of 50 Ω
interconnects the RF port and the antenna. Because the impedance of RFIO port is not 50 Ω, a matching network is
required to match the port impedance between the RF port and the 50 Ω transmission line.
Components in this network must be placed as close as possible to the RFIO pin. Try to place the first component no
further than 1 mm from the RFIO pin.

shows the PCB layout of the RF port.

Figure 3-12 GR551x routing on a PCB

Copyright © 2021 Shenzhen Goodix Technology Co., Ltd.

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Summary of Contents for GR551 Series

Page 1: ...GR551x Hardware Design Guidelines Version 2 1 Release Date 2021 06 15 Shenzhen Goodix Technology Co Ltd ...

Page 2: ...th technical specifications Shenzhen Goodix Technology Co Ltd hereafter referred to as Goodix makes no representation or guarantee for this information express or implied oral or written statutory or otherwise including but not limited to representation or guarantee for its application quality performance merchantability or fitness for a particular purpose Goodix shall assume no responsibility for...

Page 3: ...al release 1 3 2020 03 16 Updated the package pinout diagrams to the top views in Pinout 1 5 2020 05 30 Updated chip model numbers and pinout diagrams package size diagrams and reference schematic diagrams Changed power supplies and RF and explained by taking a QFN56 circuit as an example Added PCB Layout Reference Design updated ESD Considerations 1 6 2020 06 30 Updated the package layouts and da...

Page 4: ...in External Flash Updated description on I O voltage of GR5515I0ND Changed the previous ESD Considerations into ESD Protection Design and updated contents in this section 2 0 2021 04 29 Updated description on I O voltage of GR5515I0ND in Power Supply and FAQ Updated descriptions in Power Supply Scheme Power Supply Clock ESD Schematic Design PCB Layout Design and Two layer PCBs in QFN Packages 2 1 ...

Page 5: ...uction 27 3 1 2 2 32 MHz Clock XO 27 3 1 2 3 32 768 kHz Clock 28 3 1 3 RF 29 3 1 3 1 Introduction 29 3 1 3 2 RF Scheme 29 3 1 4 I O Pins 30 3 1 5 SWD Interfaces 30 3 1 6 External Flash 31 3 2 PCB Design and Layout Guideline 31 3 2 1 PCB Layer Stackup 32 3 2 2 Components Layout 32 3 2 3 Power Supply 33 3 2 3 1 DC DC Switching Regulator 33 3 2 3 2 RF Input Power Supply 34 3 2 4 Clock 35 3 2 5 RFIO P...

Page 6: ...ndix QFN and BGA Assembly Guideline 59 7 1 Package Information 60 7 1 1 GR5515IGND GR5515I0ND QFN56 60 7 1 2 GR5515RGBD BGA68 NRND 62 7 1 3 GR5515GGBD BGA55 64 7 1 4 GR5513BEND QFN40 66 7 2 Board Mounting Guideline 68 7 2 1 Stencil Design for Perimeter Pads 68 7 2 2 Via Types and Solder Voiding 69 7 2 2 1 Stencil Thickness and Solder Paste 69 7 2 2 2 PCB Materials 69 7 2 3 SMT Printing Process 70 ...

Page 7: ...4F Cortex M4F Cortex M4F Cortex M4F RAM 256 KB 256 KB 256 KB 128 KB 256 KB Flash 1 MB 1 MB 1 MB 512 KB N A Package mm QFN56 7 x 7 x 0 75 BGA68 5 3 x 5 3 x 0 88 BGA55 3 5 x 3 5 x 0 60 QFN40 5 x 5 x 0 75 QFN56 7 x 7 x 0 75 I O Number 39 39 29 22 39 Note The GR5515RGBD is not recommended for new designs 1 1 Features A Bluetooth Low Energy Bluetooth LE 5 1 transceiver integrates Controller and Host la...

Page 8: ...AT chip in reset mode Ultra deep sleep mode 0 65 µA Typical I O LDO off no memory retention Wake up on an external GPIO or an internal Timer Sleep mode 1 3 µA Typical Bluetooth LE link alive I O LDO off supporting AON_RTC AON GPIO and Bluetooth LE Event memory retention and wake up on an external GPIO or an internal Timer Peripherals 2 x QSPI interfaces up to 32 MHz 2 x SPI interfaces 1 SPI Master...

Page 9: ...sm Secure boot Encrypted firmware runs directly from Flash eFuse for encrypted key storage Differentiate application data key and firmware key supporting one data key per device product Packages QFN56 7 mm x 7 mm BGA68 5 3 mm x 5 3 mm BGA55 3 5 mm x 3 5 mm QFN40 5 mm x 5 mm Operating temperature range 40 C to 85 C 1 2 Block Diagram The block diagram of GR551x is shown in the figure below Copyright...

Page 10: ...equencer MCU Subsystem SRAM ROM Security Cores Memory State Reten on Wake up LP Comp Always On Domain Flash Cache Cache Ctrl Flash XIP Ctrl ARM Cortex M4F BB ADC PA System WDT Dual Timer Timer QSPI I2S ADC GPIO UART PWM SPI I2C ISO781 6 LNA Figure 1 1 GR551x block diagram Note For more details of each module in this block diagram see GR551x Datasheet Copyright 2021 Shenzhen Goodix Technology Co Lt...

Page 11: ...GPIO_12 VDDIO_1 VBATL VSS_BUCK VSW VREG VDD_DIGCORE_1V CHIP_EN RF pin DigitalI O supplies pin Analog pin GPIO_13 GPIO_14 42 41 40 39 38 37 36 35 34 33 32 31 AON_GPIO_5 MSIO0 AON_GPIO_4 AON_GPIO_3 AON_GPIO_2 AON_GPIO_1 AON_GPIO_0 TEST_MODE MSIO1 MSIO2 30 29 RTC_P GR5515IGND QFN56 GPIO_9 GPIO_10 GPIO_11 GPIO_15 RTC_N GPIO_29 AON_GPIO_7 AON_GPIO_6 MSIO3 MSIO4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 45 46 47...

Page 12: ...VDDIO1 14 GPIO_10 Digital I O General purpose I O VDDIO1 15 GPIO_11 Digital I O General purpose I O VDDIO1 16 GPIO_12 Digital I O General purpose I O VDDIO1 17 VDDIO_1 Digital I O supply Digital I O supply input VDDIO1 18 GPIO_13 Digital I O General purpose I O VDDIO1 19 GPIO_14 Digital I O General purpose I O VDDIO1 20 GPIO_15 Digital I O General purpose I O VDDIO1 21 CHIP_EN Mixed Signal IN Mast...

Page 13: ...st mode for factory test If TEST_MODE 0 the chip is in normal operation mode VDDIO0 36 AON_GPIO_0 Digital I O Always on GPIO VDDIO0 37 AON_GPIO_1 Digital I O Always on GPIO VDDIO0 38 AON_GPIO_2 Digital I O Always on GPIO VDDIO0 39 AON_GPIO_3 Digital I O Always on GPIO VDDIO0 40 AON_GPIO_4 Digital I O Always on GPIO VDDIO0 41 AON_GPIO_5 Digital I O Always on GPIO VDDIO0 42 AON_GPIO_6 Digital I O Al...

Page 14: ...DDIO0 54 VDD_AMS Analog RF Supply AMS supply Connect to VREG 55 XON Analog RF XO Crystal 56 XOP Analog RF XO Crystal 2 2 GR5515I0ND QFN56 Figure 2 2 shows the pin assignments of GR5515I0ND QFN56 package top view The pins Pin 43 to Pin 53 of GR5515I0ND QFN56 package are different from those of GR5515IGND QFN56 package Copyright 2021 Shenzhen Goodix Technology Co Ltd 8 ...

Page 15: ... GR5515IGND QFN56 GPIO_9 GPIO_10 GPIO_11 GPIO_15 RTC_N GPIO_26 GPIO_18 AON_GPIO_6 MSIO3 MSIO4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 45 46 47 48 49 50 51 52 53 54 55 56 43 44 26 25 24 23 22 21 20 19 18 17 16 15 28 27 GR5515I0ND QFN56 External Flash pin Figure 2 2 GR5515I0ND QFN56 package pinout Table 2 2 shows pin descriptions of GR5515I0ND QFN56 package Table 2 2 GR5515I0ND QFN56 pin descriptions Pin P...

Page 16: ... purpose I O VDDIO1 19 GPIO_14 Digital I O General purpose I O VDDIO1 20 GPIO_15 Digital I O General purpose I O VDDIO1 21 CHIP_EN Mixed Signal IN Master Enable for chip reset pin Minimum value of high level for CHIP_EN is 1 V 22 VIO_LDO_OUT PMU Connected to VBATL output of on chip I O supply regulator used as power input pin of VDDIO0 digital IO domain Connected internally to VDDIO0 23 VDD_DIGCOR...

Page 17: ...Digital I O Always on GPIO VDDIO0 40 AON_GPIO_4 Digital I O Always on GPIO VDDIO0 41 AON_GPIO_5 Digital I O Always on GPIO VDDIO0 42 AON_GPIO_6 Digital I O Always on GPIO VDDIO0 43 GPIO_18 Digital I O Connect to an external Flash VDDIO0 44 GPIO_19 Digital I O Connect to an external Flash VDDIO0 45 GPIO_20 Digital I O Connect to an external Flash VDDIO0 46 GPIO_21 Digital I O Connect to an external...

Page 18: ...PMUGND MSIO3 MSIO2 Analog pin Digital I O supplies pin RF pin 1 2 4 5 6 7 8 3 J K GPIO7 GPIO10 VIO_LDO _OUT GPIO3 VDD_DIG CORE_1V VREG VBATH VSW VBATL MSIO1 RTC_N 9 10 RF_GND GPIO1 GPIO0 DGND DGND TEST_MODE GPIO30 GPIO17 GPIO16 AON_GPIO1 AON_GPIO0 GPIO13 GPIO24 AON_GPIO6 AON_GPIO7 GPIO8 MISO0 RTC_P GPIO14 GPIO15 GPIO9 GPIO12 AON_GPIO5 AON_GPIO4 AON_GPIIO3 AON_GPIO2 NC Figure 2 3 GR5515RGBD BGA68 p...

Page 19: ...I O VDDIO0 C1 RF_GND Analog RF RF ground C3 RF_GND Analog RF RF ground C4 GPIO0 Digital I O General purpose I O default SWDCLK VDDIO1 C5 GPIO29 Digital I O General purpose I O VDDIO0 C6 GPIO31 Digital I O General purpose I O VDDIO0 C7 GPIO25 Digital I O General purpose I O VDDIO0 C8 GPIO16 Digital I O General purpose I O VDDIO0 C10 GPIO14 Digital I O General purpose I O VDDIO1 D1 TRX Analog RF RX ...

Page 20: ... O General purpose I O VDDIO1 G8 MSIO4 Mixed Signal I O Configurable to be a GPIO mixed signal ADC interface VBATL G10 AON_GPIO5 Digital I O Always on general purpose I O VDDIO0 H1 VDD_CORE Digital Supply Digital core supply H3 GPIO11 Digital I O General purpose I O VDDIO1 H4 CHIP_EN Analog PMU Master Enable for chip reset pin Minimum value of high level for CHIP_EN is 1 V H5 VBATH_LDO_WBE Analog ...

Page 21: ...EG Analog PMU Feedback pin of switch regulator K4 VBATH Analog PMU Connect to VBATL K5 VSW Analog PMU DC DC Converter Switching Node K6 VBATL Analog PMU Input from battery K7 MSIO1 Mixed Signal I O Configurable to be a GPIO mixed signal ADC interface VBATL K8 RTC_N Analog PMU RTC terminal 32 768 kHz crystal K9 RTC_P Analog PMU RTC terminal 32 768 kHz crystal K10 AON_GPIO2 Digital I O Always on gen...

Page 22: ...O9 GPIO10 VDDIO_1 AON_GPI O1 VBATL VREG VSW PMUGND Analog pin Digital I O supplies pin RF pin 1 2 4 5 6 7 8 3 Figure 2 4 GR5515GGBD BGA55 package pinout Table 2 4 shows pin descriptions of GR5515GGBD BGA55 package Table 2 4 GR5515GGBD BGA55 package pin descriptions Pin Pin Name Pin Type Description Default Function Voltage Domain A1 VDD_RF Analog RF supply RF supply 1 1 V A2 VDD_VCO Analog RF supp...

Page 23: ...round C6 AON_GPIO7 Digital I O Always on general purpose I O VDDIO0 C7 AON_GPIO2 Digital I O Always on general purpose I O VDDIO0 C8 AON_GPIO5 Digital I O Always on general purpose I O VDDIO0 D1 VBATT_RF Analog RF supply Connect to VBATL D2 GPIO3 Digital I O General purpose I O VDDIO1 D7 MSIO1 Mixed Signal I O Configurable to be a GPIO mixed signal ADC interface VBATL D8 AON_GPIO0 Digital I O Alwa...

Page 24: ...IO1 G3 GPIO11 Digital I O General purpose I O VDDIO1 G4 GPIO16 Digital I O General purpose I O VDDIO0 G5 VIO_LDO_OUT Analog PMU Output of On Chip I O supply regulator Connected internally to VDDIO0 G6 VDD_DIGCORE_1V Analog PMU LDO output of On Chip of digital core connected to 1 µF capacitor G7 MSIO4 Mixed Signal I O Configurable to be a GPIO mixed signal ADC interface VBATL G8 RTC_N Analog PMU RT...

Page 25: ...Analog pin TPP XON VDD_AMS GPIO_26 VBATT_RF CHIP_EN VIO_LDO_OUT RTC_P RTC_N Figure 2 5 GR5513BEND QFN40 package pinout Table 2 5 shows pin descriptions of GR5513BEND QFN40 package Table 2 5 GR5513BEND QFN40 package pin descriptions Pin Pin Name Pin Type Description Default Function Voltage Domain 1 VDD_VCO VDD_RF Analog RF supply Synthesizer VCO supply RF supply Connect to VREG 2 TRX Analog RF RX ...

Page 26: ...from switching regulator 18 VSW Analog PMU DC DC converter switching node 19 VSS_BUCK Analog PMU DC DC converter supply and general battery GND 20 VBATL Analog PMU Input from Battery 21 RTC_N Analog PMU RTC terminal 32 768 kHz crystal 22 RTC_P Analog PMU RTC terminal 32 768 kHz crystal 23 MSIO1 Mixed Signal I O Configurable to be a GPIO mixed signal ADC interface VBATL 24 MSIO0 Mixed Signal I O Co...

Page 27: ...32 GPIO_16 Digital I O General purpose I O VDDIO0 33 GPIO_17 Digital I O General purpose I O VDDIO0 34 GPIO_31 Digital I O General purpose I O VDDIO0 35 GPIO_30 Digital I O General purpose I O VDDIO0 36 GPIO_26 Digital I O General purpose I O VDDIO0 37 VDD_AMS Analog RF AMS supply Connect to VREG 38 XON Analog RF XO Crystal 39 XOP Analog RF XO Crystal 40 TPP Analog RF Test Mux output Copyright 202...

Page 28: ...timize battery utilization it is recommended to supply a GR551x SoC with an external LDO regulator with low quiescent current Ig lower than the product current when product is in standby mode output voltage 3 3 V output current 100 mA load regulation Iout 10 120 10 mA When the maximum input level of the LDO regulator is higher than 5 5 V connect a resistor 0 39 Ω 1 Ω in series to the input end of ...

Page 29: ...ntent retention to the memories where their content is needed after wake up Both the retention voltage and the digital voltage are connected to all power islands through a control switch matrix on the chip 3 1 1 2 Power Supply Scheme GR551x SoCs are equipped with a complete set of power management modules which guarantee the smooth and secure functioning of the GR551x SoCs This section introduces ...

Page 30: ...oC in high voltage scenarios I O LDO is set to off mode automatically based on eFuse configurations after system startup Use VIO_LDO_OUT as input for the VDDIO0 domain and connect VIO_LDO_OUT to the external power supply of 3 3 V or VBATL VSW DC DC switching regulator output connected to two inductors in series a 9 1 nH inductor for reducing RF interference caused by switching noise and a 2 2 µH p...

Page 31: ...n 250 mA To ensure secure operation and to improve the performance of GR551x inductors with higher saturation current and lower direct current resistance are preferred because a higher direct current resistance means higher power consumption 3 1 1 3 I O LDO The GR551x has an on chip linear LDO regulator that is used to supply a nominal 1 8 V default value for use in supplying the on chip Flash exc...

Page 32: ...xcept for MSIOs If you need to change the I O voltage domain corresponding to VDDIO1 use an external power supply voltage range 1 8 V 3 3 V for VDDIO1 In this process the levels of the GPIOs corresponding to VDDIO1 vary depending on the external input voltage When the external power supply is connected to VDDIO1 make sure the input voltage at VDDIO1 is not higher than that of the power VBATL The F...

Page 33: ... Crystal Freq Crystal oscillator frequency 32 MHz ESR Equivalent series resistance 100 Ohm Cload Load capacitance 6 8 pF f Xtal Crystal frequency initial tolerance 50 ppm f Xtal Crystal frequency tolerance over temperature 30 ppm f Xtal Crystal frequency tolerance aging over life of product 10 ppm PDRV Max drive power 100 µW Table 3 5 Recommended 32 MHz crystal examples Part Number Abracon ABM10W ...

Page 34: ... capacitors are required The external crystal must meet the recommended operating conditions as indicated in Table 3 6 and Table 3 7 shows examples of crystals that meet the specifications Table 3 6 32 768 kHz crystal oscillator recommended operating conditions Parameter Description Conditions Min Typ Max Unit Crystal Freq Crystal oscillator frequency 32 768 kHz ESR Equivalent series resistance 10...

Page 35: ... digital frontend provides Automatic Gain Control AGC feedback signals to adjust the gain of the LNA and BB amplifier to maximize the signal to noise ratio SNR at the demodulation On the transmitter side 1 The digital signal from the DFE is transmitted to a phase locked loop PLL for modulation 2 The modulated carrier wave is delivered to a power amplifier PA with amplification factor configurable ...

Page 36: ...H 0 2 nH 50 mOhm Q 20 250 MHz 2 4 nH 0402 Murata LQW15AN2N4B00 3 1 4 I O Pins The GR551x has software configurable I O pin assignment where different peripherals can be multiplexed out on different chip pins When configured to GPIOs they can be set as input output with configurable pull up or pull down resistors I O pins retain their last state when system enters the sleep or deep sleep mode Only ...

Page 37: ...urer Flash Capacity Range of Supply Power Voltage Unit V P25Q128L Puya Semiconductor 128 Mb 1 65 2 00 P25Q128H Puya Semiconductor 128 Mb 2 30 3 60 W25Q64JW Winbond 64 Mb 1 70 1 95 XT25Q64D XTX 64 Mb 1 65 2 10 W25Q64JV Winbond 64 Mb 2 70 3 60 XM25QH64A XMC 64 Mb 2 30 3 60 XT25F64B XTX 64 Mb 2 70 3 60 For more details about Flash model selection for GR5515I0ND see GR5515I0ND Flash Selection Guide No...

Page 38: ... examples for designing 4 layer PCB layouts are provided in Section 4 2 1 Four layer PCBs in QFN56 Package and Section 4 2 4 Four layer PCBs in BGA68 Package NRND to help users quickly get started with development and PCB layout design For users who need to reduce costs on QFN packages they shall choose 2 layer PCBs with special attention to the layout of power filter components power input the gr...

Page 39: ...hing regulator 1 Components L3 9 1 nH inductor L4 2 2 µH inductor and C15 2 2 µF capacitor connected to DC DC switching regulator should be placed as close to VSW and VREG of the chip as possible A distance within 3 mm is recommended 2 The net of VSW radiates stronger interference before VSW signals passing through the inductors and thus should be placed at a minimum distance of 0 2 mm from other ...

Page 40: ...ng path goes through the capacitors first and then connected to the chip power pins In case the capacitors are not placed on the same layer with the pins the vias should be located close to the decoupling capacitors 2 The power trace should be as short as possible and at least 0 2 mm wide A minimum distance at 0 2 mm from other signals should be guaranteed D 3mm D 3mm D 3mm D 3mm Figure 3 8 Refere...

Page 41: ...e with other signals on the board Make sure there is no other trace route next to under the crystal or the crystal routes It is recommended to shield the routes of the 32 MHz crystal If the ground below the crystal is clean and no crosstalk or interference is involved provide openings on the pad underneath the crystal as shown in Figure 3 11 which helps to reduce parasitic capacitance Figure 3 10 ...

Page 42: ...antenna Because the impedance of RFIO port is not 50 Ω a matching network is required to match the port impedance between the RF port and the 50 Ω transmission line Components in this network must be placed as close as possible to the RFIO pin Try to place the first component no further than 1 mm from the RFIO pin Figure 3 12 shows the PCB layout of the RF port Figure 3 12 GR551x routing on a PCB ...

Page 43: ...e placed along the transmission line every 1 25 mm and right next to the ground pads of the matching components A PI network should be placed close to the antenna feedpoint for antenna matching purposes The matching network value of antenna is adjusted according to the actual antenna used It is recommended to use mature antenna schemes and recommended values of antenna factories 3 2 6 Grounding Al...

Page 44: ...D protection scheme as shown in the figure below ESD 5V TVS FB1 600 Ω BLM15PX601SN1 FB2 600 Ω BLM15PX601SN1 CHAR CHAR Charge IC GND GR551x LDO Lithium ba ery VBATL POWER IN BAT Figure 3 13 ESD protection scheme at charging ports Recommended models of TVS diodes and ferrite beads as well as model selection requirements are listed in the tables below Table 3 11 Model selection for TVS diodes Paramet...

Page 45: ...ge of the system exceeds 8 kV and contact discharge is above 4 kV as the target products require additional reset mechanisms such as watchdog timeout reset are required to enhance ESD protection If an external WDT needs to be included do not start the WDT before firmware is programmed to the SoC to avoid inadvertent system reset Choose WDT that meets the requirements in Table 3 15 A recommended mo...

Page 46: ...e by the following rules for GR551x PCB grounding PCB with four layers or above is recommended A GR551x SoC is adjacent to the GND layer The GND layer shall be solid and complete so as to effectively prevent static from setting in Connect GR551x GND pin to the GND pin on the top layer and then connect the GR551x SoC GND pin to the GND pins on the other layers through vias For GR551x in QFN package...

Page 47: ...CORE_1V VIO_LDO_OUT VDD_VCO VDD_AMS VDDIO_1 C1 C2 C3 C4 C5 C6 C7 Figure 3 15 Filter capacitor layout for power supply 4 It is recommended to place communication signals neither on the top layer nor the bottom layer in the PCB stack up due to the ESD susceptibility of I O pins Avoid routing signals susceptible to ESD events such as clocks and reset pins at the edge of the board It is recommended to...

Page 48: ...protection performance and is therefore not recommended VCC GND IC PCB rou ng through pad of ﬁlter capacitor Figure 3 18 Proper routing for a capacitor as an example VCC GND IC Connec ng to ﬁlter capacitor with long wires Figure 3 19 Improper routing for a capacitor as an example 3 2 7 1 3 Product Structural Design Shell gaps shall be sealed to prevent static electricity from setting in Copyright ...

Page 49: ...stant adhesives on the exposed area of motherboard connectors to prevent short circuit or static electricity from setting in 3 2 7 2 ESD Considerations in Production Transport and Debugging To steer away from ESD events stringent ESD control is also required during production transport debugging and other relevant phases Wear antistatic wrist strap in these processes Touching the SoC with bare han...

Page 50: ...erence Design 4 1 Reference Schematic Diagram Figure 4 1 is the reference schematic for GR5515IGND QFN56 package Figure 4 1 Reference schematic for GR5515IGND QFN56 package Copyright 2021 Shenzhen Goodix Technology Co Ltd 44 ...

Page 51: ...Reference Design Figure 4 2 is the reference schematic for GR5515I0ND QFN56 package Figure 4 2 Reference schematic for GR5515I0ND QFN56 package Copyright 2021 Shenzhen Goodix Technology Co Ltd 45 ...

Page 52: ...Reference Design Figure 4 3 is the reference schematic for GR5515RGBD BGA68 package Figure 4 3 Reference schematic for GR5515RGBD BGA68 package Copyright 2021 Shenzhen Goodix Technology Co Ltd 46 ...

Page 53: ...Reference Design Figure 4 4 is the reference schematic for GR5515GGBD BGA55 package Figure 4 4 Reference schematic for GR5515GGBD BGA55 package Copyright 2021 Shenzhen Goodix Technology Co Ltd 47 ...

Page 54: ...mples to help users quickly get started with product development and design 4 2 1 Four layer PCBs in QFN56 Package In this reference design all GPIO signals are available as output The 0 6 mm PCB is composed of four layers with plated through holes PTHs The RF route is 22 mil wide which is the same with the component pad To ensure the impedance of the RF route is not higher than 50 Ω provide openi...

Page 55: ...yer PCB QFN56 Details for the PCB layout reference design are provided below 1 Top layer This layer is used for component layout and routing of key signals such as RF Figure 4 7 Top layer design for 4 layer PCB QFN56 Copyright 2021 Shenzhen Goodix Technology Co Ltd 49 ...

Page 56: ...ded on L2 Figure 4 8 L2 design for 4 layer PCB QFN56 3 L3 This layer is used for the power and a small number of routes In the reference design L3 is used as the reference ground layer for the RF transmission line and therefore the part underneath the RF transmission line shall be complete Figure 4 9 L3 design for 4 layer PCB QFN56 4 Bottom layer This layer is used for filter components layout and...

Page 57: ... Strictly follow the PCB design rules in Section 3 2 PCB Design and Layout Guideline Most importantly make sure power filter capacitors are placed close to power pins and connection to the GND return path should be enhanced Details for the PCB layout reference design are provided below 1 Try to place components and routing on the top layer only as shown in Figure 4 11 the top layer is used for com...

Page 58: ...ATL GND via for power input from VBAT_RF GND vias for RF signals Capacitor GND via for power input from VDD_VCO RF Capacitor GND via for power input from VDD_AMS Figure 4 12 Power and GND routing reference design for 2 layer PCB QFN40 4 2 3 External Flash Connection for GR5515I0ND The GR5515I0ND uses external QSPI Flash with clock frequency up to 64 MHz To avoid crosstalk from other signals the Fl...

Page 59: ... reference plane for the 50 Ω RF transmission line Details for the PCB layout reference design are provided below 1 Top layer This layer is used for component layout and routing for key signals such as RF Figure 4 14 Top layer design for 4 layer PCB BGA68 2 L2 This is the reference ground plane for the ground return path of the 50 Ω RF transmission line Two openings are provided underneath the sig...

Page 60: ...omains and place a small number of signal lines Figure 4 16 L3 design for 4 layer PCB BGA68 4 Bottom layer This layer is used for filter components layout and signal routes Filter components should be as close to the corresponding IC pins as possible Copyright 2021 Shenzhen Goodix Technology Co Ltd 54 ...

Page 61: ...Reference Design Figure 4 17 Bottom layer design for 4 layer PCB BGA68 Copyright 2021 Shenzhen Goodix Technology Co Ltd 55 ...

Page 62: ... voltages VDDIO1 can use the external input voltage which should not be higher than the power voltage Solution Setting voltages of all I O pins to 3 3 V in a GR551x SoC is not allowed According to the above Issue Analysis you can set the I O pin voltages specific to demands in different environments Note The Flash of GR5515I0ND supports operations in high voltage scenarios when VDDIO0 3 3 V VBATL ...

Page 63: ...ts for RF a PI circuit close to GR551x and a PI circuit close to the antenna Whether these two PI circuits can be simplified or removed needs to be treated differently Solution The PI circuit close to GR551x is used to match GR551x internal PA and cannot be removed It cannot be simplified also as its inductance and capacitance values must be kept consistent with the recommended circuit The impedan...

Page 64: ...ture GPIO General Purpose Input Output LDO Low dropout LNA Low Noise Amplifier NRND Not Recommended for New Designs PLL Phase Locked Loop PMU Power Management Unit PCB Printed Circuit Board PTH Plated Through Hole QFN Quad Flat No Lead Package QSPI Queued Serial Peripheral Interface RoHS Restriction of Hazardous Substances Directive SDK Software Development Kit SOC System on Chip SPI Serial Periph...

Page 65: ...nt effect on mounting QFN or BGA packages on the board and the quality of solder joints Some of these factors include amount of solder paste coverage in exposed ground thermal pad region stencil design for peripheral and thermal pad region type of vias board thickness lead finish on the package surface finish on the board type of solder paste and reflow temperature profile Note It should be emphas...

Page 66: ...Trench type solder mask opening where a big opening is designed around all pads on each side of the package with no solder mask in between the pads as shown in Figure 7 2 Note The inner edge of the solder mask should be rounded especially for corner leads to allow for enough solder mask web in the corner area Figure 7 2 Solder mask definition for perimeter lands for 0 4 mm pitch parts 7 1 Package ...

Page 67: ...posed Pad Size 5 2 x 5 2 mm 0 1 mm The Figure 7 3 shows the GR5515IGND GR5515I0ND QFN56 package outlines Figure 7 3 GR5515IGND GR5515I0ND QFN56 package outlines Note Drawing is not to scale Table 7 2 GR5515IGND GR5515I0ND QFN56 package dimensions Dimensions in mm Dimensions in inch Symbol MIN NOM MAX MIN NOM MAX A 0 700 0 750 0 800 0 028 0 030 0 032 A1 0 000 0 020 0 050 0 000 0 001 0 002 Copyright...

Page 68: ...0 0 004 Note Values in inches are converted from mm and rounded to 3 decimal digits Refer to the JEDEC standard J STD 020 for relevant soldering information The document can be downloaded at https www jedec org 7 1 2 GR5515RGBD BGA68 NRND GR5515RGBD BGA68 is a 68 pin and 5 3 x 5 3 x 0 88 mm package It is qualified for MSL3 Table 7 3 GR5515RGBD BGA68 package information Parameter Value Unit Toleran...

Page 69: ...D BGA68 package dimensions Dimension in mm Dimension in inch Symbol MIN NOM MAX MIN NOM MAX A 0 780 0 880 0 980 0 031 0 035 0 039 A1 0 130 0 180 0 230 0 005 0 007 0 009 A2 0 650 0 700 0 750 0 026 0 028 0 030 c 0 140 0 170 0 200 0 006 0 007 0 008 D 5 200 5 300 5 400 0 205 0 209 0 213 Copyright 2021 Shenzhen Goodix Technology Co Ltd 63 ...

Page 70: ...e converted from Millimeters and rounded to 3 decimal digits 7 1 3 GR5515GGBD BGA55 GR5515GGBD BGA55 is a 55 pin and 3 5 x 3 5 x 0 60 mm BGA package It is qualified for MSL3 Table 7 5 GR5515GGBD BGA55 package information Parameter Value Unit Tolerance Package Size 3 5 x 3 5 mm 0 1 0 1 mm BGA Ball Count 55 Total Thickness 0 60 0 05 0 05 mm mm BGA Ball Pitch 0 40 Ball Diameter 0 20 Ball Height 0 12 ...

Page 71: ...e 7 6 GR5515GGBD BGA55 package dimensions Dimension in mm Dimension in inch Symbol MIN NOM MAX MIN NOM MAX A 0 550 0 600 0 650 0 022 0 024 0 026 A1 0 090 0 120 0 150 0 004 0 005 0 006 A2 0 435 0 475 0 505 0 017 0 019 0 020 A3 0 350 REF 0 014 REF c 0 125 REF 0 005 REF Copyright 2021 Shenzhen Goodix Technology Co Ltd 65 ...

Page 72: ...hes are converted from Millimeters and rounded to 3 decimal digits 7 1 4 GR5513BEND QFN40 GR5513BEND QFN40 is 40 pin and 5 x 5 x 0 75 mm package It is qualified for MSL3 Table 7 7 GR5513BEND QFN40 Package Information Parameter Value Unit Tolerance Package Size 5 x 5 mm 0 1 mm QFN Pad Count 40 Total Thickness 0 75 0 05 mm QFN Pad Pitch 0 40 Pad Width 0 20 0 05 mm Exposed Pad Size 3 7 x 3 7 mm 0 1 m...

Page 73: ... NOM MAX MIN NOM MAX A 0 700 0 750 0 800 0 028 0 030 0 032 A1 0 000 0 020 0 050 0 000 0 001 0 002 A2 0 550 0 022 A3 0 203 REF 0 008 REF b 0 150 0 200 0 250 0 006 0 008 0 010 D 5 000 BSC 0 197 BSC E 5 000 BSC 0 197 BSC e 0 400 BSC 0 016 BSC D2 3 600 3 700 3 800 0 142 0 146 0 150 E2 3 600 3 700 3 800 0 142 0 146 0 150 L 0 300 0 400 0 500 0 012 0 016 0 020 Copyright 2021 Shenzhen Goodix Technology Co...

Page 74: ...y to company careful process development is recommended 7 2 1 Stencil Design for Perimeter Pads The optimum and reliable solder joints on the perimeter pads should have about 50 to 75 microns 2 mils to 3 mils standoff height and good side fillet on the outside A joint with good standoff height but no or low fillet will have reduced life but may meet application requirement The first step in achiev...

Page 75: ... can increase the current path of the circuit The maximum size for a void should be less than the via pitch within the plane This recommendation would assure that any one via would not be rendered ineffectual based on any one void increasing the current path beyond the distance to the next available via 7 2 2 1 Stencil Thickness and Solder Paste The stencil thickness of 0 125 mm is recommended for...

Page 76: ...mil larger than the top can be utilized Sn Ag Cu solder does not wet as well as Sn Pb solder Printing Process The printing process requires no significant changes comparing with that applies Sn Pb solder Any guidelines recommended by the paste manufacturers to accommodate paste specific characteristics should be followed Post print inspection and paste volume measurement is very critical to ensure...

Page 77: ...llow the recommendation from paste manufacturers and general standards such as JEDEC IPC J STD 20 Figure 7 9 shows the range of temperature profiles of the J STD 20 specification The profile parameters and component peak temperature guidelines are listed in Table 7 9 Figure 7 9 JEDEC recommended lead free reflow profile The GR551x fulfills the lead free soldering requirements from IPC JEDEC i e re...

Page 78: ...es offers higher flexibility to optimize the reflow profile for complex and or larger boards Nitrogen atmosphere can improve the wet ability and reduce temperature gradient across the board It can also enhance the appearance of the solder joints by reducing the effects of oxidation 7 4 Rework Guideline Because solder joints are not fully exposed for QFN and BGA packages any retouch is limited to t...

Page 79: ...ting in the component area and heating of adjacent components should be minimized Excessive airflow should also be avoided because this may cause chip scale package CSP to skew Air velocity of 15 20 liters per minute is a good starting point Once the joints have reflowed the Vacuum lift off should be automatically engaged during the transition from reflow to cool down Because of the small size of ...

Page 80: ... system should be used to align the component on the motherboard This will form an image of leads overlaid on the mating footprint and aid in proper alignment The alignment should also be done at 50 to 100x magnification The placement machine should have the capability of allowing fine adjustments in X Y and rotational axes 7 4 5 Component Attachment The reflow profile developed during original at...

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