Chipset Features Setup
↑ ↓ → ←
:Move Ente r:S elec t +/-/ PU/P D:Va lue F1 0:S ave ESC :Ex it F1: Gene ral Hel p
F5:Previous Val ues F6:Fail-S Afe Def aults F7:Opti mized D efaults
DRAM Clock
This item allows you to set the DRAM Clock. Options are Host CLK,
HCLK+33M or HCLK-33M. Please set the item according to the Host (CPU)
Clock and DRAM Clock.
SDRAM Cycle Length
This feature is similar to SDRAM CAS Latency Time. It controls the time delay
(in clock cycles - CLKs) that passes before the SDRAM starts to carry out a
read command after receiving it. This also determines the number of CLKs for
the completion of the first part of a burst transfer. Thus, the lower the cycle
length, the faster the transaction. However, some SDRAM cannot handle the
lower cycle length and may become unstable. So, set the SDRAM Cycle
Length to 2 for optimal performance if possible but increase it to 3 if your
system becomes unstable.
3312400 User's Manual
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