Glitch Works 8085 SBC, User Manual And Assembly Manual

Page: 9 / 17

5 Technical Notes
5.1 Board Control Register
The 8085 SBC rev 3 includes a board control register, which is a series of writable latches that affect
how various parts of the built-in circuitry function. This register is addressed at
I/O BASE + 0x02
;
in the default configuration, this places the board control register at
0x02
. Electrically, it is composed
of three different latches: a 4-bit D-type latch at U2, and two elements of a dual D-type latch at U3.
The bits of the board control register are mapped as follows:
Register Bit Function Notes
0 ROM Page Address, bit 0 Cleared on reset
1 ROM Page Address, bit 1 Cleared on reset
2 ROM Page Address, bit 2 Cleared on reset
3 ROM Boot flip-flop Reset state determined by J1
4 ROM Enabled flip-flop Reset state determined by J2
5 Unused
6 Unused
7
USER
LED output Cleared (LED off) on reset
Bits 0-2 control the selected 4K page of ROM available at
ROM BASE
. These bits are cleared on reset
so that the first page of ROM is available for booting. Writing to these bits immediately changes the
ROM page. The state of these bits is available through the Board Status Register.
Bit 3 controls the ROM Boot flip-flop. When set, ROM is addressed at all memory locations,
repeating throughout memory. This allows the 8085 to read ROM code at
0x0000
on reset. Writing
a 0 to this bit clears it and immediately switches off the ROM Boot functionality. Typically, ROM
boot code should contain a jump to a startup routine in ROM, which should immediately clear the
ROM Boot bit. The reset state of bit 3 is controlled by J1, see the “Configuration” section for more
information. The state of these bits is available through the Board Status Register.
Bit 4 enables ROM when set, and disables ROM when cleared. This allows unmapping ROM for use
of the full 64 KB of system memory. Writing a 0 to this bit clears it and immediately switches off
ROM, writing a 1 to this bit switches ROM in. The selected ROM page is not affected. The reset
state of bit 3 is controlled by J2, see the “Configuration” section for more information. The state of
these bits is available through the Board Status Register.
Bits 5 and 6 are not implemented; that is, nothing responds to their state when writing to the Board
Control Register.
Bit 7 is connected to the
USER
LED (D3). Writing a 1 to this bit lights the LED, writing a 0 turns
the LED off. This bit is cleared on reset.
5.2 Board Status Register
The 8085 SBC rev 3 includes a board status register which provides the state of several bits of the
Board Control Register, as well as
ROM OPT
(SW3) DIP switch settings. This register is addressed
at
I/O BASE + 0x02
; in the default configuration, this places the board control register at
0x02
.
8