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1
Introduction
The Glitch Works 8085 SBC rev 3 (GW-8085SBC-3) is a single-board computer based on the Intel
8085 CPU. It includes the following features:
•
Intel 8085 CPU at 2 MHz (guaranteed operation, overclocking possible)
•
64 KB static RAM, FeRAM compatible
•
32 KB ROM, EEPROM, or FeRAM in 4K pages, in-board programmable
•
Serial console via Intel 8251A USART
•
USART clock independent of system clock
•
Software controlled power-on jump
•
ROM paging and switch-out
•
Debounced reset and power supply supervisory circuit
•
Glitchbus expansion header
The 8085 SBC rev 3, when paired with GWMON, is a self-contained system needing only a serial
terminal (or teminal emulation software on a PC) for full operation. GWMON for the 8085 SBC
rev 3 includes Glitch Works ROM-FS, which allows for the storage of file records in ROM. These
records can be loaded from the monitor, or automatically selected by option switches on reset/power-
up. This also allows for in-board updates to GWMON without overwriting the current, known-good
copy.
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Configuration
The 8085 SBC rev 3 includes a number of jumpers and switch packs for configuring system op-
tions:
Name
Function
J1
ROM Boot, 1-2 disables ROM boot, 2-3 enables ROM boot
J2
ROM Enabled, 1-2 disables ROM on reset, 2-3 enables ROM on reset
J5
Console USART Bitrate, jumper one position only for printed speed
SW2
I/O Port Block Base Address
SW3
ROM Base Address, Write Protect, and Boot Page Address
For normal operation with standard GWMON ROM images, J1 and J2 should both be set 2-3, SW2
should be all open, SW3 1-4 should be closed, and SW3 5-8 should be open. This places the I/O block
at
0x00 - 0x03
, ROM at
0xF000 - 0xFFFF
, and enables jump to ROM on reset and power-up.
Console bitrate is selected with J5. The board’s silkscreen shows each position’s speed.
Only one
speed may be selected
. Note that the silkscreen legend will be incorrect if anything other than a
2.4576 MHz crystal is used at Y2.
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Summary of Contents for 8085 SBC
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