Electrically, it is composed of an octal tristate bus transceiver. The bits of the board status register
are mapped as follows:
Register Bit
Function
Notes
0
RPA0 switch, SW3-8
Closed reads 1
1
RPA1 switch, SW3-7
Closed reads 1
2
RPA2 switch, SW3-6
Closed reads 1
3
ROM Boot status
Boot Enabled reads 1
4
ROM Enabled status
ROM Enabled reads 1
5
ROM Page Address latch, bit 0
6
ROM Page Address latch, bit 1
7
ROM Page Address latch, bit 2
Bits 0-2 reflect the state of SW3 positions 8 through 6. These positions are labeled
RPA0 - RPA2
in
the silkscreen. With the standard version of GWMON, these switches select the ROM-FS record to
load into memory at reset. A 1 in a given bit position corresponds to a closed switch.
Bit 3 reflects the status of the ROM Boot flip-flop. ROM Boot is enabled when this bit reads 1.
Bit 4 reflects the status of the ROM Enabled flip-flop. ROM is enabled when this bit reads 1.
Bits 5-7 reflect the state of the ROM Page Address latch, which selects the currently addressed 4K
page from ROM at U17.
5.3
Default Memory Map
Address Range
Contents
0x0000 - 0x7FFF
Static RAM, IC socket U15
0x8000 - 0xEFFF
Static RAM, IC socket U16
0xF000 - 0xFFFF
Static RAM, IC socket U16, when ROM is disabled
0xF000 - 0xFFFF
4K page of ROM, IC socket U19, when ROM is enabled
Onboard memory devices may be overlaid by external devices on the Glitchbus using the
*BMASK
signal.
5.4
Default I/O Map
I/O Address
R/W
Function
0x00
R/W
USART Data Register
0x01
R
USART Status Register
0x01
W
USART Control Register
0x02
R
Board Status Register
0x02
W
Board Control Register
0x03
R
Board Status Register
0x03
W
Board Control Register
Note that the Board Control Register and Board Status register appear at both
0x02
and
0x03
.
9
Summary of Contents for 8085 SBC
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