Hints for programming the latches
I/O addresses:
I/O addresses are incompletely decoded due to compatibility to ZX81. I/O addresses use
exclusively one from 8 bits (low active) which reduces the capability of the system to handle 8
devices only.
Following addresses are used from the ZX81 hardware:
A0
address $FE => switches on NMI circuit and keyboard handling
A1
address $FD => switches off NMI circuit
A2
address $FB => control of printer
For the additional features of the ZXmore for address the latches and USB communication a
further address bit is used which may be choosed from A3/A4/A5/A6/A7 for avoiding address
overlap when additional hardware modules are used. Standard address together with A0 and
A1 is:
address $7F USB communication
address $7E RAM latch
address $7D ROM latch
address $7C internal usage
Interesting for programmers may be the RAM and ROM latches to control the memory
management. This is recommended for experts only as this may influence the stability of the
ZXmore.
The schematic shows the latch control. The RAM latch controls an address comparator which
compares the programmed address with the current address and activate RAMCS when the
current address is greater than the programmed and otherwise activates ROMCS. Bit 4 allows
to swap ROM and RAM.
Bit 5-7 selects the memory page (64k) used for the active instance while these bits are
inverted. Instance 0 has all 3 bits set while instance 7 has all bits reset.
V1.9 - 06/2016
ZXmore & ZXmaster – user manual
page 27 from 29
