HRG and UDG:
The ZX81 uses a character generator which automatically overdrives the address bus for
feeding the shift register with data from the char map inside the ROM in conjunction with a
scanline counter (0-7). The address is derived from the index register, the char read in the
display file and the scanline counter.
This overdrive is used for the ROM addressing only (through the ULA). Consequently char
maps can be place in ROM only and are not usable from RAM for user defined graphics (UDG).
On the other hand high resolution graphics (HRG) can be used with RAM only to read the pixel
file (256x192 pixels in 6kB area). So HRG works only from RAM and UDG only from ROM on a
standard ZX81 hardware.
The ZXmore has no direct assignment of memory areas for HRG and UDG. The address
override is activated with interrupt acknowledge cycles only which are used with UDG only but
not with HRG. Plain software HRG which address the content for the video shift register with
index register and refresh register do not use any interrupts.
This circumstance with no interrupts when using HRG is used to
control the address override mode. Any INT ACK sets a flipflop
which activates the char map logic while activating NMI resets
this flipflop for index/refresh register addressing.
So user defined graphics may be stored in ROM or RAM and are
addressed with index/refresh register. It is possible to use 64
char sets (with 64 inverted chars) or use of 128 chars while the
second 64 chars are selected with D7 which is normally used for
just inverting the chars.
Bit 7 automatically overrides A9 during char map mode as soon
as bit 0 of index register (A8) is set during the refresh.
A normal char set consists of 64*8 bytes (=512 bytes) and
addressing is used at even boundary only – so bit 0 of index
register is used to control the usage of 64 or 128 char sets:
0 => 64 chars (512 bytes)
1 => 128 chars (1024 bytes)
V1.9 - 06/2016
ZXmore & ZXmaster – user manual
page 25 from 29
