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Embedded PC/RTOS Features 47
3.6 NVRAM
The VMIVME-7805/VME-7805RC provide 32 KByte of nonvolatile SRAM. This
memory is mapped in 32k of address space starting at the address in BAR1. This
memory is available at any time and supports byte, short word and long word
accesses from the PCI bus. The contents of this memory is retained when the
power to the board is removed.
3.7 VME Control
The following table shows the register definitions for the VMIVME-7805/
VME-7805RC (offset from BAR0).
Please refer to Table 3-2, PCI Configuration Space Registers, on page 41 for more
information concerning BAR0.
Table 3-3 Register Definitions Offset From BAR0
Register Name
Offset
VMECOMM
0x00
Bit Name
Bit
Definition
MEC_SEL
0
Master big-endian enable bit 1=Big Endian 0=Little
Endian bit
SEC_SEL
1
Slave Big-Endian enable bit 1=Big Endian 0=Little Endian
ABLE
2
Auxiliary BERR logic enable bit
1=Aux. BERR enabled 0=Aux. BERR disabled
BTO
3
Bus error timer enabled 1=enabled 0=disabled
BTOV [1:0]
5:4
Timeout value
00 - 16 µs
01 - 64 µs
10 -256 µs
11 - 1.00 ms
BERRI
6
BERR interrupt enable 1=Interrupt enabled 0=Interrupt
disabled
BERRST
7
BERR status read/clear bit
1=Clear BERR status 0=Do nothing
SFENA
8
Enables generation of VME SYSFAIL upon WDT timeout
1= Enable SYSFAIL generation 0=Disable
Unused
9
Not Used
BPENA
10
Endian conversion bypass bit
1 = bypass 0 = not bypassed
VBENA
11
VME enable bit
1 = enabled 0 = disabled
Unused
31:12 Not
Used
VBAR
0x08
VME_ADDR
All
Latched VME Address
VBAM
0x04
VME_ADDR
5:0
Latched VME Address Modifier
Unused
31:6
Not Used
SEC_SEL
0x001