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34 VMIVME-7805/VME-7805RC Hardware Reference Manual
2.7 Integrated Peripherals
The VMIVME-7805/VME-7805RC incorporate a National Semiconductor
Super I/O (SIO) chip. The SIO provides the VMIVME-7805/VME-7805RC with a
standard floppy drive controller, two 16550 UART-compatible serial ports,
keyboard and mouse ports and general purpose I/O for system monitoring
functions. Both serial port signals are available from the front panel. The floppy
signals are available via the VME backplane connectors and can be accessed with
the appropriate RTM (VMIACC-0562/ACC-0562RC).
The IDE interface is provided by the Intel I/O Controller Hub (ICH4-M) chip. The
IDE interface supports two channels known as the primary and secondary
channels. The secondary channel is routed onboard to the optional CompactFlash
socket. The primary channel is routed out the VME backplane and can be
accessed using a VMIACC-0562/ACC-0562RC RTM which terminates into a
standard 40-pin header. This channel can support two drives, a master and slave.
The IDE interface on the VMIVME-7805/VME-7805RC supports Ultra ATA/33,
Ultra ATA/66 and Ultra ATA/100 drives and automatically determines the proper
operating mode based on the type of drive used. In order to properly function in
the Ultra ATA/100 mode, a special 80 conductor cable must be used instead of the
standard 40 conductor cable. This cable is typically available from the
Ultra ATA/100 drive manufacturer.
Table 2-6 NMI Register Bit Descriptions
Status Control Register (I/O Address $061, Read/Write, Read Only)
Bit 7
SERR# NMI Source Status (Read Only) - This bit is set to 1 if a system board agent detects a
system board error. It then asserts the PCI SERR# line. To reset the interrupt, set Bit 2 to 0 and
then set it to 1. When writing to port $061, Bit 7 must be 0.
Bit 2
PCI SERR# Enable (Read/Write) - 1 = Clear and Disable, 0 = Enable
Enable and Real-Time Clock Address Register (I/O Address $070, Write Only)
Bit 7
NMI Enable - 1 = Disable, 0 = Enable