31
CHAPTER
Programming
Contents
Data Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Data Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Control and Status Register (CSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Introduction
The VMIVME-2533 performs output transfers by writing data to the appropriate
Output Data Registers (ODRs). The differential digital outputs are read by performing
a read from differential data receivers. For programming simplicity differential
receivers are mapped into the same address locations as the drivers. Therefore, the
bits of each register correspond to an output channel when performing a write to that
register, but the output data can be read back by performing a read cycle.
The base address required for accessing the VMIVME-2533 is selected by the address
jumpers JD and JF referred to Chapter 2
Configuration and Installation
on page 22. The
on-board registers are selected by address bits A02, A01, DS1, and DS0.
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