GE H
EALTHCARE
D
IRECTION
5394141, R
EVISION
5
LOGIQ™ P5 S
EVICE
M
ANUAL
Section 5-4 - Main Board Detail
5-17
5-4-3-3
PERIPHERAL BLOCK
•
IDE Interface :
SYSCONPM(SYSCONCM) Assy has SATA bus for HDD and PATA bus for DVD-R drive interface.
-
Primary Master SATA: HDD
-
Secondary Master PATA: DVD-R Drive
•
DISPLAY (VGA, DVI, TV input) BLOCK
Basically SOM support 2 kinds of display output. One is LVDS level for Plat panel display, and other is
analog RGB for CRT monitor.
To obtain advanced and stable quality image, SYSCONPM(SYSCONCM) Assy convert LVDS signal to
Digital Video Interface (DVI) and transport TMDS signal to main display of system.
•
ETHERNET BLOCK
SOM on the SYSCONPM(SYSCONCM) has one integrated Ethernet port : Intel 82562 10/100 Mbps
Fast Ethernet controller
•
SOM supply four USB 1.1/2.0 port. Each USB ports are used for the keyboard, BW digital printer,
USB port for usb memory stick, etc.
•
VCR INPUT
For Video play back, SYSCONPM(SYSCONCM) has Video Decoder device. It support NTSC/ PAL
mode both. It transfers encoded data to SOM through PCI bus.
-
Supports capture resolutions up to 768x576(Full PAL mode)
-
CCIR 656 Interface
-
S-Video & composite input interface
5-4-3-4
FPGA BLOCK
•
FEBC FPGA(FEBUS Control):
A major function of FEBC is that generate FEBUS to control scan sequence, access register on the
each other front end assy, and interface to DSP through EMIFB bus. Other roles are below
-
Generates a stable PGC curve for getting better image quality.
-
Gathers the diagnostic information: LV, HV, Probe temperature, Nest temperature.
-
Supervises the system safety
-
Manages the each ASSY information with IIC Bus: SYSCONPM(SYSCONCM), CL1TRX,
P3RLY(P2RL), ACWD (option) and Probes
-
Controls HV Voltage output level: Transfer the voltage reference data from DSP to APS/APS
Pro via IIC interface.
•
CPDI FPGA(CHACOM Processing Data Interface):
The major function of CPDI is that transfer mid processed data from CHACOM to DSP local process.
CPDI has 2EA 8x1024 Dual port as one scan line image data buffer. Address sequencer indicates to
DSP that buffered data is full one scan line. then DSP can transfer a scan line data to one's SDRAM.
For debugging, CPDI generate test pattern image data. It will be able to check CHACOM run normally.
5-4-3-5
CLOCK DISTRIBUTION BLOCK
Each operation clock is divided from 160MHz. Also ECL logic is used to remove clock skew for all clock
distribution.
Required clocks is following:
•
40MHz In-phase and 40MHz Quad-phase for ACWD, CL1TRX assy
•
40MHz In-phase for P3RLY assy
