C2K User’s Guide
4-12
Functional Blocks
NOTE:
The crossbar must map the UART_INT# signal to the INT0# interrupt to assert an inter-
rupt to the C8051 Controller.
Pin
Port 0
Port 1
Port 2
Port 3
7
6
5
4
3
2
1
0
Externally SRAM
An external 128kB SRAM is attached to the C8051 Controller by an 8-bit multiplexed A/D Bus
created from Port 2 and Port 3, and portions of Port 0 and Port 1. The SRAM_CS# signal on
Port 1 provides access to the SRAM. The RAM is organized as two 64kB pages. The IO1
Controller SRAM_A16 signal selects the page prior to access.
External UART
An external 16550-compatible UART is also attached to the C8051 Controller through the A/D
bus to provide the ICMB interface. The C8051 software implements the ICMB Bridge feature
described in ICMB 1.0. The external UART and a half-duplex RS-485 transceiver provide the
physical layer.
The UART_CS# signal on Port 1 provides access to the UART. The UART_INT# signal indicates
the UART has asserted an interrupt. The crossbar must map UART_INT# to the INT0# interrupt.
SPI-based EEPROM
An SPI-based 64kB EEPROM provides non-volatile storage for data records and event logs. The
EEPROM_CS# signal on Port 1 provides access to the EEPROM.
SPI-based I/O
Two SPI-based I/O controllers monitor and control signals as listed in Table 4-5 on page 4-13.
The IO1_CS# and IO2_CS# signals provide access to the I/O controllers. The I/O controller
perform two functions: provide sufficient I/O to support C8051 features, and hold the state of the
output signals (UART_RESET#, FPGA_INT#, and BRD_RST#) during a watchdog-initiated
C8051 Controller reset.
Table 4-4
C8051 external I/O ports pin assignments
RAM_WR#
RAM_CS#
A15
A7 / D7
RAM_RD#
UART_CS#
A14
A6 / D6
RAM_ALE
EEPROM_CS#
A13
A5 / D5
SCL
IO1_CS#
A12
A4 / D4
SDA
IO2_CS#
A11
A3 / D3
MOSI
UART_INT#
A10
A2 / D2
MISO
RX1
A9
A1 / D1
SCK
TX1
A8
A0 / D0
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