5-49
C2K User’s Guide
Resources
USART Line Control Register
The USART Line Control Register specifies the format of the asynchronous or bit-synchronous
data communication used and provides access to the baud-rate divisor registers.
5 - 4
TX_TRIG
0b00
Transmit FIFO Trigger Level—sets the Transmit FIFO buffer trigger
levels.
3
Not used
-
Not used
2
TX_CLR
0
Transmit FIFO Clear—clears the Transmit FIFO buffer. This bit is
self-clearing.
1 = clears Transmit FIFO buffer
1
RX_CLR
0
Receive FIFO Clear—clears the Receive FIFO buffer. This bit is
self-clearing.
1 = clears Receive FIFO buffer
0
EN
0
FIFO Enable—enables the FIFO buffers.
0 = disable FIFO buffers
1 = enable FIFO buffers
Address offset:
USAR0x3
Access:
Read-only
Bit(s)
Field
Default
Description
7
DLAB
0
Divisor Latch Access Bit—determines whether access is provided to
normal registers at offset 0x0 and 0x1 or divisor latch registers.
0 = normal registers
1 = divisor latch registers
6
BREAK
0
Break Control—enables the break control function which forces serial
data out to (0).
0 = disable break function
1 = enable break function
5
STICK_PAR
0
Stick Parity—enables stick parity, which transmits and checks parity as
a (0) for odd parity and a (1) for even parity.
0 = disable stick parity
1 = enable stick parity
Bit(s)
Field
Default
Description
16-byte FIFO –
64-byte FIFO –
0bXX = 1 byte
0b00 = 1 byte
0b01 = 16 bytes
0b10 = 56 bytes
0b11 = 64 bytes
256-byte FIFO –
1024-byte FIFO –
0b00 = 1 byte
0b00 = 1 byte
0b01 = 64 bytes
0b01 = 256 bytes
0b10 = 224 bytes
0b10 = 896 bytes
0b11 = 256 bytes
0b11 = 1024 bytes
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