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5-3

C2K User’s Guide

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5.1.4 Multi-Purpose Pins (MPP)

The MV64460 System Controller provides a 32-pin Multi-Purpose Pins (MPP) interface. Table
5-4 lists the MPP signal assignments.

Table 5-4

MV64460 System Controller MPP pin assignments

MPP

Assignment

MPP

Assignment

PCI1_GNT0 (PMC1)

PCI0_GNT0 (PMC0)

PCI1_REQ0 (PMC1)

PCI0_REQ0 (PMC0)

PCI1_GNT1 (PCI 6254)

WDOG_NMI

PCI1_REQ1 (PCI 6254)

WDOG_EXP

PCI1_GNT2 (PCI2050B)

RTC_INT

PCI1_REQ2 (PCI2050B)

TEMP_INT

PCI1_GNT3 (GD31244)

ETH_PHY_INT

PCI1_REQ3 (GD31244)

GPIO_INT

S0_TXD

FPGA_INT

S1_SCLK

TC_NT0

S1_TSCLK

TC_EN1

S1_RXD

USB_INT

S1_TXD

CNTR_INT

S0_SCLK

TC_NT2

S0_TSCLK

TC_EN3

S0_RXD

SATA_INT

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Summary of Contents for C2K

Page 1: ...l service in house repair center WE BUY USED EQUIPMENT Sell your excess underutilized and idle used equipment We also offer credit for buy backs and trade ins www artisantg com WeBuyEquipment REMOTE INSPECTION Remotely inspect equipment before purchasing with our interactive website at www instraview com LOOKING FOR MORE INFORMATION Visit us on the web at www artisantg com for more information on ...

Page 2: ...E Intelligent Platforms Publication No 70000524 800 Rev C Hardware Reference C2K 6U CPCI Single Board Computer Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 3: ...Document History Hardware Reference Document Number 70000524 800 Rev C September 30 2011 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 4: ... 4 3 PCI VIO Select P9 P12 2 2 2 4 4 COP_EN P10 2 3 2 4 5 C8051 Debug P11 2 3 2 4 6 Header Jumper Locations 2 3 2 5 Installation 2 3 2 5 1 C2K C style Installation 2 3 2 5 2 C2K N style Installation 2 4 2 6 U Boot Utility 2 7 2 6 1 Installation 2 7 2 6 2 Initialization 2 7 2 6 3 Commands 2 7 2 6 4 Information Commands 2 9 2 6 5 Memory Commands 2 10 2 6 6 Flash Memory Commands 2 11 2 6 7 Execution ...

Page 5: ... 4 4 6 SMBus 4 4 4 7 Gigabit Ethernet 4 4 4 8 Serial I O 4 5 4 8 1 Serial RS 232 422 Ports COM1 COM2 4 5 4 8 2 Serial RS 232 422 Ports COM3 COM4 4 5 4 8 3 Serial RS 422 485 Ports COM5 COM8 4 5 4 9 USB Ports 4 6 4 10 General Purpose I O 4 6 4 11 Serial ATA I O 4 6 4 12 Counter Timers 4 7 4 12 1 Watchdog Timer 4 7 4 13 FPGA 4 8 4 13 1 System Management Interrupt 4 8 4 14 RTC 4 9 4 15 CompactPCI Back...

Page 6: ... Module C2K TM 6 1 Overview 6 1 6 2 Physical Description 6 2 6 3 Block Diagram 6 3 6 4 Connector Pin Assignments 6 4 6 4 1 CompactPCI Connectors 6 4 6 4 2 Ethernet Connectors J6 J7 and J8 6 7 6 4 3 Serial ATA Connectors P19 P20 6 7 6 4 4 USB Connectors J9 J10 and J11 6 8 6 4 5 Serial RS 232 Connectors COM1 COM2 P15 P16 6 8 6 4 6 Serial RS 422 485 COM1 COM8 P1 P8 6 9 6 4 7 Serial RS 232 COM3 COM4 P...

Page 7: ...5 Front panel LEDs 3 16 Figure 4 1 Watchdog timer circuitry 4 8 Figure 4 2 SMI processing 4 9 Figure 4 3 Interrupt circuitry 4 16 Figure 4 4 JTAG circuitry 4 18 Figure 5 1 C2K component locations primary side 5 54 Figure 5 2 C2K component locations secondary side 5 55 Figure 6 1 C2K TM block diagram 6 3 Figure 6 2 Ethernet RJ 45 connector pinout 6 7 Figure 6 3 SATA connector pinout 6 7 Figure 6 4 ...

Page 8: ...tor J8 pin assignment 3 15 Table 3 13 Serial I O COM port termination header P15 pin assignments 3 15 Table 4 1 Gigabit Ethernet on board indicator LEDs 4 4 Table 4 2 USB on board indicator LEDs 4 6 Table 4 3 SATA on board activity indicator LEDs 4 7 Table 4 4 C8051 external I O ports pin assignments 4 12 Table 4 5 I O controller pin assignments 4 13 Table 5 1 PCI local bus configuration 5 1 Table...

Page 9: ...onnectors P19 P20 pin assignments 6 7 Table 6 6 USB connectors J9 J10 and J11 pin assignments 6 8 Table 6 7 COM1 P15 and COM2 P16 pin assignments 6 8 Table 6 8 COM1 P1 through COM8 P8 pin assignments 6 9 Table 6 9 COM3 P9 and COM4 P10 pin assignments 6 9 Table 6 10 BATT header P13 pin assignment 6 9 Table 6 11 ICMB interface header P17 pin assignment 6 10 Table 6 12 GPIO on board header P2 pin ass...

Page 10: ... of 167MHz DDR SDRAM with ECC PLX PCI 6254 PCI to PCI Interface for CPCI backplane Two selectable 115kbps RS 232 or 2Mbps source synchronous RS 422 ports available to the backplane connectors Six additional 460kbps source synchronous RS 422 485 ports available to the backplane connectors Two 10 100 1000T Ethernet ports available to the backplane connector J3 wired per PICMG 2 16 One 10 100 1000T E...

Page 11: ...P11 on board 2 x 32 pin header PMC1 I O P12 on board 2 x 32 pin header Reset switch S1 rear panel manual hardware reset micro switch SATA1 P19 rear panel connector SATA2 P20 rear panel connector Serial I O COM1 COM2 RS 232 P15 P16 rear panel DB9 connectors Serial I O COM3 COM4 RS 232 P10 P9 on board 2 x 5 pin headers Serial I O COM1 COM4 RS 422 P1 P4 on board 2 x 5 pin headers Serial I O COM5 COM8...

Page 12: ...TBD TBD Inrush 2 0A 120µs 2 0A 120µs BATT 10µA Total 42W Measured at VxWorks prompt Temperature operating C style 0 C to 70 C ambient N style 40 C to 85 C Temperature storage C style 40 C to 85 C N style 55 C to 105 C Relative Humidity 40 C non condensing C style 5 95 40 C N style 5 95 40 C Shock half sine C style 20g peak 6ms 3 axes up down 3 hits direction N style 40g peak 11ms 3 axes up down 3 ...

Page 13: ...e 1 1 C2K GPIO DC Electrical Characteristics Symbol Parameter Min Max Unit GPIO Igpio GPIO source current 12 mA lgpio GPIO sink current 12 mA Vih GPIO input high voltage 2 0 5 5 V Vil GPIO input low voltage 0 8 V Voh GPIO output high voltage 2 4 V Vol GPIO output low voltage 0 4 Unit Supply Current and Power Dissipation Ppmc Maximum Power available to each PMC site sum of 5 0V and 3 3V powers 7 5 ...

Page 14: ...J12 PMC0 J13 J14 cPCI_J5 PCI2050B PCI PCI Bridge GD31244 SATA Controller ISP 1563 USB 2 0 Controller cPCI bus to JTAG Scan Chain JTAG_J7 RGMII0 RGMII1 RGMII2 ETH0 ETH1 ETH2 J21 J22 PMC1 J23 J24 PCI Bus 0 SATA1 SATA2 Mem Bus 167MHz PCI Bus 0 cPCI_J3 64 bit 33 66MHz 64 bit 33 66MHz USB1 USB2 USB3 or 133MHz PCI X 64 bit 33 66MHz FPGA Device Bus RTC Hot Swap Ctlr 8051 IPMC PCI Bus 1 Figure 1 1 C2K Blo...

Page 15: ... RS 485 I F RS 485 I F RS 485 I F cPCI_J4 Device Bus RS 422 I F RS 232 I F RS 422 I F GPIO0 GPIO1 GPIO2 GPIO3 COM3 COM4 COM5 COM6 COM7 COM8 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 cPCI_J5 MPSC 1 6 C2K User s Guide Introduction Figure 1 2 C2K Block diagram b Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 16: ...nc Doc no MV S101286 00 01 Rev B July 2004 PCI 6254 HB6 Dual Mode Universal PCI to PCI Bridge DataBook PLX Technology Inc Version 2 0 May 2003 PCI2050B PCI to PCI Data Manual Texas Instruments Incorporated SCPS076E November 2004 ISP1563 Hi Speed USB PCI Host Controller Product Data Philips Semiconductors Doc ument Order Number 9397 750 14244 Rev 01 July 2005 Intel 31244 PCI X to Serial ATA Control...

Page 17: ...E Std 1101 1 1991 Equipment Practice December 1996 IEEE Std 1149 1 1990 IEEE Standard Test Access Port and Boundary Scan Architec ture June 1993 IEEE Std 1284 2000 IEEE Standard Signaling Method for a Bidirectional Parallel Peripheral Interface for Personal Computers September 2000 IEEE1386 2001 IEEE Standard for a Common Mezzanine Card CMC Family June 2001 IEEE1386 1 2001 IEEE Standard Physical a...

Page 18: ...Cooled Euroboards August 2002 VITA Standards Organization VITA 32 2002 Processor PMC Standard for Processor PCI Mezzanine Cards September 2002 VITA Standards Organization VITA 39 2003 PCIX Auxiliary Standard for PMCs and Processor PMCs August 2003 Universal Serial Bus Specification Revision 2 0 April 2000 1 PICMG Specifications are available to PICMG members only GEIP is not authorized to distribu...

Page 19: ...are needed to install and operate the C2K C style CompactPCI compatible chassis or N style CompactPCI compatible chassis E S D Caution Always use proper Electrostatic Discharge ESD protection when han dling printed circuit boards to avoid seriously damaging components Product han dlers must always be properly grounded Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www ar...

Page 20: ...sses PMC sites at 3 3V or 5V P12 controls the VIO for PCI Bus 0 PMC0 and P9 controls VIO for PCI Bus 1 PMC1 If a jumper is installed on P6 the FLASH_WP signal is asserted preventing writes to the flash ROM If a jumper is not installed on P6 the FLASH_WP signal is de asserted allowing writes the flash ROM If a jumper is installed on the EM_BOOTSEL header P7 the GEIP firmware will boot from the GEIP...

Page 21: ...nnector is bused or routed in accordance with the CompactPCI H110 specification The C2K is equipped with an IEC key to prevent such installation but if the backplane is not keyed installation is still possible Caution Do not attempt to install the C2K in a Fabric slot of a PICMG 2 16 Packet Switching Backplane The C2K is equipped with an IEC key to prevent such installation but if the backplane is...

Page 22: ...o the chassis 8 Apply power to the chassis NOTE C2K can be installed in a system controller or peripheral slot If the C2K is not installed in a system slot a system controller card must be installed in the system slot to supply a PCI ref erence clock to C2K 2 5 2 C2K N style Installation 1 Remove the C2K SBC from the static safe envelope see E S D Caution on page 2 1 2 Install optional PMC module ...

Page 23: ...PMC Module PMC Module 2 5 C2K User s Guide Installation Figure 2 1 C2K C style with PMC modules installed Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 24: ...PMC Module PMC Module C2K User s Guide 2 6 Installation Figure 2 2 C2K N style with PMC modules installed Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 25: ...alized during production and testing 2 6 3 Commands The following is a summary of commands the U Boot utility uses for the C2K alias for help autoscr runs script from memory base prints or sets address offset bdinfo prints Board Info structure boot boots default e g run bootcmd bootd boots default e g run bootcmd bootelf boots from an ELF image in memory bootm boots application image from memory b...

Page 26: ... memory fill nm modifies memory constant address ping sends ICMP ECHO REQUEST to network host printenv prints environment variables protect enables or disables flash write protect rarpboot boots image from network using RARP TFRP protocol reset resets the CPU run runs commands in an environment variable saveenv saves environment variables to a persistent storage setenv sets environment variables s...

Page 27: ... flinfo N prints information for flash memory bank N iminfo addr addr prints header information for application image starting at address addr in memory this includes ver ification of the image contents magic number header and payload checksums imls prints information about all images found at sector boundaries in flash help command shows help information for command prints online help for the mon...

Page 28: ...s offset for memory commands to off crc32 address count addr calculates CRC32 checksum save at addr cmp b w l adder1 addr2 count compares memory cp b w l source target count copies memory md b w l address of objects displays memory mm b w l address modifies memory automatically increments address mtest start end pattern performs simple RAM read write test Artisan Technology Group Quality Instrumen...

Page 29: ...orms loop on a set of addresses erase start end erases flash from addr start to addr end erase N SF SL erases sectors SF SL in flash bank N erase bank N erases flash bank N erase all erases all flash banks protect on start end protects flash from addr start to addr end protect on N SD SL protects sectors SF SL in flash bank N protect on bank N protects flash bank N protect on start all protects al...

Page 30: ...sh bank N protect on bank N enables writes to flash bank N protect on start all enables writes to all flash banks bootm addr arg boots application image stored in memory passing argument arg when booting a Linux kernel arg can be the address of an initrd image go addr arg starts application at address addr passing arg as arguments bootp loadAddress bootfilename bootelf address loads address of ELF...

Page 31: ...ud loads off baud loads S Record fileover serial line with offset off and baud rate baud rarpboot loadAddress bootfilename prints values of all environment variables tftpboot loadAddress bootfilename printenv prints values of all environment variables printenv name print value of environment variable end saveenv no help available setenv name value sets environment variable name to value setenv nam...

Page 32: ...in the environment variable s var bootd no help available ping pingaddress date MMDDhhmm CC YY ss date reset without arguments prints data and time with arguments sets the system date and time with reset argument resets the Real Time Clock reset no help available sleep N delays execution for N seconds N is _decimal_ version no help available Artisan Technology Group Quality Instrumentation Guarant...

Page 33: ...two cutouts to accommodate installed PMC module front panels USB Connector USB4 Type A USB connector J8 Recessed Reset provides access to a recessed reset micro switch for performing a manual hardware reset TIP A straightened paper clip can be used to access the recessed reset button Figure 3 1 Front panels a C style b N style b a HS HS PWR PBIT USER IPMC PWR PBIT USER IPMC RESET USB USB PMC1 PMC1...

Page 34: ...12 P13 P10 J6 J21 J24 J12 J13 J22 J23 J11 J14 J3 J2 J1 J4 J5 Drawing not to scale Figure 3 2 Connector locations C style NOTE The front panel USB connector J8 is only available on C style versions of the C2K Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 35: ...12 P13 P10 J6 J21 J24 J12 J13 J22 J23 J11 J14 J3 J2 J1 J4 J5 3 3 C2K User s Guide Interfaces Figure 3 3 Connector locations N style Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 36: ...r Table 3 1 cPCI connector J1 pin assignments 5V REQ64 ENUM 3 3V 5V GND AD1 5V VIO AD0 ACK64 GND 3 3V AD4 AD3 5V AD2 GND AD7 GND 3 3V AD6 AD5 GND 3 3V AD9 AD8 M66EN C BE0 GND AD12 GND VIO AD11 AD10 GND 3 3V AD15 AD14 GND AD13 GND SERR GND 3 3V PAR C BE1 GND 3 3V IPMB_SCL IPMB_SDA GND PERR GND DEVSEL GND VIO STOP LOCK GND 3 3V FRAME IRDY BD_SEL TRDY GND AD18 AD17 AD16 GND C BE2 GND AD21 GND 3 3V AD...

Page 37: ...16 BRSVP2B16 DEG GND BRSVP2E16 GND BRSVP2A15 GND FAL REQ5 GNT5 GND AD35 AD34 AD33 GND AD32 GND AD38 GND VIO AD37 AD36 GND AD42 AD41 AD40 GND AD39 GND AD45 GND VIO AD44 AD43 GND AD49 AD48 AD47 GND AD46 GND AD52 GND VIO AD51 AD50 GND AD56 AD55 AD54 GND AD53 GND AD59 GND VIO AD58 AD57 GND AD63 AD62 AD61 GND AD60 GND C BE5 CPCI_64EN VIO C BE4 PAR64 GND VI O BRSVP2B4 C BE7 GND C BE6 GND CLK4 GND GNT3 R...

Page 38: ..._20 PMC0_19 PMC0_18 PMC0_17 PMC0_16 GND PMC0_25 PMC0_24 PMC0_23 PMC0_22 PMC0_21 GND PMC0_30 PMC0_29 PMC0_28 PMC0_27 PMC0_26 GND PMC0_35 PMC0_34 PMC0_33 PMC0_32 PMC0_31 GND PMC0_40 PMC0_39 PMC0_38 PMC0_37 PMC0_36 GND PMC0_45 PMC0_44 PMC0_43 PMC0_42 PMC0_41 GND PMC0_50 PMC0_49 PMC0_48 PMC0_47 PMC0_46 GND PMC0_55 PMC0_54 PMC0_53 PMC0_52 PMC0_51 GND PMC0_60 PMC0_59 PMC0_58 PMC0_57 PMC0_56 GND PMC0_VIO...

Page 39: ...2_RX n c COM1_TXD COM2_TXD GND COM8_TXD COM4_232_TX n c COM1_TXD COM2_TXD GND COM3_RXC COM4_RXC COM5_RXC COM6_RXC COM7_RXC GND COM3_RXC COM4_RXC COM5_RXC COM6_RXC COM7_RXC GND COM3_TXC COM4_TXC COM5_TXC COM6_TXC COM7_TXC GND COM3_TXC COM4_TXC COM5_TXC COM6_TXC COM7_TXC GND COM3_RXD COM4_RXD COM5_RXD COM6_RXD COM7_RXD GND COM3_RXD COM4_RXD COM5_RXD COM6_RXD COM7_RXD GND COM3_TXD COM4_TXD COM5_TXD C...

Page 40: ...5 GPIO_10 GND SATA1_TX SATA2_TX USB1_PWR USB2_PWR USB3_PWR GND SATA1_TX SATA2_TX USB1_D USB2_D USB3_D GND COM1_232_RX COM2_232_RX USB1_D USB2_D USB3_D GND COM1_232_TX COM2_232_TX USB1_GND USB2_GND USB3_GND GND NOTES a BATT External battery input The 3 3V supply from the system is used as a battery backup for the NVRAM and RTC devices b BIT_PASS Built In Test BIT Status output At power up or after ...

Page 41: ...output This signal is asserted when a processor failure watchdog timer expire has been detected l ROM_WP Flash write protect input When asserted active low the flash memory is write pro tected This signal is pulled up enabling writes to flash memory for backplanes that do not support a write protect feature m Serial ATA 1 5Gb s serial ATA SATA1 SATA2 n Serial I O These ports are configured as RS 2...

Page 42: ...USMODE4 PCI0_REQ0 5V PME GND VIO PCI0_AD31 PCI0_AD30 PCI0_AD29 PCI0_AD28 PCI0_AD27 GND PCI0_AD26 PCI0_AD25 GND PCI0_AD24 3 3V GND PCI0_C BE3 PCI0_IDSEL PCI0_AD23 PCI0_AD22 PCI0_AD21 3 3V PCI0_AD20 PCI0_AD19 5V PCI0_AD18 GND VIO PCI0_AD17 PCI0_AD16 PCI0_C BE2 PCI0_FRAME GND GND rsvd GND PCI0_IRDY PCI0_TRDY 3 3V PCI0_DEVSEL 5V GND PCI0_STOP PCIXCAP PMC0_LOCK PCI0_PERR GND rsvd rsvd 3 3V PCI0_SERR PC...

Page 43: ...64 PMC0_9 PMC0_10 PCI0_AD63 PCI0_AD62 PMC0_11 PMC0_12 PCI0_AD61 GND PMC0_13 PMC0_14 GND PCI0_AD60 PMC0_15 PMC0_16 PCI0_AD59 PCI0_AD58 PMC0_17 PMC0_18 PCI0_AD57 GND PMC0_19 PMC0_20 VIO PCI0_AD56 PMC0_21 PMC0_22 PCI0_AD55 PCI0_AD54 PMC0_23 PMC0_24 PCI0_AD53 GND PMC0_25 PMC0_26 GND PCI0_AD52 PMC0_27 PMC0_28 PCI0_AD51 PCI0_AD50 PMC0_29 PIO0_30 PCI0_AD49 GND PMC0_31 PMC0_32 GND PCI0_AD48 PMC0_33 PMC0_3...

Page 44: ...0 5V PME GND VIO PCI1_AD31 PCI1_AD30 PCI1_AD29 PCI1_AD28 PCI1_AD27 GND PCI1_AD26 PCI1_AD25 GND PCI1_AD24 3 3V GND PCI1_C BE3 PCI1_IDSEL PCI1_AD23 PCI1_AD22 PCI1_AD21 3 3V PCI1_AD20 PCI1_AD19 5V PCI1_AD18 GND VIO PCI1_AD17 PCI1_AD16 PCI1_C BE2 PCI1_FRAME GND GND rsvd GND PCI1_IRDY PCI1_TRDY 3 3V PCI1_DEVSEL 5V GND PCI1_STOP GND PMC1_LOCK PCI1_PERR GND rsvd rsvd 3 3V PCI1_SERR PCI1_PAR GND PCI0_C BE...

Page 45: ...PMC1_9 PMC1_10 PCI1_AD63 PCI1_AD62 PMC1_11 PMC1_12 PCI1_AD61 GND PMC1_13 PMC1_14 GND PCI1_AD60 PMC1_15 PMC1_16 PCI1_AD59 PCI1_AD58 PMC1_17 PMC1_18 PCI1_AD57 GND PMC1_19 PMC1_20 VIO PCI1_AD56 PMC1_21 PMC1_22 PCI1_AD55 PCI1_AD54 PMC1_23 PMC1_24 PCI1_AD53 GND PMC1_25 PMC1_26 GND PCI1_AD52 PMC1_27 PMC1_28 PCI1_AD51 PCI1_AD50 PMC1_29 PMC1_30 PCI1_AD49 GND PMC1_31 PMC1_32 GND PCI1_AD48 PMC1_33 PMC1_34 P...

Page 46: ...ignments The C2K includes an onboard 2 x 5 socket JTAG header J7 for FPGA programming and JTAG Boundary Scan Chain Table 3 10 COP Port J20 pin assignments COP_TDO COP_QACK COP_TDI COP_TRST RUN_STOP VDD_SENSE COP_TCK COP_CKSTP_IN COP_TMS n c COP_SRESET GND COP_HRESET KEY CKSTP_OUT GND n c n c n c n c This pin may be pulled to ground by the COP adapter cable to automatically enable the COP port inst...

Page 47: ...rts Line termination for a port is enabled when a jumper is installed across the cor responding pins shown in Table 3 13 NOTE Receive termination must always be enabled when a port is configured for RS 422 opera tion Pins Assignment 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Table 3 12 Front panel Ethernet connector J8 pin assignment Pin Assignment 1 USB4_VCC 2 USB4_D 3 USB4_D 4 USB4_GND Table 3 13 Se...

Page 48: ...are out of specification PBIT Green Illuminates when the processor has completed its built in test diagnostics De illumi nates if the built in test diagnostic tests fail either during the initial power up or reset diagnostics or during continual background diagnostics User Yellow User defined Controlled through MV64460 multi purpose pin 8051 Yellow Controlled by the C8051 microcontroller Hot Swap ...

Page 49: ... 167MHz Memory Bus System memory includes full Error Checking and Correction ECC protection with one bit error detect and correct multiple bit error detect and report functions 4 3 Flash Memory The C2K includes 64 512MB of flash memory configured in one 32 bit bank of 8 bit Spansion MirrorBit flash ROM devices The flash devices are located on the 32 bit asynchronous parallel Device Bus mastered by...

Page 50: ...nal C2K TM companion board that provides a ROM_WP header jumper for asserting the backplane ROM_WP signal On board Write Protect The C2K provides an on board FLASH_WP header jumper site P6 for manually asserting the ROM_WP signal to enable global flash write protection see FLASH_WP P6 on page 2 2 If the ROM_WP signal is asserted active low all write erase functions are disabled If the ROM_WP signa...

Page 51: ... page 2 2 or an external jumper see Note b below attached to a backplane connector pin cPCI_J5 B9 4 4 PCI Busses The C2K includes two PCI busses controlled by the MV64460 System Controller s PCI Bus interface PCI Bus 0 is configured for 64 bit 33 66MHz PCI or 133MHz PCI X operation and is dedicated to the PMC0 site PCI Bus 1 is configured for 64 bit 33 66MHz PCI 2 2 and is shared by PMC1 site the ...

Page 52: ...t Media Access Controllers MACs The VSC8244 PHY provides the physical interfaces The C2K provides nine on board LEDs to monitor link activity and data transfer speeds for the three Ethernet ports as described in Table 4 1 Table 4 1 Gigabit Ethernet on board indicator LEDs LED Description LED Indication D1 ETH0 Link Activity Link Activity Indicates a valid link has been establish blinking indi cate...

Page 53: ...ured as RS 232 they can operate at transfer rates up to 115kb s and are routed to the backplane through cPCI_J4 When either or both of these ports are configured as RS 422 they can operate at rates up to 230kb s in asynchronous mode or up to 460kb s in source synchronous mode and are routed to the backplane through cPCI_J4 These ports are configured RS 232 422 through the COM3_TYPE bit 7 and COM4_...

Page 54: ... control and interrupt masking see GPIO Registers on page 5 16 Each GPIO line can be configured as a input or output The inputs can be configured as inverted or non inverted and the outputs can be configured as TTL or open drain Each line can generate an interrupt that can be masked through the FPGA Interrupt Mask Register Each interrupt can be configured as edge triggered or level triggered The G...

Page 55: ...z TCLK reference It has a maximum interval duration of approximately 32 seconds The MV64460 watchdog circuitry can output the WDOG_NMI and WDOG_EXP signals mapped to the MV64460 MPP pins If the watchdog counter reaches the value programmed in the Watchdog Value Register NMI_VAL field the watchdog timer asserts the WDOG_NMI output to the FPGA which generates a SMI to interrupt the processor If the ...

Page 56: ...ment USARTs Device Bus management SMI 4 13 1 System Management Interrupt The FPGA can generate the System Management Interrupt SMI input to the processor The SMI is a level sensitive processor input which the FPGA asserts if one or more of the following interrupt sources are asserted Backplane NMI maskable Backplane DEG maskable Backplane FAL maskable Watchdog NMI maskable Each interrupt source is...

Page 57: ...tem controller and peripheral slot applications is selected in hardware based on slot address information in the backplane The PCI 6254 supports either 33MHz and 66MHz bus clocks on the backplane using 32 bit or 64 bit data transfers and provides bus arbitration logic support for seven peripheral slots The PCI 6254 also supports 33 66MHz operation on the internal primary side PCI bus interface NOT...

Page 58: ...d by the SYSEN signal from the backplane cPCI_J2 C2 SYSEN is asserted when the C2K is installed in a system slot and de asserted when the C2K is installed in a peripheral slot NOTE The cPCI 64EN backplane signal is connected to the PCI 6254 64EN input pin The state of 64EN can be determined by an internal PCI 6254 register If the 64EN indicates 32 bit only no 64 bit accesses should be allowed to t...

Page 59: ...pport and monitors ejector handle status and Geographic Address inputs It also contributes to the software control of the blue front panel Hot Swap LED 4 16 4 C8051 Microcontroller The IPMI Controller consists of the C8051F127 Microcontroller C8051 support logic and GEIP s IPMI software The C8051 Microcontroller includes the following features 128kbytes of internal flash storage for program code 8...

Page 60: ...ART_CS signal on Port 1 provides access to the UART The UART_INT signal indicates the UART has asserted an interrupt The crossbar must map UART_INT to the INT0 interrupt SPI based EEPROM An SPI based 64kB EEPROM provides non volatile storage for data records and event logs The EEPROM_CS signal on Port 1 provides access to the EEPROM SPI based I O Two SPI based I O controllers monitor and control s...

Page 61: ...ICMB_ARB_SEL PGOOD_1 5V 6 SYSEN PGOOD_2 5V 1 1V 5 BDSEL HSC_PWRGOOD 4 GA4 FPGA_INT 3 GA3 BRD_RESET 2 GA2 YELLOW_LED 1 GA1 UART_RST 0 GA0 SMB_ALERT NOTES a The PCI_PRESENT input does not directly affect the C2K operation The Hot Swap function operates as normal whether the backplane PCI_PRESENT signal is asserted or not b The ALERT input is an optional signal used to support legacy IPMI devices Thi...

Page 62: ...Vaux is not supported Reserved pins are not connected Reset signals from each PMC site are isolated from the C2K such that the C2K can drive the PMC reset but the PMC reset will not be acknowledged by the C2K This prevents the C2K from being reset when an installed PMC module initiates a reset 4 17 1 PMC0 Site Features PMC0 is located on dedicated PCI Bus 0 connected to the MV64460 System Controll...

Page 63: ...tes cannot exceed 15W 4 18 Temperature Sensor The C2K includes a MAX6658 Dual Channel Temperature Sensor that monitors the MPC7448 processor temperature through an on die thermal diode and board temperature with an on chip sensor The Temperature Sensor is attached to the MV64460 Bridge chip through the I2C SMBus at address 0x4C Boot code must program the temperature sensor to generate an over temp...

Page 64: ...upt Controller This causes the Interrupt Controller to assert the CPU_INT interrupt to the MCP7447A processor Figure 4 3 Interrupt circuitry 4 20 EEPROMS The C2K provides the following programmable configuration serial EEPROMS located on the IIC SMBus EEPROM Type Address Function Board Configuration AT24C64AN 64kb 0x50 Provides storage for product configuration data such as assem bly serial number...

Page 65: ...n P11 The C8051 Isolation header jumper P11 isolates the C8051 Microcontroller from the JTAG Boundary Scan Chain for software debugging as shown in Figure 4 4 on page 4 18 When a jumper is installed on header P11 the C8051 Controller is isolated from the JTAG Scan chain see C8051 Debug P11 on page 2 3 When a jumper is not installed all JTAG equipped devices on the board are included in the JTAG ch...

Page 66: ...B PCI PCI Bridge GD31244_TDO PCI 6254_TDO PCI2050B_TDO PMC0_TDI PMC0_TDO PMC1_TDI PMC1_TDO PMC0 PMC1 GD31244_TDI PCI 6254_TDI PCI2050B_TDI A B Y P11 MPC7448 Processor MV64460 System Controller COP_TDI COP_TDO 3 1 7447A_TDO 7447A_TDI P10 CORE_TDI 64460_TDO 64460_TDI 7447A_TDO Voltage shifting buffers A3 B3 C3 7447A_TDI COP_J6 C2K User s Guide 4 18 Functional Blocks Figure 4 4 JTAG circuitry Artisan...

Page 67: ...so connects to PMC1 site the USB 2 0 Controller through the PCI2050B PCI PCI Bridge and the GD31244 SATA Host Controller Table 5 1 summarizes the C2K PCI local bus configurations The MV64460 System Controller provides arbitration for both local busses so its interfaces do not require an arbitration number Table 5 1 PCI local bus configuration PCI Bus Arbitration No IDSEL Device 0 AD16 MV64460 PCI ...

Page 68: ...ces and default address ranges set by the MV64460 following power up or hard reset Addressing for these devices is according to MV64460 instructions for interfacing 8 bit 16 bit and 32 bit devices NOTE MV64460 default values may be redefined in U Boot boot loader utility Bank Device Access Size Default Address Range Boot 32 bit 8MB 0xFF80_0000 to 0xFFFF_FFFF 3 2 8 bit 64kB 0xD811_0000 to 0xD811_FF...

Page 69: ... PMC0 1 PCI1_REQ0 PMC1 17 PCI0_REQ0 PMC0 2 PCI1_GNT1 PCI 6254 18 WDOG_NMI 3 PCI1_REQ1 PCI 6254 19 WDOG_EXP 4 PCI1_GNT2 PCI2050B 20 RTC_INT 5 PCI1_REQ2 PCI2050B 21 TEMP_INT 6 PCI1_GNT3 GD31244 22 ETH_PHY_INT 7 PCI1_REQ3 GD31244 23 GPIO_INT 8 S0_TXD 24 FPGA_INT 9 S1_SCLK 25 TC_NT0 10 S1_TSCLK 26 TC_EN1 11 S1_RXD 27 USB_INT 12 S1_TXD 28 CNTR_INT 13 S0_SCLK 29 TC_NT2 14 S0_TSCLK 30 TC_EN3 15 S0_RXD 31...

Page 70: ...s required by the MV64460 Table 5 5 FPGA memory map 16 bit Chip Select Address Description Main 0x0 Revision 0x8 Status 0x10 Control 0x12 Reset Control Interrupt 0x20 Interrupt Mask Reg 1 0x22 Unused 0x24 Interrupt Summary Status 1 0x26 Unused 0x28 SMI Mask 0x2A SMI Status GPIO 0x30 GPIO Direction 0x32 GPIO Polarity 0x34 GPIO Output Type 0x36 GPIO Interrupt Type 0x38 GPIO De Bounce Enable 0x40 GPI...

Page 71: ...ter 3 Current Value Low 0x210 Counter 4 Current Value High 0x212 Counter 4 Current Value Low 0x214 Counter 5 Current Value High 0x216 Counter 5 Current Value Low 0x218 Counter 6 Current Value High 0x21A Counter 6 Current Value Low 0x21C Counter 7 Current Value High 0x21E Counter 7 Current Value Low 0x220 Counter 8 Current Value High 0x222 Counter 8 Current Value Low 0x224 Counter 9 Current Value H...

Page 72: ...8 Counter 6 Preload Value High 0x25A Counter 6 Preload Value Low 0x25C Counter 7 Preload Value High 0x25E Counter 7 Preload Value Low 0x260 Counter 8 Preload Value High 0x262 Counter 8 Preload Value Low 0x264 Counter 9 Preload Value High 0x266 Counter 9 Preload Value Low 0x268 Counter 10 Preload Value High 0x26A Counter 10 Preload Value Low 0x26C Counter 11 Preload Value High 0x26E Counter 11 Prel...

Page 73: ...Bits Field Default Description 15 to 8 0x01 7 to 0 0x01 Table 5 6 FPGA memory map 8 bit Chip Select Address Description USART 0x00 0x07 USART 0 0x10 0x17 USART 1 0x20 0x27 USART 2 0x30 0x37 USART 3 0x40 0x47 USART 4 0x50 0x57 USART 5 0x60 0x67 Unused 0x70 0x77 Unused 0x80 0x86 UART 8 dedicated to C8051 Table 5 7 Main registers Offset Register Description 0x0 FPGA Revision Provides FPGA firmware re...

Page 74: ... that the PRST or PCI_RST signal from the cPCI backplane initiated the last board reset 0 other cause initiated last board reset 1 PRST or PCI_RST signal initiated last board reset 11 SYS_SLOT R CPCI System Slot status indicates whether the C2K is installed in a system or peripheral slot 0 C2K installed in peripheral slot 1 C2K installed in system slot 10 PCI_PRESENT R cPCI Bus Present indicates t...

Page 75: ...nt Address offset 0x10 Access Read write Bits Field Default Description 15 OVR_TEMP_RST_EN 0 Over Temperature Reset Enable enables a board reset by the Temperature Sensor over temperature reset output 0 reset disabled 1 reset enabled NOTE The OVERT_RST_ENBL bit is only reset by a power up sequence not by other resets 14 YELLOW_LED_EN 0 Yellow LED Enable controls yellow front panel LED 0 LED off 1 ...

Page 76: ...otect asserts write protection to the emergency boot code area of Flash ROM upper 8MB of Flash Bank 0 0 do not assert boot write protection 1 assert boot write protection Indicates bit only resets to default value on power up and is not affected by a hard reset event Address offset 0x12 Access Read write Bits Field Default Description 15 6 Not used Not used 5 PMC1_RESET 0 PMC1 Reset Control 0 rese...

Page 77: ...the CPCI_BRG_P_INT signal is or ed with the PMC1 INTA signal When the board is not in the system slot the CPCI INTA signal is or ed with the PMC1 INTA signal 0 enable interrupt 1 disable mask interrupt 14 PMC1_CPCI_INTB_MSK Xx7 PMC1 INTB Mask blocks masks INTB from the PMC module installed on PMC1 Each bit indicates a logic or of the PMC and CPCI interrupt When the board is not in the system contr...

Page 78: ...ART_INT_MSK 1 8051 UART Interrupt Mask blocks masks the 8051 UART inter rupt 0 enable interrupt 1 disable mask interrupt 5 USART5_INT_MSK 1 USART5 INT Mask blocks masks the USART interrupt 0 enable interrupt 1 disable mask interrupt 4 USART4_INT_MSK 1 USART4 INT Mask blocks masks the USART interrupt 0 enable interrupt 1 disable mask interrupt 3 USART3_INT_MSK 1 USART3 INT Mask blocks masks the USA...

Page 79: ... installed on PMC1 Each bit indi cates a logic or of the PMC and CPCI interrupt When the board is not in the system controller slot the CPCI inter rupts are disabled 0 interrupt is de asserted 1 interrupt is asserted 12 PMC1_CPCI_INTD_STAT PMC1 CPCI INTD Status indicates the status of INTD from a PMC module installed on PMC1 Each bit indi cates a logic or of the PMC and CPCI interrupt When the boa...

Page 80: ...e USART Port 3 interrupt 0 interrupt is de asserted 1 interrupt is asserted 2 USART_INT2_STAT USART INT2 Status indicates the status of the USART Port 2 interrupt 0 interrupt is de asserted 1 interrupt is asserted 1 USART_INT1_STAT USART INT1 Status indicates the status of the USART Port 1 interrupt 0 interrupt is de asserted 1 interrupt is asserted 0 USART_INT0_STAT USART INT0 Status indicates th...

Page 81: ...e Bits Field Default Description 15 to 4 Not used Not used 3 DEG_STAT 1 DEG signal Status indicates the backplane DEG sig nal status 0 DEG signal is de asserted 1 DEG signal is asserted 2 FAL_STAT 1 FAL signal Status indicates the backplane FAL signal status 0 FAL signal is de asserted 1 FAL signal is asserted 1 WDOG_NMI_STAT 1 Watchdog NMI Status indicates the MV64460 Watch dog NMI signal status ...

Page 82: ...terrupt input the FPGA interrupt output passes through the MV64460 interrupt logic The selected logic polarity for GPIO inputs affects the value read in the GPIO Data Register and affects which logic level will cause an interrupt assertion The regis ters default bit values occur after a power up reset Table 5 9 lists the GPIO registers Table 5 9 GPIO registers Offset Register Description 0x30 GPIO...

Page 83: ...es the circuit direction i e input or output for the GPIO11 line 0 input 1 output 10 GPIO10_DIR 0 GPIO10 Direction enables the circuit direction i e input or output for the GPIO10 line 0 input 1 output 9 GPIO9_DIR 0 GPIO9 Direction enables the circuit direction i e input or output for the GPIO9 line 0 input 1 output 8 GPIO8_DIR 0 GPIO8 Direction enables the circuit direction i e input or output fo...

Page 84: ...GPIO2_DIR 0 GPIO2 Direction enables the circuit direction i e input or output for the GPIO2 line 0 input 1 output 1 GPIO1_DIR 0 GPIO1 Direction enables the circuit direction i e input or output for the GPIO1 line 0 input 1 output 0 GPIO0_DIR 0 GPIO0 Direction enables the circuit direction i e input or output for the GPIO0 line 0 input 1 output Bits Field Default Description Artisan Technology Grou...

Page 85: ...ircuit polarity i e high or low for the GPIO11 line 0 active high 1 active low 10 GPIO10_POL 0 GPIO10 Polarity enables the circuit polarity i e high or low for the GPIO10 line 0 active high 1 active low 9 GPIO9_POL 0 GPIO9 Polarity enables the circuit polarity i e high or low for the GPIO9 line 0 active high 1 active low 8 GPIO8_POL 0 GPIO8 Polarity enables the circuit polarity i e high or low for...

Page 86: ...IO2_POL 0 GPIO2 Polarity enables the circuit polarity i e high or low for the GPIO2 line 0 active high 1 active low 1 GPIO1_POL 0 GPIO1 Polarity enables the circuit polarity i e high or low for the GPIO1 line 0 active high 1 active low 0 GPIO0_POL 0 GPIO0 Polarity enables the circuit polarity i e high or low for the GPIO0 line 0 active high 1 active low Bits Field Default Description Artisan Techn...

Page 87: ... output type for the GPIO11 line 0 actively driven output 1 open drain output 10 GPIO10_OUTPUT_TYPE 0 GPIO10 Output Type enables the output type for the GPIO10 line 0 actively driven output 1 open drain output 9 GPIO9_OUTPUT_TYPE 0 GPIO9 Output Type enables the output type for the GPIO9 line 0 actively driven output 1 open drain output 8 GPIO8_OUTPUT_TYPE 0 GPIO8 Output Type enables the output typ...

Page 88: ...OUTPUT_TYPE 0 GPIO2 Output Type enables the output type for the GPIO2 line 0 actively driven output 1 open drain output 1 GPIO1_OUTPUT_TYPE 0 GPIO1 Output Type enables the output type for the GPIO1 line 0 actively driven output 1 open drain output 0 GPIO0_OUTPUT_TYPE 0 GPIO0 Output Type enables the output type for the GPIO0 line 0 actively driven output 1 open drain output Bits Field Default Descr...

Page 89: ... sensitive interrupt 1 select edge sensitive interrupt 10 GPIO10_INTERRUPT_TYPE 0 GPIO10 Interrupt Type enables the signal sensitivity interrupt type for the GPIO10 line 0 select level sensitive interrupt 1 select edge sensitive interrupt 9 GPIO9_INTERRUPT_TYPE 0 GPIO9 Interrupt Type enables the signal sensitivity interrupt type for the GPIO9 line 0 select level sensitive interrupt 1 select edge s...

Page 90: ...errupt Type enables the signal sensitivity interrupt type for the GPIO2 line 0 select level sensitive interrupt 1 select edge sensitive interrupt 1 GPIO1_INTERRUPT_TYPE 0 GPIO1 Interrupt Type enables the signal sensitivity interrupt type for the GPIO1 line 0 select level sensitive interrupt 1 select edge sensitive interrupt 0 GPIO0_INTERRUPT_TYPE 0 GPIO0 Interrupt Type enables the signal sensitivi...

Page 91: ... Register 0 disable de bounce circuit 1 enable de bounce circuit 12 GPIO12_DEBOUNCE_EN 0 GPIO12 Debounce Enable enables a debounce circuit for GPIO12 line if designated as an input in the Control Register 0 disable de bounce circuit 1 enable de bounce circuit 11 GPIO11_DEBOUNCE_EN 0 GPIO11 Debounce Enable enables a debounce circuit for GPIO11 line if designated as an input in the Control Register ...

Page 92: ... 0 disable de bounce circuit 1 enable de bounce circuit 3 GPIO3_DEBOUNCE_EN 0 GPIO3 Debounce Enable enables a debounce circuit for GPIO3 line if designated as an input in the Control Register 0 disable de bounce circuit 1 enable de bounce circuit 2 GPIO2_DEBOUNCE_EN 0 GPIO2 Debounce Enable enables a debounce circuit for GPIO2 line if designated as an input in the Control Register 0 disable de boun...

Page 93: ...the GPIO Polarity Register for the GPIO13 line 0 inactive state 1 active state 12 GPIO12_INPUT_DATA GPIO12 Input Data Read reads the GPIO Polarity Register for the GPIO12 line 0 inactive state 1 active state 11 GPIO11_INPUT_DATA GPIO11 Input Data Read reads the GPIO Polarity Register for the GPIO11 line 0 inactive state 1 active state 10 GPIO10_INPUT_DATA GPIO10 Input Data Read reads the GPIO Pola...

Page 94: ... Data Read reads the GPIO Polarity Register for the GPIO3 line 0 inactive state 1 active state 2 GPIO2_INPUT_DATA GPIO2 Input Data Read reads the GPIO Polarity Register for the GPIO2 line 0 inactive state 1 active state 1 GPIO1_INPUT_DATA GPIO1 Input Data Read reads the GPIO Polarity Register for the GPIO1 line 0 inactive state 1 active state 0 GPIO0_INPUT_DATA GPIO0 Input Data Read reads the GPIO...

Page 95: ...ity Register for the GPIO9 line 0 inactive state 1 active state 8 GPIO8_IO_DATA GPIO8 I O Data Read controls the GPIO output states as well as reports the input states for the GPIO Polarity Register for the GPIO8 line 0 inactive state 1 active state 7 GPIO7_IO_DATA GPIO7 I O Data Read controls the GPIO output states as well as reports the input states for the GPIO Polarity Register for the GPIO7 l...

Page 96: ...1 active state 1 GPIO1_IO_DATA GPIO1 I O Data Read controls the GPIO output states as well as reports the input states for the GPIO Polarity Register for the GPIO1 line 0 inactive state 1 active state 0 GPIO0_IO_DATA GPIO0 I O Data Read controls the GPIO output states as well as reports the input states for the GPIO Polarity Register for the GPIO0 line 0 inactive state 1 active state Address offse...

Page 97: ...6_INT_STAT GPIO6 Interrupt Status provides the GPIO interrupt status for the GPIO6 line 0 interrupt not active 1 interrupt active 5 GPIO5_INT_STAT GPIO5 Interrupt Status provides the GPIO interrupt status for the GPIO5 line 0 interrupt not active 1 interrupt active 4 GPIO4_INT_STAT GPIO4 Interrupt Status provides the GPIO interrupt status for the GPIO4 line 0 interrupt not active 1 interrupt activ...

Page 98: ...1_INT_MSK 1 GPIO11 Interrupt Mask blocks masks GPIO11 interrupt output 0 enable interrupt 1 disable mask interrupt 10 GPIO10_INT_MSK 1 GPIO10 Interrupt Mask blocks masks GPIO10 interrupt output 0 enable interrupt 1 disable mask interrupt 9 GPIO9_INT_MSK 1 GPIO9 Interrupt Mask blocks masks GPIO9 interrupt out put 0 enable interrupt 1 disable mask interrupt 8 GPIO8_INT_MSK 1 GPIO8 Interrupt Mask blo...

Page 99: ...ity of clear is determined by the CPIO Control Register settings 0 does not affect the corresponding GPIO15 bit 1 clear the corresponding GPIO15 bit 14 GPIO14_CLEAR GPIO14 Clear bit asserts the GPIO14 line Polarity of clear is determined by the CPIO Control Register settings 0 does not affect the corresponding GPIO14 bit 1 clear the corresponding GPIO14 bit 13 GPIO13_CLEAR GPIO13 Clear bit asserts...

Page 100: ...ar the corresponding GPIO6 bit 5 GPIO5_CLEAR GPIO5 Clear bit asserts the GPIO5 line Polarity of clear is determined by the GPIO Control Register settings 0 does not affect the corresponding GPIO5 bit 1 clear the corresponding GPIO5 bit 4 GPIO4_CLEAR GPIO4 Clear bit asserts the GPIO4 line Polarity of clear is determined by the GPIO Control Register settings 0 does not affect the corresponding GPIO4...

Page 101: ... by the corresponding bit in the Control Register 0 does not affect GPIO10 bit 1 set the corresponding GPIO10 bit 9 GPIO9_SET GPIO9 Set asserts the GPIO9 line Polarity is determined by the corresponding bit in the Control Register 0 does not affect GPIO9 bit 1 set the corresponding GPIO9 bit 8 GPIO8_SET GPIO8 Set asserts the GPIO8 line Polarity is determined by the corresponding bit in the Control...

Page 102: ... not affect GPIO2 bit 1 set the corresponding GPIO2 bit 1 GPIO1_SET GPIO1 Set asserts the GPIO1 line Polarity is determined by the corresponding bit in the Control Register 0 does not affect GPIO1 bit 1 set the corresponding GPIO1 bit 0 GPIO0_SET GPIO0 Set asserts the GPIO0 line Polarity is determined by the corresponding bit in the Control Register 0 does not affect GPIO0 bit 1 set the correspond...

Page 103: ...mon interrupt output CNTR_TIMR_INT Table 5 10 lists the counter timer registers Counter Enable Register The Counter Enable Register enables counters 15 0 Table 5 10 Counter timer registers Offset Register Description 0x50 Counter Enable Enables counters 0x52 Counter Disable Disables counters 0x54 Counter Mode Configures counter timer as a counter or timer 0x56 Counter Interrupt Mask Enables counte...

Page 104: ...er 4 Enable enables counter 4 0 disable counter 1 enable counter 3 CNTR3_EN 0 Counter 3 Enable enables counter 3 0 disable counter 1 enable counter 2 CNTR2_EN 0 Counter 2 Enable enables counter 2 0 disable counter 1 enable counter 1 CNTR1_EN 0 Counter 1 Enable enables counter 1 0 disable counter 1 enable counter 0 CNTR0_EN 0 Counter 0 Enable enables counter 0 0 disable counter 1 enable counter Add...

Page 105: ... 0 no effect 1 disable 6 CNTR6_DISABLE 0 Counter 6 Disable disables counter 6 0 no effect 1 disable 5 CNTR5_DISABLE 0 Counter 5 Disable disables counter 5 0 no effect 1 disable 4 CNTR4_DISABLE 0 Counter 4 Disable disables counter 4 0 no effect 1 disable 3 CNTR3_DISABLE 0 Counter 3 Disable disables counter 3 0 no effect 1 disable 2 CNTR2_DISABLE 0 Counter 2 Disable disables counter 2 0 no effect 1 ...

Page 106: ...er or counter 0 counter 1 timer 10 CNTR10_MODE 0 Counter 10 Mode configures counter 10 as a timer or counter 0 counter 1 timer 9 CNTR9_MODE 0 Counter 9 Mode configures counter 9 as a timer or counter 0 counter 1 timer 8 CNTR8_MODE 0 Counter 8 Mode configures counter 8 as a timer or counter 0 counter 1 timer 7 CNTR7_MODE 0 Counter 6 Mode configures counter 7 as a timer or counter 0 counter 1 timer ...

Page 107: ...le mask interrupt 13 CNTR13_INT_MSK 1 Counter 13 Interrupt Mask blocks masks the interrupt for counter 13 0 enable interrupt 1 disable mask interrupt 12 CNTR12_INT_MSK 1 Counter 12 Interrupt Mask blocks masks the interrupt for counter 12 0 enable interrupt 1 disable mask interrupt 11 CNTR11_INT_MSK 1 Counter 11 Interrupt Mask blocks masks the interrupt for counter 11 0 enable interrupt 1 disable m...

Page 108: ...terrupt for counter 3 0 enable interrupt 1 disable mask interrupt 2 CNTR2_INT_MSK 1 Counter 2 Interrupt Mask blocks masks the interrupt for counter 2 0 enable interrupt 1 disable mask interrupt 1 CNTR1_INT_MSK 1 Counter 1 Interrupt Mask blocks masks the interrupt for counter 1 0 enable interrupt 1 disable mask interrupt 0 CNTR0_INT_MSK 1 Counter 0 Interrupt Mask blocks masks the interrupt for coun...

Page 109: ..._INT_STAT Counter 7 Interrupt Status provides current interrupt status for counter 7 0 interrupt is de asserted 1 interrupt is asserted 6 CNTR6_INT_STAT Counter 6 Interrupt Status provides current interrupt status for counter 6 0 interrupt is de asserted 1 interrupt is asserted 5 CNTR5_INT_STAT Counter 5 Interrupt Status provides current interrupt status for counter 5 0 interrupt is de active 1 in...

Page 110: ...High and Counter Preload Value Low registers The 16 uppermost counter bits are read from the High register A subsequent read from the Low register provides the lower 16 bits of the preload value 0 CNTR0_INT_STAT Counter 0 Interrupt Status provides current interrupt status for counter 0 0 interrupt is de asserted 1 interrupt is asserted Address offset 0x200 0x204 0x23C Access Read only Bits Field D...

Page 111: ...ameters for the USART ports Table 5 11 USART Resister Offset Register Description 0xF0 USART 0 Control Mode 0xF2 USART 1 Control Mode 0xF4 USART 2 Control Mode 0xF6 USART 3 Control Mode 0xF8 USART 4Control Mode 0xFA USART 5 Control Mode 0xFC Unused 0xFE Unused Address offset 0xF0 0xFE Access Read write Bits Field Default Description 15 8 Not used Not used 7 ACTIVATE 0 Logical Device Activation ena...

Page 112: ...h USART will operate 0 standard asynchronous mode 1 external clock synchronous mode Table 5 12 Standard 16550 compatible USART registers Offset DLAB Register Description 0x0 0 Receive Buffer Transmit Buffer Receive data buffer read Transmit data buffer write 0x1 0 Interrupt Enable Interrupt event enable mask 0x2 X Interrupt Identification FIFO Control Interrupt event status read FIFO control setti...

Page 113: ... Read write Bit s Field Default Description 7 4 Not used Not used 3 Modem 0 Modem Status Interrupt Enable enables the modem status interrupt 0 block mask interrupt cause 1 enable interrupt cause 2 Line 0 Received Line Status Interrupt Enable enables an interrupt indicating the received line is available 0 block mask interrupt cause 1 enable interrupt cause 1 TX 0 Transmit Holding Register Interrup...

Page 114: ... the transmit and receive data FIFO buffers and sets the trigger levels 3 1 ID 0b000 Interrupt Identification as highest priority identifies the interrupt with highest priority 0b011 1st receiver line status 0b010 2nd receiver data available 0b001 3rd Transmit Holding Register empty 0b000 4th modem status 0 NPEND 1 Interrupt Pending indicates an USART interrupt is pending 0 interrupt is pending 1 ...

Page 115: ... Read only Bit s Field Default Description 7 DLAB 0 Divisor Latch Access Bit determines whether access is provided to normal registers at offset 0x0 and 0x1 or divisor latch registers 0 normal registers 1 divisor latch registers 6 BREAK 0 Break Control enables the break control function which forces serial data out to 0 0 disable break function 1 enable break function 5 STICK_PAR 0 Stick Parity en...

Page 116: ...et USART_Base 0x4 Access Write only Bit s Field Default Description 7 5 RSVD 0b000 Reserved read only 4 LOOPBACK 0 Loopback Mode sets modem operation to loopback mode In loop back mode the serial transmit output is set to 1 the transmit shift reg ister is internally connected to the receive shift register DTR is connected to DSR RTS is connected to CTS OUT1 is connected to RI and OUT2 is connected...

Page 117: ...r at least one full character start bit data parity stop bit time In FIFO mode this applies to the character at the top of the FIFO buffer This bit also generates a Receiver Line Status interrupt The Break Indi cator bit is cleared when read 0 no break event has occurred 1 break event has occurred 3 FE 0 Framing Error indicates when a received character does not have a valid stop bit In FIFO mode ...

Page 118: ...lt Description 7 DCD 0 Compliment of external DCD input equals OUT2 in loopback mode 6 RI 0 Compliment of external RI input equals OUT1 in loopback mode 5 DSR 0 Compliment of DSR input equals DTR in loopback mode 4 CTS 0 Compliment of external CTS input equals RTS in loopback mode 3 DDCD 0 Delta Data Carrier Detect indicates a change of state on DCD line 0 no change of state 1 change of state on D...

Page 119: ...lt Description 7 0 0x00 Table 5 13 shows the divisor values for some common serial data rates with a 14 7692MHz 48 0MHz x 4 13 reference clock Address offset USART Base 0x0 DLAB 1 Access Read write DIV 7 0 LSB of baud rate generator divisor Address offset USART Base 0x2 DLAB 1 Access Read write DIV 15 8 MSB of baud rate generator divisor Table 5 13 Baud rate divisor settings Baud Rate Sync Mode Di...

Page 120: ...nt Locations Figure 5 1 shows the C2K major component locations Figure 5 1 C2K component locations primary side 2 3 4 10 9 6 7 5 1 8 Drawing not to scale Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 121: ... ISP1563 USB 2 0 Controller M41T62 RTC DDR SDRAM Bank 0 XC3S1200E FPGA MV64460 System Controller PCI 6254 PCI cPCI Bridge MCP7447A MPC7448 PPC G4 processor Flash Memory PCI2050B PCI PCI Bridge DDR SDRAM Bank 1 GD31244 SATA Host Controller XC95144XL CPLD VSC8244 Quad Port Ethernet PHY Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 122: ... Misc Control header P18 on board 2 x 5 pin header PMC0 I O P11 on board 2 x 32 pin header PMC1 I O P12 on board 2 x 32 pin header Reset switch S1 rear panel manual hardware reset micro switch SATA1 P19 rear panel connector SATA2 P20 rear panel connector COM1 COM2 RS 232 P15 P16 rear panel DB9 connectors COM3 COM4 RS 232 P9 P10 on board 2 x 5 pin headers COM1 COM4 RS 422 P1 P4 on board 2 x 5 pin h...

Page 123: ...M per PICMG 2 0 Height 233 20 0 15 mm 9 1811 0 0059 in Depth 79 85 0 15 mm 3 15 0 0059 in Temperature Extended Temperature 0 C to 70 C ambient 40 C to 85 C 40 C to 85 C 55 C to 105 C Relative Humidity non condensing 5 to 95 40 C Shock half sine 12g peak 6ms Vibration random 5 100 Hz 2g Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 124: ...PB_RST COM7 P14 P11 P17 P18 EM_BOOTSEL ROM_WP J8 ETH2 SATA0 COM1 COM2 COM3 COM5 COM4 RS 232 COM6 P6 P4 P9 P2 P10 P3 P5 P7 P1 cPCI_J4 SATA1 P20 J10 J11 USB2 USB1 P12 ICMB P13 BATT BATT PB_RST P8 COM8 COM1 COM2 COM3 RS 232 Figure 6 1 C2K TM block diagram Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 125: ...ETH1_DA ETH1_DA GND ETH1_DC ETH1_DC GND ETH1_DB ETH1_DB GND ETH1_DD ETH1_DD GND 3 3V 3 3V 3 3V 5V 5V GND PMC0_5 PMC0_4 PMC0_3 PMC0_2 PMC0_1 GND PMC0_10 PMC0_9 PMC0_8 PMC0_7 PMC0_6 GND PMC0_15 PMC0_14 PMC0_13 PMC0_12 PMC0_11 GND PMC0_20 PMC0_19 PMC0_18 PMC0_17 PMC0_16 GND PMC0_25 PMC0_24 PMC0_23 PMC0_22 PMC0_21 GND PMC0_30 PMC0_29 PMC0_28 PMC0_27 PMC0_26 GND PMC0_35 PMC0_34 PMC0_33 PMC0_32 PMC0_31 ...

Page 126: ...COM8_TXC COM3_232_RX n c COM1_TXC COM2_TXC GND COM8_TXC COM3_232_TX n c COM1_TXC COM2_TXC GND COM8_RXD n c n c COM1_RXD COM2_RXD GND COM8_RXD n c n c COM1_RXD COM2_RXD GND COM8_TXD COM4_232_RX n c COM1_TXD COM2_TXD GND COM8_TXD COM4_232_TX n c COM1_TXD COM2_TXD GND COM3_RXC COM4_RXC COM5_RXC COM6_RXC COM7_RXC GND COM3_RXC COM4_RXC COM5_RXC COM6_RXC COM7_RXC GND COM3_TXC COM4_TXC COM5_TXC COM6_TXC ...

Page 127: ... PMC1_14 PMC1_13 PMC1_12 PMC1_11 GND PMC1_20 PMC1_19 PMC1_18 PMC1_17 PMC1_16 GND PMC1_25 PMC1_24 PMC1_23 PMC1_22 PMC1_21 GND PMC1_30 PMC1_29 PMC1_28 PMC1_27 PMC1_26 GND PMC1_35 PMC1_34 PMC1_33 PMC1_32 PMC1_31 GND PMC1_40 PMC1_39 PMC1_38 PMC1_37 PMC1_36 GND PMC1_45 PMC1_44 PMC1_43 PMC1_42 PMC1_41 GND PMC1_50 PMC1_49 PMC1_48 PMC1_47 PMC1_46 GND PMC1_55 PMC1_54 PMC1_53 PMC1_52 PMC1_51 GND PMC1_60 PMC...

Page 128: ...n assignment listed in Table 6 5 applies to both P19 and P20 SATA connectors 1 8 Table 6 4 Ethernet RJ 45 rear panel connectors J6 J7 J8 pin assignments Pin Assignments 1 ETHn_DA TXD 2 ETHn_DA TXD 3 ETHn_DB RXD 4 ETHn_DC 5 ETHn_DC 6 ETHn_DB RXD 7 ETHn_DD 8 ETHn_DD Figure 6 2 Ethernet RJ 45 connector pinout 1 2 3 4 5 6 7 Table 6 5 Serial ATA connectors P19 P20 pin assignments Pin Assignment 1 GND 2...

Page 129: ...B9 connectors to access the RS 232 serial ports COM1 P15 and COM2 P16 The pin assignment listed in Table 6 7 applies to both DB9 connectors Figure 6 5 Serial RS 232 DB9 connector pinout Table 6 7 COM1 P15 and COM2 P16 pin assignments Pin Assignment Pin Assignment 1 n c 2 COM1 2_RX 3 COM1 2_TX 4 n c 5 GND 6 n c 7 n c 8 n c 9 n c 4 3 2 1 Table 6 6 USB connectors J9 J10 and J11 pin assignments Pin As...

Page 130: ...in header P13 for the BATT line A 3 3V supply can be connected to the BATT header to provide power to the NVRAM RTC device as a battery backup when the C2K is not powered on but still installed in a chassis slot Table 6 8 COM1 P1 through COM8 P8 pin assignments Pin Assignment Pin Assignment 1 COMx_TXD 2 COMx_TXD 3 COMx_TXC 4 COMx_TXC 5 COMx_RXC 6 COMx_RXC 7 COMx_RXD 8 COMx_RXD 9 SGND 10 n c Table ...

Page 131: ...access to the GPIO Status and Control signals NOTE Samtec IDSD Series connectors can be used to mate with the GPIO connector Pin Assignment Pin Assignment 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 NOTE Samtec IDSD Series connectors can be used to mate with all on board headers Table 6 11 ICMB interface header P17 pin assignment n c n c ICMB_D ICMB_D GND n c n c n c n c n c Table 6 12 GPIO...

Page 132: ...1 2 to assert active low the EM_BOOTSEL signal see Boot Code Selection on page 4 3 and on pins 3 4 to assert active low the ROM_WP signal see External Write Protect on page 4 2 at the backplane Table 6 13 JTAG header P18 pin assignments Pin Assignment Pin Assignment 1 EM_BOOTSEL 2 GND 3 ROM_WP 4 GND 5 rsvd 6 GND 7 n c 8 n c 9 rsvd 10 3 3V Artisan Technology Group Quality Instrumentation Guaranteed...

Page 133: ...1_23 24 PMC1_24 25 PMC0_25 26 PMC0_26 25 PMC1_25 26 PMC1_26 27 PMC0_27 28 PMC0_28 27 PMC1_27 28 PMC1_28 29 PMC0_29 30 PMC0_30 29 PMC1_29 30 PMC1_30 31 PMC0_31 32 PMC0_32 31 PMC1_31 32 PMC1_32 33 PMC0_33 34 PMC0_34 33 PMC1_33 34 PMC1_34 35 PMC0_35 36 PMC0_36 35 PMC1_35 36 PMC1_36 37 PMC0_37 38 PMC0_38 37 PMC1_37 38 PMC1_38 39 PMC0_39 40 PMC0_40 39 PMC1_39 40 PMC1_40 41 PMC0_41 42 PMC0_42 41 PMC1_41...

Page 134: ...8 P16 P9 P10 P13 P17 P2 P19 P20 P18 P12 COM2 232 COM2 232 COM1 232 COM1 232 RESET RESET ETH 0 ETH 0 ETH 1 ETH 1 ETH 2 ETH 2 SATA 1 SATA 1 USB 3 USB 3 USB 2 USB 2 USB 1 USB 1 SATA 2 SATA 2 J5 J4 J3 Figure 6 6 C2K TM connector locations Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 135: ...O on board header RJ 45 ETH2 rear panel connector PMC1 I O on board header Type A USB1 rear panel connector BATT on board header Type A USB2 rear panel connector GPIO on board header Type A USB3 rear panel connector DB9 COM1 RS 232 rear panel connector COM1 RS 422 on board header DB9 COM2 RS 232 rear panel connector COM2 RS 422 on board header ICMB interface on board header COM3 RS 422 on board he...

Page 136: ...N HISTORY ECO REV SHEET LOC DATE TABLE OF CONTENTS DESCRIPTION C SIZE DRAWING NUMBER REV R SBS Technologies Inc RALEIGH NC 27607 6301 CHAPEL HILL RD SBC GROUP All resistor values are in ohms All discrete resistor tolerances are 1 1 Unless otherwise specified All resistor network tolerances are 5 Denotes active low signal Denote differential pairs 2 Signal name conventions 3 Detailed part informati...

Page 137: ...ATA1 P14 GPIO Misc Reset Switch P19 ICMB P13 BATT P15 P16 COM1 COM2 RS 232 romwp embootsel P20 SATA2 P18 J 5 J 3 J 4 J 8 E T H 2 J 6 E T H 0 J 7 E T H 1 J 1 0 P 1 9 S A T A 1 J 1 1 J 9 P 1 6 C O M 2 R S 2 3 2 P12 PMC1 I O P10 COM3 RS 232 P11 PMC0 I O R S T S W P14 GPIO etc P13 BATT P4 COM4 RS422 485 P5 COM5 RS422 485 P6 COM6 RS422 485 P1 COM1 RS422 P2 COM2 RS422 P3 COM3 RS422 485 P9 COM4 RS 232 P7...

Page 138: ...20 E19 E18 E17 E16 E15 E25 E24 E23 E11 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 J4 CPCI_25A D22 D21 D20 D19 D18 D17 D16 D15 D25 D24 D23 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 J4 CPCI_25A 3 3V NC4_A3 NC4_A23 NC4_A25 4B2 6F2 4E2 4A7 6D6 6D6 6C8 J3_ETH0_DD J3_ETH0_DC J3_ETH0_DC J3_ETH0_DB J3_ETH0_DA NC4_E25 NC4_D25 COM6_TXD COM6_TXD COM6_RXD COM6_RXD COM6_TXC COM6_TXC COM6_RXC COM6_RXC COM5_RXD COM8_RXD 4D8 4F7 GP...

Page 139: ...HR_2X5 9 8 7 6 5 4 3 2 10 1 SMD_SHR_2X5 P4 1 10 2 3 4 5 6 7 8 9 P3 SMD_SHR_2X5 9 8 7 6 5 4 3 2 10 1 SMD_SHR_2X5 P9 3 3V 9 7 6 5 4 3 2 1 SMD_SHR_2X5 P17 1 10 2 3 4 5 6 7 8 9 P13 SMD_SHR_2X5 BIT_PASS GPIO_D14 GPIO_D12 GPIO_D10 GPIO_D8 GPIO_D6 GPIO_D4 GPIO_D2 GPIO_D0 GPIO_D15 3E2 4D2 3E8 3E3 5C7 3E8 3E3 4E4 3E2 4E4 3E2 3E3 3E8 GPIO_D1 3E8 3E8 3E7 3D5 5D7 3D2 3E5 3E5 3D4 3D4 3D2 3C2 3D2 3C2 3D2 3C2 3C...

Page 140: ...C0_64 PMC0_62 PMC0_60 PMC0_58 PMC0_56 PMC0_54 PMC0_52 PMC0_50 PMC0_48 PMC0_46 PMC0_44 PMC0_42 PMC0_40 PMC0_38 PMC0_36 PMC0_34 PMC0_32 PMC0_30 PMC0_28 PMC0_26 PMC0_24 PMC0_22 PMC0_20 PMC0_18 PMC0_16 PMC0_14 PMC0_12 PMC0_10 PMC0_8 PMC0_6 PMC0_4 PMC0_2 PMC0_ 64 1 PMC0_1 PMC0_3 PMC0_5 PMC0_7 PMC0_9 PMC0_11 PMC0_13 PMC0_15 PMC0_17 PMC0_19 PMC0_21 PMC0_23 PMC0_25 PMC0_27 PMC0_29 PMC0_31 PMC0_33 PMC0_35 ...

Page 141: ... J9 1 2 3 6 4 5 7 8 9 10 J6 CONN_RJ45 1 2 3 6 4 5 7 8 9 10 J8 CONN_RJ45 10 9 8 7 5 4 6 3 2 1 CONN_RJ45 J7 7 6 5 4 3 2 1 9 8 P20 3 7 10 11 1 2 4 5 9 6 8 P16 CONN_DB9_RA 3 7 10 11 1 2 4 5 9 6 8 P15 CONN_DB9_RA 6E9 6E9 6F9 6F9 6E9 5D9 3E2 3C9 3C7 3C4 3C9 3C7 3C4 3C3 3C3 3C9 3C7 3C9 3C4 3C7 3C3 3C4 3C3 R2 10 3E3 FB1 100MA 600 OHM USB3_D 3C4 3C4 3C2 3C2 3C7 3C8 3C7 3C8 USB1_D 3E5 USB3_VCC 3E8 USB1_GND ...

Page 142: ...d I O connections If products must be returned contact GE for a Return Material Authorization RMA Number This RMA Number must be obtained prior to any return RMA request forms can be obtained from www ge ip com rma GE Technical Support is available at 1 800 433 2682 in North America or 1 780 401 7700 for international calls Requests for Technical Support can be sent to support huntsville ip ge com...

Page 143: ...front panel Ethernet RJ 45 J15 3 15 PMC0_P11 P12 3 10 PMC0_P13 P14 3 11 6 12 PMC1_P21 P22 3 12 PMC1_P23 P24 3 13 Counter timers 4 7 cPCI interface 4 9 CPLD SMI 4 8 CPLD registers configuration 5 8 control 5 9 5 10 firmware release ID 5 7 GPIO interrupt mask 5 32 interrupt mask 5 11 5 13 D DDR SDRAM 4 1 Device Bus 4 4 E Emissions 1 4 Ethernet port 4 4 F Flash ROM 4 1 Flash write protection 4 1 FPGA...

Page 144: ...Q Quad UART RS 422 4 5 R Real Time Clock 4 9 Related Documents 1 7 S Safety 1 4 Serial I O RS 232 ports 4 5 RS 422 ports 4 5 SMBus 4 4 5 2 T Technical Support 1 7 Temperature sensor 4 15 TM schematics 6 14 U U Boot Utility 2 7 V Vibration 1 3 W Watchdog timer 4 7 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 145: ...OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED INCLUDING BUT NOT LIMITED TO WARRANTIES OF DESIGN MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ALL OTHER LIABILITY ARISING FROM RELIANCE UPON ANY INFORMATION CONTAINED HEREIN IS EXPRESSLY DISCLAIMED GE Intelligent Platforms Information Centers Americas 1 800 322 3616 or 1 256 880 0444 Asia Pacific 86 10 6561 1561 Europe Middle East and Af...

Page 146: ...l service in house repair center WE BUY USED EQUIPMENT Sell your excess underutilized and idle used equipment We also offer credit for buy backs and trade ins www artisantg com WeBuyEquipment REMOTE INSPECTION Remotely inspect equipment before purchasing with our interactive website at www instraview com LOOKING FOR MORE INFORMATION Visit us on the web at www artisantg com for more information on ...

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