GE BRIVO MR355, Service Training, Page: 121 / 227

119
The IRF3 is the third generation Interface and Remote RF Functions circuit board. It is designed for use
within the DVMR system and, despite many architectural similarities, maintains no backwards
compatibility with IRF or IRF2.
The IRF3 primarily serves as a communications hub within the CAM chassis, supporting
communication with one or two Remote Receiver devices (RRx), one or two Remote Exciter devices
(DTx), and the XGD gradient subsystem via five identical high-speed (2Gbit) serial fiber optic interfaces
implementing the DVMR Common Communications Link.
The IRF3 accepts an 80MHz reference clock input via a fiber optic receiver. This clock is used as the
master clock, both on-board and for the CAM system. CAM clocks, except PCI, are normally derived
from this reference. The FPGA provides logic to detect the absence of transitions on the reference
clock input. The FPGA also provides the ability to operate the CAM system stand-alone, using the PCI
clock instead of the reference clock, and, in fact, this is the default clock mode of the IRF3. Note that
system operation is asynchronous in this mode.
The IRF3 includes a front panel reset push button for CAM chassis reset. The debounced switch drives
the backplane reset request to the backplane system slots with a pulse of at least 100ms to initiate a
PCI reset.
The IRF3 interfaces to the CAM system through the backplane. These interfaces include the 32-bit 33
MHz PCI interface and the custom Sequence Bus. This also includes the CAM chassis temperature
monitoring portion of the SMC interface.
The IRF3 provides the same SMC inputs and outputs as IRF1 and IRF2. In SV, only Scan Room Door is
required.
The IRF3 provides five instances of the DVMR Common Communications Link that are identical and
interchangeable. The fiber optic transceiver modules have internal real-time diagnostic capability, and
measure internal module temperature, internal supply voltage, transmit bias current, transmit optical
output power and receive optical input power. Via the FPGA, these values are collected and made
available to the system via PCI.
Eight indicator LEDs on the front panel to provide general status information and to provide the status
of the communications links.