GSWP050W-EVBPA
GaN E-HEMT Wireless Power Transfer Evaluation Board
User’s Guide
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GSWP050W-EVBPA Rev 190304
© 2019 GaN Systems Inc.
www.gansystems.com 17
Please refer to the Evaluation Board/Kit Important Notice on page 22
The evaluation results for performance are captured in Figures 17 through 21.
Figure 17 •
Oscilloscope Plot Showing Both GS61004B Gate Node Signals at TP8, TP81
For a Class EF2 power amplifier topology, the optimal efficiency is achieved at a duty cycle of
approximately 35%. At that operating point, the PA can work under very ZVS wide impedance range
with high efficiency. The PA duty cycle is controlled by gate driver PE29102A. For a detailed time-delay
design please refer to Figure 8 and Figure 9. The total resistor value of R955/R965 dominates the dead
time of U86, and the delay time of U90 is controlled by R953/R952. Both two of PE29102A operate as
high side mode, low side of chip is disable, and to reduce inductance thru shortened length of trace
between gate of GS61004B and PE29102A, the pins of low side output of PE29102A are removed in the
layout.
Typical waveforms at the devices Drain node are shown in Figure 18. Channel 1 is shown in yellow and
channel 2 is shown in blue. At 25.0V
DC
input voltage, the output power is 50W .
Figure 18 •
Oscilloscope Plot Showing Both GS61004B Drain Node Signals