eRide
OPUS 6/
eRide
OPUS 7 GV-8620/ GV-8720
Dead Reckoning User
’
s Guide
SE16-900-002-02
4
FURUNO ELECTRIC CO., LTD. All rights reserved.
4 Reference Circuit
This section shows reference circuits of FURUNO supported sensor. Operation guarantee of these circuits is
just based on FURUNO original development environment, which means that FURUNO is not able to
guarantee operation at customer development environment. Therefore, please verify and check expected
operation at customer end.
For example, in the schematics below, the both I2C lines (TXD2_SCL, RXD2_SDA) are pulled up with the
10k
Ω resistors (R1, R2). Depending on the wiring capacity of the I2C line, the H and L levels may deviate from
the specified values, or the rising slope may become slow, causing timing errors. In such a case, it can be
adjusted by decreasing the value of the pull-up resistors (R1, R2) within the range that the IC can drive. Since
the wiring capacity varies according to the customer's actual layout of the circuit board, the design should be
decided by customer's evaluation.
4.1 SMI130
I/O signal
Description
Interface connection destination
eRideOPUS 6/7
GV-86/ 87
SCL
I2C clock
TXD2_SCL
TXD2_SCL
SDA
I2C address/data bus
RXD2_SDA
RXD2_SDA
Figure 4.1 Reference Circuit of SMI130
Notes:
(*1) When the I2C master device is eRideOPUS 6/eRideOPUS 7 and using 1.8V I/O power supply, please
change to 3.3V I/O signal voltage with level shifter.
(*2) The power supply (VCC) should be common with the receiver.
(*3)
Since this resistance value may not satisfy the electrical characteristics due to the floating capacitance of
the line, please decide the resistance value in consideration of the floating capacitance of the line.
SCL
SDA
R2
10k
C1
0.1uF
R1
10k
C2
0.1uF
U1
SMI130
INT2
1
NC
2
VDD
3
GND
4
CSB2
5
GNDIO
6
PS
7
SC
K
8
SDI
9
SDO2
10
VDDIO
11
INT3
12
INT4
13
CSB1
14
SDO1
15
IN
T
1
16
VCC
VCC
VCC
(*1)
(*1)
(*2)
(*2)
(*2)
(*3)
(*3)
