Fukuda Denshi HC-530, Service Manual

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Chapter 8
(1) External interruption
IRQ0: End of A/D conversion
IRQ1: SCA send/receive interruption
(2) Serial interface
ch1:
Communication system: Start-stop
Baud rate: 19200 bps
Data bits: 8 bits
Stop bits: 1 bit
Parity: None
Flow control: None
Reset IC (MB3773)
Power-on reset: 1000 ms
Watchdog timer clock: 1000 ms
Watchdog timer reset: 160 ms
HJCPU Circuit Diagram (Page 3)
This circuit uses an MBM29F800BC-70PFTN (1 MB) device for the application
area, and an HY5118160CJC-60 (2MB) device for the work area.
HJCPU Circuit Diagram (Page 4)
This circuit uses a pair of TC55100CFT-70L devices (128 bytes each) for the
work area for HDLC communication.
HJCPU Circuit Diagram (Page 5)
This circuit uses an ispLSI2064LT100 (PLD) device as the SCA interface
control and I/O circuit.
IO
INST1 to 9: Installs ECG when low.
RESPINST: Installs RESP when low.
LD_CNT0-3: Switch between electrodes subject to detection of
disconnect.
0h: RA 1h: LA 2h: LF 3h: C1 4h: C2 5h: C3 6h: C4
7h: C5 8h: C6
LEAD_SEL0, 1: Switch between leads according to the number of electrodes.
0h: 3-electrode lead III
1h: 3-electrode lead II
2h: 3-electrode lead I
3h: 10-electrode or 5-electrode lead
HJCPU Circuit Diagram (Page 6)
This circuit uses an HD64570F (SCA) device as a serial communication IC for
HDLC communication.
HJCPU Circuit Diagram (Page 7)
This circuit converts the serial data (from the A/D converter) to 16-bit parallel
data. Start of A/D conversion is delayed 75 us after issue of the S/W instruction.
HJCPU Circuit Diagram (Page 8)
This circuit detects pacing pulses and changes them to 10-ms pulses.
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