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C141-E093-01EN

6 - 2

6.1.1

Response to power-on

After the master device (device 0) releases its own power-on reset state, the master device
shall check a DASP- signal for up to 450 ms to confirm presence of a slave device (device 1).
The master device recognizes presence of the slave device when it confirms assertion of the
DASP- signal. Then, the master device checks a PDIAG- signal to see if the slave device has
successfully completed the power-on diagnostics.

If the master device cannot confirm assertion of the DASP- signal within 450 ms, the master
device recognizes that no slave device is connected.

After the slave device (device 1) releases its own power-on reset state, the slave device shall
report its presence and the result of power-on diagnostics to the master device as described
below:

DASP- signal: Asserted within 400 ms, and negated after the first command is received from

the host or within 31 seconds or after executing software reset, which ever
comes first.

PDIAG- signal: Negated within 1 ms and asserted within 30 seconds, then negated within 31

seconds.

Max. 31 sec.

Max. 400 ms.

Max. 31 sec.

Max. 30 sec.

Max. 1 ms.

If presence of a slave device is
confirmed, PDIAG- is checked for
up to 31 seconds.

Checks DASP- for up to
450 ms.

DASP-

PDIAG-

BSY bit

Power On Reset-

Status Reg.
BSY bit

Power On Reset-

Slave device

Master device

Power on

Figure 6.1

Response to power-on

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Summary of Contents for MPE3043AE

Page 1: ...C141 E093 02EN MPE3xxxAE DISK DRIVES PRODUCT MANUAL ...

Page 2: ...start time is modified in the Table 1 1 A dimension is added to the Figure 3 1 R in the explanatory notes of the Table 5 4 is modified Section 6 3 1 Power save mode is modified Specification No C141 E093 EN The contents of this manual is subject to change without prior notice All Rights Reserved Copyright 1999 FUJITSU LIMITED ...

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Page 4: ...k drives into user systems This manual assumes that users have a basic knowledge of hard disk drives and their application in computer systems This manual consists of the following six chapters Chapter 1 DEVICE OVERVIEW Chapter 2 DEVICE CONFIGURATION Chapter 3 INSTALLATION CONDITIONS Chapter 4 THEORY OF DEVICE OPERATION Chapter 5 INTERFACE Chapter 6 OPERATIONS In this manual disk drives may be ref...

Page 5: ...situation could result in minor or moderate personal injury if the user does not perform the procedure correctly This alert signal also indicates that damages to the product or other property may occur if the user does not perform the procedure correctly This indicates information that could help the user use the product more efficiently In the text the alert signal is centered followed below by t...

Page 6: ...e adjustment repair or replacement Fujitsu is not liable for any other disk drive defects such as those caused by user misoperation or mishandling inappropriate operating environments defects in the power supply or cable problems of the host system or other causes outside the disk drive ...

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Page 8: ... 1 6 Shock and Vibration 1 9 1 7 Reliability 1 9 1 8 Error Rate 1 10 1 9 Media Defects 1 10 CHAPTER 2 DEVICE CONFIGURATION 2 1 2 1 Device Configuration 2 1 2 2 System Configuration 2 3 2 2 1 ATA interface 2 3 2 2 2 1 drive connection 2 3 2 2 3 2 drives connection 2 3 CHAPTER 3 INSTALLATION CONDITIONS 3 1 3 1 Dimensions 3 1 3 2 Mounting 3 3 3 3 Cable Connections 3 7 3 3 1 Device connector 3 7 3 3 2...

Page 9: ...alibration contents 4 8 4 5 2 Execution timing of self calibration 4 9 4 5 3 Command processing during self calibration 4 9 4 6 Read write Circuit 4 10 4 6 1 Read write preamplifier PreAMP 4 10 4 6 2 Write circuit 4 10 4 6 3 Read circuit 4 11 4 6 4 Synthesizer circuit 4 12 4 7 Servo Control 4 12 4 7 1 Servo control circuit 4 13 4 7 2 Data surface servo format 4 16 4 7 3 Servo frame format 4 16 4 7...

Page 10: ...Initiating an Ultra DMA data in burst 5 70 5 5 3 2 The data in transfer 5 71 5 5 3 3 Pausing an Ultra DMA data in burst 5 71 5 5 3 4 Terminating an Ultra DMA data in burst 5 72 5 5 4 Ultra DMA data out commands 5 74 5 5 4 1 Initiating an Ultra DMA data out burst 5 74 5 5 4 2 The data out transfer 5 75 5 5 4 3 Pausing an Ultra DMA data out burst 5 75 5 5 4 4 Terminating an Ultra DMA data out burst ...

Page 11: ...er on and reset 5 94 CHAPTER 6 OPERATIONS 6 1 6 1 Device Response to the Reset 6 1 6 1 1 Response to power on 6 2 6 1 2 Response to hardware reset 6 3 6 1 3 Response to software reset 6 4 6 1 4 Response to diagnostic command 6 5 6 2 Address Translation 6 6 6 2 1 Default parameters 6 6 6 2 2 Logical address 6 7 6 3 Power Save 6 8 6 3 1 Power save mode 6 8 6 3 2 Power commands 6 10 6 4 Defect Manage...

Page 12: ...ing the condition of the CBLID signal 3 11 3 12 Cable type detection using IDENTIFY DEVICE data Device sensing the condition of the CBLID signal 3 11 3 13 Jumper location 3 12 3 14 Factory default setting 3 13 3 15 Jumper setting of master or slave device 3 13 3 16 Jumper setting of Cable Select 3 14 3 17 Example 1 of Cable Select 3 14 3 18 Example 2 of Cable Select 3 14 4 1 Head structure 4 2 4 2...

Page 13: ...rst 5 87 5 14 Host terminating an Ultra DMA data in burst 5 88 5 15 Initiating an Ultra DMA data out burst 5 89 5 16 Sustained Ultra DMA data out burst 5 90 5 17 Device pausing an Ultra DMA data out burst 5 91 5 18 Host terminating an Ultra DMA data out burst 5 92 5 19 Device terminating an Ultra DMA data out burst 5 93 5 20 Power on Reset Timing 5 94 6 1 Response to power on 6 2 6 2 Response to h...

Page 14: ...signals 5 2 5 2 Signal assignment on the interface connector 5 3 5 3 I O registers 5 7 5 4 Command code and parameters 5 14 5 5 Information to be read by IDENTIFY DEVICE command 5 30 5 6 Features register values and settable modes 5 35 5 7 Diagnostic code 5 39 5 8 Features Register values subcommands and functions 5 49 5 9 Format of device attribute value data 5 52 5 10 Format of insurance failure...

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Page 16: ... ATA controller The disk drive is compact and reliable 1 1 Features 1 1 1 Functions and performance 1 Compact The disk has 1 or 2 disks of 95 mm 3 5 inches diameter and its height is 26 1 mm 1 inch 2 Large capacity The disk drive can record up to 8 46 GB formatted on one disk using the 48 51 EPR4ML recording method and 15 recording zone technology The MPE3xxxAE series have a formatted capacity of ...

Page 17: ... disk drive can be connected to an ATA interface of a personal computer 2 512KB data buffer The disk drive uses a 512KB data buffer to transfer data between the host and the disk media In combination with the read ahead cache system described in item 3 and the write cache described in item 6 the buffer contributes to efficient I O processing 3 Read ahead cache system After the execution of a disk ...

Page 18: ...ry The 40 bytes ECC has improved buffer error correction for correctable data errors 6 Write cache When the disk drive receives a write command the disk drive posts the command completion at completion of transferring data to the data buffer completion of writing to the disk media This feature reduces the access time at writing ...

Page 19: ... Write 19 ms typical Start Stop time Start 0 rpm to Drive Read Stop at Power Down Typical 8 sec Maximum 16 sec Typical 20 sec Maximum 30 sec Interface ATA 4 Maximum Cable length 0 46 m Data Transfer Rate To From Media To From Host 20 3 to 34 4 MB s 16 7 MB s Max burst PIO mode 4 burst DMA mode 2 66 6 MB s Max burst ultra DMA mode 4 Data buffer 512 KB Physical Dimensions Height Width Depth 26 1 mm ...

Page 20: ...rs Model Name Capacity user area Mounting Screw Order No Remarks MPE3043AE 4 33 GB No 6 32UNC CA05743 B311 MPE3084AE 8 45 GB No 6 32UNC CA05743 B321 MPE3173AE 17 34 GB No 6 32UNC CA05743 B341 1 3 Power Requirements 1 Input Voltage 5 V 5 12 V 8 2 Ripple 12 V 5 V Maximum 200 mV peak to peak 100 mV peak to peak Frequency DC to 1 MHz DC to 1 MHz ...

Page 21: ... 300 450 5 5 5 5 5 9 Standby 7 0 7 0 7 0 185 1 0 1 0 1 0 Sleep 7 0 7 0 7 0 185 1 0 1 0 1 0 1 Current is typical rms except for spin up 2 Power requirements reflect nominal values for 12V and 5V power 3 Idle mode is in effect when the drive is not reading writing seeking or executing any commands A portion of the R W circuitry is powered down the spindle motor is up to speed and the Drive ready con...

Page 22: ...er on off sequence The voltage detector circuit monitors 5 V and 12 V The circuit does not allow a write signal if either voltage is abnormal This prevents data from being destroyed and eliminates the need to be concerned with the power on off sequence 5VDC 0 5A div 0 0 0 0 0 5 1 0 A 1 5 A 0 5 0 12VDC 0 5A div 1 2 seconds 8 7 6 5 4 3 ...

Page 23: ... 80 RH Non condensing 5 to 85 RH Non condensing 29 C Altitude relative to sea level Operating Non operating 60 to 3 000 m 200 to 10 000 ft 60 to 12 000 m 200 to 40 000 ft 1 5 Acoustic Noise Table 1 5 lists the acoustic noise specification Table 1 5 Acoustic noise specification Model MPE3043AE MPE3084AE MPE3173AE Idle mode DRIVE READY 3 4 bels 3 5 bels Seek mode Random 4 0 bels 4 1 bels Idle mode D...

Page 24: ... mean time between failures MTBF is 500 000 POH power on hours or more operation 24 hours day 7 days week This does not include failures occurring during the first three months after installation MTBF is defined as follows MTBF H Disk drive defects refers to defects that involve repair readjustment or replacement Disk drive defects do not include failures caused by external factors such as damage ...

Page 25: ...ernative blocks can be assigned are not included in the error rate count below It is assumed that the data blocks to be accessed are evenly distributed on the disk media 1 Unrecoverable read error Read errors that cannot be recovered by read retries without user s retry and ECC corrections shall occur no more than 10 times when reading data of 1015 bits Read retries are executed according to the d...

Page 26: ...iguration 2 1 Device Configuration Figure 2 1 shows the disk drive The disk drive consists of a disk enclosure DE read write preamplifier and controller PCA The disk enclosure contains the disk media heads spindle motors actuators and a circulating air filter Figure 2 1 Disk drive outerview ...

Page 27: ...ned by feedback of the servo information read by the read write head If the power is not on or if the spindle motor is stopped the head assembly stays in the specific CSS zone on the disk and is fixed by a mechanical lock 5 Air circulation system The disk enclosure DE is sealed to prevent dust and dirt from entering The disk enclosure features a closed loop air circulation system that relies on th...

Page 28: ...A mode 2 and the ultra DMA transfer till 66 6 MB s Ultra DMA mode 4 2 2 2 1 drive connection ATA interface AT bus Host interface Disk drive HA Host adaptor Host Figure 2 2 1 drive system configuration 2 2 3 2 drives connection ATA interface AT bus Host interface Disk drive 1 Disk drive 0 HA Host adaptor Host Note When the drive that is not conformed to ATA is connected to the disk drive is above c...

Page 29: ...de 3 mode 4 DMA mode 2 or ultra DMA mode 4 occurrence of ringing or crosstalk of the signal lines AT bus between the HA and the disk drive may be a great cause of the obstruction of system reliability Thus it is necessary that the capacitance of the signal lines including the HA and cable does not exceed the ATA 3 and ATA 4 standard and the cable length between the HA and the disk drive should be ...

Page 30: ...INSTALLATION CONDITIONS 3 1 Dimensions 3 2 Mounting 3 3 Cable Connections 3 4 Jumper Settings 3 1 Dimensions Figure 3 1 illustrates the dimensions of the disk drive and positions of the mounting screw holes All dimensions are in mm ...

Page 31: ...C141 E093 02EN 3 2 Figure 3 1 Dimensions ...

Page 32: ...body is connected to signal ground SG and the mounting frame is also connected to signal ground These are electrically shorted Note Use No 6 32UNC screw for the mounting screw and the screw length should satisfy the specification in Figure 3 4 3 Limitation of side mounting When the disk drive is mounted using the screw holes on both side of the disk drive use two screw holes shown in Figure 3 3 Do...

Page 33: ...e 3 4 Mounting frame structure 5 0 or less 4 5 or less 2 B Frame of system cabinet Details of B Details of A Frame of system cabinet Screw Screw PCA DE 2 5 2 5 2 5 A DE Side surface mounting Bottom surface mounting Do not use this screw holes Use these screw holes ...

Page 34: ... in the cabinet such that the PCA side in particular receives sufficient cooling To check the cooling efficiency measure the surface temperatures of the DE Regardless of the ambient temperature this surface temperature must meet the standards listed in Table 3 1 Figure 3 5 shows the temperature measurement point Figure 3 5 Surface temperature measurement points Table 3 1 Surface temperature measur...

Page 35: ...on Figure 3 6 Service area 6 External magnetic fields Avoid mounting the disk drive near strong magnetic sources such as loud speakers Ensure that the disk drive is not affected by external magnetic fields P side Cable connection Mode setting switches R side Mounting screw hole Mounting screw hole Q side Mounting screw hole ...

Page 36: ...connectors and terminals listed below for connecting external devices Figure 3 7 shows the locations of these connectors and terminals Power supply connector CN1 ATA interface connector CN1 Figure 3 7 Connector locations ATA interface connector Mode Setting Pins Power supply connector CN1 ...

Page 37: ...ket housing 1 480424 0 AMP Contact 60617 4 AMP Note The cable of twisted pairs and neighboring line separated individually is not allowed to use for the host interface cable It is because that the location of signal lines in these cables is not fixed and so the problem on the crosstalk among signal lines may occur It is recommended to use the ribbon cable for ATA interface that cable length is les...

Page 38: ... fine pitch cable to double the number of conductors available to the 40 pin connector The grounds assigned by the interface are commoned with the additional 40 conductors to provide a ground between each signal line and provide the effect of a common ground plane 2 The cable assembly may contain up to 3 connectors which shall be uniquely colored as follows All connectors shall have position 20 bl...

Page 39: ...a DMA modes greater than mode 2 shall not connect to the PDIAG CBLID signal c Host system that do support Ultra DMA modes greater than mode 2 shall either connect directly to the device without using a cable assembly or determine the cable assembly type Determining the cable assembly type may be done either by the host sensing the condition of the PDIAG CBLID signal see Figure 3 11 or by relying o...

Page 40: ...sensing the condition of the CBLID signal open 0 047 µF 10 or 20 Host Device 0 Device 1 with 80 conductor cable with 40 conductor cable PDIAG CBLID conductor PDIAG CBLID conductor IDENTIFY DEVICE information word 93 bit13 1 Device detected CBLID above VIH IDENTIFY DEVICE information word 93 bit13 0 Device detected CBLID below VIL Host Device 0 Device 1 0 047 µF 10 or 20 Figure 3 12 Cable type dete...

Page 41: ... 3 4 Jumper Settings 3 4 1 Location of setting jumpers Figure 3 13 shows the location of the jumpers to select drive configuration and functions Figure 3 13 Jumper location Interface Connector 1 DC Power Connector 2 1 40 ...

Page 42: ...elected 8 6 4 2 a Master device shorted b Slave device 9 7 5 3 1 8 6 4 2 9 7 5 3 1 Figure 3 15 Jumper setting of master or slave device Note When the device type is set by the jumper on the device the device should not be configured for cable selection 2 Cable Select CSEL In Cable Select mode the device can be configured either master device or slave device For use of Cable Select function Unique ...

Page 43: ...f the cable and connecting it to ground further the CSEL is set to low level The device is identified as a master device At this time the CSEL of the slave device does not have a conductor Thus since the slave device is not connected to the CSEL conductor the CSEL is set to high level The device is identified as a slave device Open CSEL conductor GND Slave device Master device Host system Figure 3...

Page 44: ...plied Slave Device Master Device Cable Select 8 6 4 2 9 7 5 3 1 8 6 4 2 9 7 5 3 1 8 6 4 2 9 7 5 3 1 Model No of cylinders No of heads No of sectors MPE3043AE 4 092 16 63 MPE3084AE 4 092 16 63 MPE3173AE 4 092 16 63 b Slave present If the slave device does not use the Device Active Slave Present DASP signal to indicate its presence the device is configured as a Master with slave present when the fol...

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Page 46: ... and drive control method 4 2 Subassemblies The disk drive consists of a disk enclosure DE and printed circuit assembly PCA The DE contains all movable parts in the disk drive including the disk spindle actuator read write head and air filter For details see Subsections 4 2 1 to 4 2 5 The PCA contains the control circuits for the disk drive The disk drive has one PCA For details see Sections 4 3 4...

Page 47: ...embly is activated by the direct drive sensor less DC spindle motor which has a speed of 5 400 rpm The spindle is controlled with detecting a PHASE signal generated by counter electromotive voltage of the spindle motor at starting After that the rotational speed is kept with detecting a servo information 4 2 4 Actuator The actuator consists of a voice coil motor VCM and a head carriage The VCM mov...

Page 48: ...around the spindle when the disk starts or stops rotating When disk drives are transported under conditions where the air pressure changes a lot filtered air is circulated in the DE The circulation filter cleans out dust and dirt from inside the DE The disk drive cycles air continuously through the circulation filter through an enclosed loop air cycle system operated by a blower on the rotating di...

Page 49: ...ontains the 48 51 group coded recording GCR encoder and decoder and servo demodulation circuit 2 Servo circuit The position and speed of the voice coil motor are controlled by 2 closed loop servo using the servo information recorded on the data surface The servo information is an analog signal converted to digital for processing by a MPU and then reconverted to an analog signal for control of the ...

Page 50: ...C141 E093 01EN 4 5 Figure 4 2 MPE3xxxAE Block diagram ...

Page 51: ... read write test after enabling response to the ATA bus c After confirming that the spindle motor has reached rated speed the disk drive releases the heads from the actuator magnet lock mechanism by applying current to the VCM This unlocks the heads which are parked at the inner circumference of the disks d The disk drive positions the heads onto the SA area and reads out the system information e ...

Page 52: ...uffer write read test The spindle motor starts Self diagnosis 1 MPU bus test Inner register write read test Work RAM write read test Start Power on Drive ready state command waiting state Execute self calibration Initial on track and read out of system information f e d End Figure 4 3 Power on operation sequence ...

Page 53: ...ation The measured values are stored in the SA cylinder In the self calibration the compensating value is updated using the value in the SA cylinder 2 Compensating open loop gain Torque constant value of the VCM has a dispersion for each drive and varies depending on the cylinder that the head is positioned To realize the high speed seek operation the value that compensates torque constant value c...

Page 54: ...utes About 60 minutes 4 About 30 minutes About 90 minutes 5 About 30 minutes About 120 minutes 6 About 30 minutes About 150 minutes 7 9 Every about 30 minutes 4 5 3 Command processing during self calibration If the disk drive receives a command execution request from the host while executing self calibration according to the timechart the disk drive terminates self calibration and starts executing...

Page 55: ...TA The IC generates a write error sense signal WUS when a write error occurs due to head short circuit or head disconnection 4 6 2 Write circuit The write data is output from the hard disk controller HDC with the NRZ data format and sent to the encoder circuit in the RDC with synchronizing with the write clock The NRZ write data is converted from 48 bits data to 51 bits data by the encoder circuit...

Page 56: ... high frequency boost up function that equalizes the waveform of the read signal Cut off frequency of the low pass filter and boost up gain are controlled from each DAC circuit in read channel by an instruction of the parallel data signal from MPU M1 The MPU optimizes the cut off frequency and boost up gain according to the transfer frequency of each zone 3 Adaptive equalizer circuit This circuit ...

Page 57: ...3 4 5 6 7 Cylinder 0 to 964 965 to 2150 2151 to 3580 3581 to 4790 4791 to 6120 6121 to 8030 8031 to 9440 9441 to 11210 Transfer rate MB s 34 44 34 44 34 44 34 44 33 41 31 83 30 59 28 71 Zone 8 9 10 11 12 13 14 Cylinder 11211 to 12170 12171 to 12590 12591 to 13430 13431 to 14430 14431 to 15860 15861 to 16660 16661 to 17300 Transfer rate MB s 27 68 27 14 26 10 24 80 22 96 21 93 20 36 The MPU transfe...

Page 58: ...rvo control circuit 1 Microprocessor unit MPU The MPU includes DSP unit etc and the MPU starts the spindle motor moves the heads to the reference cylinders seeks the specified cylinder and executes calibration according to the internal operations of the MPU The major internal operations are listed below a Spindle motor start Starts the spindle motor and accelerates it to normal speed when power is...

Page 59: ...he head to the specified cylinder d Calibration Senses and stores the thermal offset between heads and the mechanical forces on the actuator and stores the calibration value Figure 4 5 Physical sector servo configuration on disk surface Servo frame 96 servo frames per revolution ...

Page 60: ...mplifier feeds currents corresponding to the DAC output signal voltage to the VCM 6 Spindle motor control circuit The spindle motor control circuit controls the sensor less spindle motor This circuit detects number of revolution of the motor by the interrupt generated periodically compares with the target revolution speed then flows the current into the motor coil according to the differentiation ...

Page 61: ...a is used as the user data area and SA area 3 Outer guard band This area is located at outer position of the user data area and the rotational speed of the spindle can be controlled on this cylinder area for head moving 4 7 3 Servo frame format As the servo information the drive uses the two phase servo generated from the gray code and Pos A to D This servo information is used for positioning oper...

Page 62: ...SCD 0 84 µs Servo Frame DATA DATA Servo Frame 115 7 µs 7 98 µs Figure 4 6 96 servo frames in each track 1 Write read recovery This area is used to absorb the write read transient and to stabilize the AGC 2 Servo mark SMK1 SMK2 This area generates a timing for demodulating the gray code and position demodulating Pos A to D by detecting the servo mark ...

Page 63: ...pdates the VCM drive current The servo control of the actuator includes the operation to move the head to the reference cylinder the seek operation to move the head to the target cylinder to read or write data and the track following operation to position the head onto the target track 1 Operation to move the head to the reference cylinder The MPU moves the head to the reference cylinder when the ...

Page 64: ...he firmware 4 7 5 Spindle motor control Hall less three phase eight pole motor is used for the spindle motor and the 3 phase full half wave analog current control circuit is used as the spindle motor driver called SVC hereafter The firmware operates on the MPU manufactured by Fujitsu The spindle motor is controlled by sending several signals from the MPU to the SVC There are three modes for the sp...

Page 65: ... stable rotation mode 3 Stable rotation mode The MPU calculates a time for one revolution of the spindle motor based on the PHASE signal from the SVC The MPU takes a difference between the current time and a time for one revolution at 5 400 rpm that the MPU already recognized Then the MPU keeps the rotational speed to 5 400 rpm by charging or discharging the charge pump for the different time For ...

Page 66: ...C141 E093 01EN 5 1 CHAPTER 5 INTERFACE 5 1 Physical Interface 5 2 Logical Interface 5 3 Host Commands 5 4 Command Protocol 5 5 Ultra DMA feature set 5 6 Timing ...

Page 67: ... Data bus bit 12 DD12 Data bus bit 13 DD13 Data bus bit 14 DD14 Data bus bit 15 DD15 Device active or slave present see note DASP Device address bit 0 DA0 Device address bit 1 DA1 Device address bit 2 DA2 DMA acknowledge DMACK DMA request DMARQ Interrupt request INTRQ I O read DIOR DMA ready during Ultra DMA data in bursts HDMARDY Data strobe during Ultra DMA data out bursts HSTROBE I O ready IORD...

Page 68: ... GND GND CSEL GND reserved PDIAG CBLID DA2 CS1 GND signal I O Description RESET I Reset signal from the host This signal is low active and is asserted for a minimum of 25 µs during power on The device has a 10 kΩ pull up resistor on this signal DATA 0 15 I O Sixteen bit bi directional data bus between the host and the device These signals are used for data transfer DIOW STOP I DIOW is the strobe s...

Page 69: ...ster When the device is not selected or interrupt is disabled the INTRQ Signal shall be in a high impedance state CS0 I Chip select signal decoded from the host address bus This signal is used by the host to select the command block registers CS1 I Chip select signal decoded from the host address bus This signal is used by the host to select the control block registers DA 0 2 I Binary decoded addr...

Page 70: ...n the IDD is a slave device This signal is pulled up with 10 kΩ resistor DMACK I The host system asserts this signal as a response that the host system receive data or to indicate that data is valid DMARQ O This signal is used for DMA transfer between the host system and the device The device asserts this signal when the device completes the preparation of DMA data transfer to the host system at r...

Page 71: ...tor Number registers are LBA bits The sector No under the LBA mode proceeds in the ascending order with the start point of LBA0 defined as follows LBA0 Cylinder 0 Head 0 Sector 1 Even if the host system changes the assignment of the CHS mode by the INITIALIZE DEVICE PARAMETER command the sector LBA address is not changed LBA Cylinder No Number of head Head No Number of sector track Sector No 1 5 2...

Page 72: ...nd X 1F7 1 1 X X X Invalid Invalid Control block registers 0 1 1 1 0 Alternate Status Device Control X 3F6 0 1 1 1 1 X 3F7 Notes 1 The Data register for read or write operation can be accessed by 16 bit data bus DATA0 to DATA15 2 The registers for read or write operation other than the Data registers can be accessed by 8 bit data bus DATA0 to DATA7 3 When reading the Drive Address register bit 7 i...

Page 73: ... IDNF X ABRT TK0NF AMNF X Unused Bit 7 Interface CRC error ICRC This bit indicates that an interface CRC error has occurred during an Ultra DMA data transfer The content of this bit is not applicable for Multiword DMA transfers Bit 6 Uncorrectable Data Error UNC This bit indicates that an uncorrectable data error has been encountered Bit 5 Unused Bit 4 ID Not Found IDNF This bit indicates an error...

Page 74: ...ation between the host system and the device When the value in this register is X 00 the sector count is 256 When this register indicates X 00 at the completion of the command execution this indicates that the command is completed successfully If the command is not completed successfully this register indicates the number of sectors to be transferred to complete the request from the host system Th...

Page 75: ...h order 8 bits of the cylinder address are set to the Cylinder High register Under the LBA mode this register indicates LBA bits 23 to 16 8 Device Head register X 1F6 The contents of this register indicate the device and the head number When executing INITIALIZE DEVICE PARAMETERS command the contents of this register defines the number of heads minus 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit...

Page 76: ... ns after RESET is negated or SRST is set in the Device Control register the BSY bit is set the BSY bit is cleared when the reset process is completed The BSY bit is set for no longer than 15 seconds after the IDD accepts reset b Within 400 ns from the host system starts writing to the Command register c Within 5 µs following transfer of 512 bytes data during execution of the READ SECTOR S WRITE S...

Page 77: ...us command was being executed The Error register indicates the additional information of the cause for the error 10 Command register X 1F7 The Command register contains a command code being sent to the device After this register is written the command execution starts immediately Table 5 3 lists the executable commands and their command codes This table also lists the necessary parameters for each...

Page 78: ...sets both device simultaneously The slave device is not required to execute the DASP handshake Bit 1 nIEN bit enables an interrupt INTRQ signal from the device to the host When this bit is 0 and the device is selected an interruption INTRQ signal can be enabled through a tri state buffer When this bit is 1 or the device is not selected the INTRQ signal is in the high impedance state 5 3 Host Comma...

Page 79: ...Y WRITE SECTOR S 0 0 1 1 0 0 0 R N Y Y Y Y RECALIBRATE 0 0 0 1 X X X X N N N N D SEEK 0 1 1 1 X X X X N N Y Y Y INITIALIZE DEVICE DIAGNOSTIC 1 0 0 1 0 0 0 1 N Y N N Y IDENTIFY DEVICE 1 1 1 0 1 1 0 0 N N N N D IDENTIFY DEVICE DMA 1 1 1 0 1 1 1 0 N N N N D SET FEATURES 1 1 1 0 1 1 1 1 Y N N N D SET MULTIPLE MODE 1 1 0 0 0 1 1 0 N Y N N D EXECUTE DEVICE DIAGNOSTIC 1 0 0 1 0 0 0 0 N N N N D FORMAT TRA...

Page 80: ...SS 1 1 1 1 1 0 0 1 N Y Y Y Y READ NATIVE MAX ADDRESS 1 1 1 1 1 0 0 0 N N N N D Notes FR Features Register CY Cylinder Registers SC Sector Count Register DH Drive Head Register SN Sector Number Register R R 0 or 1 Y Necessary to set parameters Y Necessary to set parameters under the LBA mode N Necessary to set parameters The parameter is ignored if it is set N May set parameters D The device parame...

Page 81: ...A 1F3H SN Start sector No LBA LSB 1F2H SC Transfer sector count 1F1H FR xx At command completion I O registers contents to be read Bit 7 6 5 4 3 2 1 0 1F7H ST Error information 1F6H DH L DV End Head No LBA MSB 1F5H CH End cylinder address MSB LBA 1F4H CL End cylinder address LSB LBA 1F3H SN End sector No LBA LSB 1F2H SC X 00 1F1H ER Error information CM Command register FR Features register DH Dev...

Page 82: ... is not on the track specified by the host the device performs a implied seek After the head reaches to the specified track the device reads the target sector The DRQ bit of the Status register is always set prior to the data transfer regardless of an error condition Upon the completion of the command execution command block registers contain the cylinder head and sector addresses in the CHS mode ...

Page 83: ...ULTIPLE MODE command should be executed prior to the READ MULTIPLE command When the READ MULTIPLE command is issued the Sector Count register contains the number of sectors requested not a number of the block count or a number of sectors in a block Upon receipt of this command the device executes this command even if the value of the Sector Count register is less than the defined block count the v...

Page 84: ...xecution example of READ MULTIPLE command At command issuance I O registers setting contents 1F7H CM 1 1 0 0 0 1 0 0 1F6H DH L DV Start head No LBA MSB 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H FR Start cylinder No MSB LBA Start cylinder No LSB LBA Start sector No LBA LSB Transfer sector count xx At command completion I O registers contents to be read 1F7H ST Status information 1F6H DH L DV End head No...

Page 85: ...rror information is the same as the READ SECTOR S command In LBA mode The logical block address is specified using the start head No start cylinder No and first sector No fields At command completion the logical block address of the last sector and remaining number of sectors of which data was not transferred like in the CHS mode are set The host system can select the DMA transfer mode by using th...

Page 86: ... BSY bit of the Status register and generates an interrupt Upon the completion of the command execution the command block registers contain the cylinder head and sector number of the last sector verified If an error occurs the verify operation is terminated at the sector where the error occurred The command block registers contain the cylinder the head and the sector addresses in the CHS mode or t...

Page 87: ...by the host the device performs a implied seek After the head reaches to the specified track the device writes the target sector The data stored in the buffer and CRC code and ECC bytes are written to the data field of the corresponding sector s Upon the completion of the command execution the command block registers contain the cylinder head and sector addresses of the last sector written If an e...

Page 88: ... MODE command should be executed prior to the WRITE MULTIPLE command When the WRITE MULTIPLE command is issued the Sector Count register contains the number of sectors requested not a number of the block count or a number of sectors in a block Upon receipt of this command the device executes this command even if the value of the Sector Count register is less than the defined block count the value ...

Page 89: ... Error information Note When the command terminates due to error only the DV bit and the error information field are valid 7 WRITE DMA X CA or X CB This command operates similarly to the WRITE SECTOR S command except for following events The data transfer starts at the timing of DMARQ signal assertion The device controls the assertion or negation timing of the DMARQ signal The device posts a statu...

Page 90: ... 1F4H CL 1F3H SN 1F2H SC 1F1H ER End cylinder No MSB LBA End cylinder No LSB LBA End sector No LBA LSB 00 1 Error information 1 If the command is terminated due to an error the remaining number of sectors of which data was not transferred is set in this register 8 WRITE VERIFY X 3C This command operates similarly to the WRITE SECTOR S command except that the device verifies each sector immediately...

Page 91: ...0 to X F This command performs the calibration Upon receipt of this command the device sets BSY bit of the Status register and performs a calibration When the device completes the calibration the device updates the Status register clears the BSY bit and generates an interrupt This command can be issued in the LBA mode At command issuance I O registers setting contents 1F7H CM 0 0 0 1 x x x x 1F6H ...

Page 92: ...e this command performs the seek operation to the cylinder and head position in which the sector is specified with the logical block address At command issuance I O registers setting contents 1F7H CM 0 1 1 1 x x x x 1F6H DH L DV Head No LBA MSB 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H FR Cylinder No MSB LBA Cylinder No LSB LBA Sector No LBA LSB xx xx At command completion I O registers contents to be ...

Page 93: ...thin a default area It is recommended that the host system refers the addressable user sectors total number of sectors in word 60 to 61 of the parameter information by the IDENTIFY DEVICE command At command issuance I O registers setting contents 1F7H CM 1 0 0 1 0 0 0 1 1F6H DH DV Max head No 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H FR xx xx xx Number of sectors track xx At command completion I O regi...

Page 94: ...ntents 1F7H CM 1 1 1 0 1 1 0 0 1F6H DH DV xx 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H FR xx xx xx xx xx At command completion I O registers contents to be read 1F7H ST Status information 1F6H DH DV xx 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H ER xx xx xx xx Error information ...

Page 95: ...tly set by READ WRITE MULTIPLE command 60 61 11 Total number of user addressable sectors LBA mode only 62 X 0000 Retired 63 X xx07 Multiword DMA transfer mode 12 64 X 0003 Advance PIO transfer mode support status 13 65 X 0078 Minimum multiword DMA transfer cycle time per word 120 ns 66 X 0078 Manufacturer s recommended DMA transfer cycle time 120 ns 67 X 0078 Minimum PIO transfer cycle time withou...

Page 96: ...ing model numbers MPE3043AE MPE3084AE MPE3173AE 7 Word 49 Capabilities Bit 15 14 Reserved Bit 13 Standby timer value 0 Standby timer values shall be manage d by the device Bit 12 Reserved Bit 11 IORDY support 1 Supported Bit 10 IORDY inhibition 0 Disable inhibition Bit 9 LBA support 1 Supported Bit 8 DMA support 1 Supported Bit 7 0 Vendor specific 8 Word 51 PIO data transfer mode Bit 15 8 PIO data...

Page 97: ...d Buffer command supported 1 Bit 12 Write Buffer command supported 1 Bit 11 Write Verify command supported Old Spec 0 Bit 10 Host Protected Area feature command supported 1 Bit 9 Device Reset command supported 0 Bit 8 SERVICE Interrupt supported 0 Bit 7 Release Interrupt supported 0 Bit 6 Lock Ahead supported 1 Bit 5 Write cache supported 1 Bit 4 Packet command feature set supported 0 Bit 3 Power ...

Page 98: ...8 Word 86 Enable disable Command set feature enabled Bit 15 5 Reserved Bit 4 Removable Media Status Notification feature set enabled 0 Bit 3 Advanced Power Management feature set enabled 1 Bit 2 CFA feature set supported 0 Bit 1 READ WRITE DMA QUEUED command supported 0 Bit 0 DOWNLOAD MICROCODE command supported 0 19 Word 88 Ultra DMA modes Bit 15 13 Reserved Bit 12 8 Currently used Ultra DMA tran...

Page 99: ...formation 14 SET FEATURES X EF The host system issues the SET FEATURES command to set parameters in the Features register for the purpose of changing the device features to be executed For the transfer mode Feature register 03 detail setting can be done using the Sector Count register Upon receipt of this command the device sets the BSY bit of the Status register and saves the parameters in the Fe...

Page 100: ...e reset X 77 No operation X 81 No operation X 82 Disables the write cache function X 84 No operation X 85 Disable the advanced power management function X 88 No operation X 99 No operation X AA Enables the read cache function X AB No operation X BB Specifies the transfer of 4 byte ECC for READ LONG and WRITE LONG commands X CC Enables the reverting to power on default settings after software reset...

Page 101: ...e and lower 3 bits specifies the binary mode value However the IDD can operate with the PIO transfer mode 4 and multiword DMA transfer mode 2 regardless of reception of the SET FEATURES command for transfer mode setting The IDD supports following values in the Sector Count register value If other value than below is specified an ABORTED COMMAND error is posted PIO default transfer mode 00000 000 X...

Page 102: ... enabled If the value of the Sector Count register is not a supported block count an ABORTED COMMAND error is posted and the READ MULTIPLE and WRITE MULTIPLE commands are disabled If the contents of the Sector Count register is 0 when the SET MULTIPLE MODE command is issued the READ MULTIPLE and WRITE MULTIPLE commands are disabled When the SET MULTIPLE MODE command operation is completed the devi...

Page 103: ... DRV bit of the Drive Head register is to 0 however the DV bit is not checked If two devices are present both devices execute self diagnosis If device 1 is present Both devices shall execute self diagnosis The device 0 waits for up to 5 seconds until device 1 asserts the PDIAG signal If the device 1 does not assert the PDIAG signal but indicates an error the device 0 shall append X 80 to its own d...

Page 104: ...ompletion of 512 byte format parameter transfer from the host system After completion of transfer the device clears the DRQ bits sets the BSY bit However the device does not perform format operation but the drive clears the BYS bit and generates an interrupt soon When the command execution completes the device clears the BSY bit and generates an interrupt The drive supports this command for keep t...

Page 105: ...or No LBA LSB 00 1 Error information 1 If the command is terminated due to an error this register indicates 01 19 WRITE LONG X 32 or X 33 This command operates similarly to the READ SECTOR S command except that the device writes the data and the ECC bytes transferred from the host system to the disk medium The device does not generate ECC bytes by itself The WRITE LONG command supports only single...

Page 106: ...LBA LSB 00 1 Error information 1 If the command is terminated due to an error this register indicates 01 20 READ BUFFER X E4 The host system can read the current contents of the sector buffer of the device by issuing this command Upon receipt of this command the device sets the BSY bit of Status register and sets up the sector buffer for a read operation Then the device sets the DRQ bit of Status ...

Page 107: ...it of the Status register Then the device sets the DRQ bit of Status register and clears the BSY bit when the device is ready to receive the data After that 512 bytes of data is transferred from the host and the device writes the data to the sector buffer then generates an interrupt At command issuance I O registers setting contents 1F7H CM 1 1 1 0 1 0 0 0 1F6H DH DV xx 1F5H CH 1F4H CL 1F3H SN 1F2...

Page 108: ...wn function means that the device automatically enters the standby mode after a certain period of time When the device enters the idle mode the timer starts countdown If any command is not issued while the timer is counting down the device automatically enters the standby mode If any command is issued while the timer is counting down the timer is initialized and the command is executed The timer r...

Page 109: ... the Status register and enters the idle mode Then the device clears the BSY bit and generates an interrupt This command does not support the automatic power down function At command issuance I O registers setting contents 1F7H CM X 95 or X E1 1F6H DH DV xx 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H FR xx xx xx xx xx At command completion I O registers contents to be read 1F7H ST Status information 1F6H...

Page 110: ... the Sector Count register is 0 the automatic power down function is disabled Under the standby mode the spindle motor is stopped Thus when the command involving a seek such as the READ SECTOR s command is received the device processes the command after driving the spindle motor At command issuance I O registers setting contents 1F7H CM X 96 or X E2 1F6H DH DV xx 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F...

Page 111: ...ceipt of this command the device sets the BSY bit of the Status register and enters the sleep mode The device then clears the BSY bit and generates an interrupt The device generates an interrupt even if the device has not fully entered the sleep mode In the sleep mode the spindle motor is stopped and the ATA interface section is inactive All I O register outputs are in high impedance state The onl...

Page 112: ...is command The host system can confirm the power save mode of the device by analyzing the contents of the Sector Count and Sector Number registers The device sets the BSY bit and sets the following register value After that the device clears the BSY bit and generates an interrupt Power save mode Sector Count register Sector Number register During moving to standby mode Standby mode During returnin...

Page 113: ...edictions according to a subcommand specified in the FR register If the value specified in the FR register is supported the Aborted Command error is posted It is necessary for the host to set the keys CL 4Fh and CH C2h in the CL and CH registers prior to issuing this command If the keys are set incorrectly the Aborted Command error is posted In the default setting the failure prediction feature is...

Page 114: ...ice receives this subcommand it asserts the BSY bit enables or disables the automatic saving feature then clears the BSY bit X D3 SMART Save Attribute Values When the device receives this subcommand it asserts the BSY bit saves device attribute value data then clears the BSY bit X D4 SMART Executive Off line Immediate A device which receives this command asserts the BSY bit then starts collecting ...

Page 115: ...he device compares the device attribute values with insurance failure threshold values If there is an attribute value exceeding the threshold F4h and 2Ch are loaded into the CL and CH registers If there are no attribute values exceeding the thresholds 4Fh and C2h are loaded into the CL and CH registers After the settings for the CL and CH registers have been determined the device clears the BSY bi...

Page 116: ...nd completion I O registers setting contents 1F7H ST Status information 1F6H DH DV xx 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H ER Key failure prediction status C2h 2Ch Key failure prediction status 4Fh F4h xx xx Error information The attribute value information is 512 byte data the format of this data is shown below The host can access this data using the SMART Read Attribute Values subcommand FR regi...

Page 117: ...attribute 30 The format of each attribute value is the same as that of bytes 02 to 0D 16A Off line data collection status 16B Self test execution status 16C 16D Off line data collection execution time sec 16E Reserved 16F Off line data collection capability 170 171 Trouble prediction capability flag 172 Error logging capability 173 Vendor unique 174 Simple self test execution time min 175 Comprehe...

Page 118: ...ibute values or insurance failure thresholds The data format version numbers of the device attribute values and insurance failure thresholds are the same When a data format is changed the data format version numbers are updated Attribute ID The attribute ID is defined as follows Attribute ID Attribute name 0 Indicates unused attribute data 1 Read error rate 2 Throughput performance 3 Spin up time ...

Page 119: ...ue gets to 01h the higher the possibility of a failure The device compares the attribute values with thresholds When the attribute values are larger than the thresholds the device is operating normally Attribute value for the worst case so far This is the worst attribute value among the attribute values collected to date This value indicates the state nearest to a failure so far Raw attribute valu...

Page 120: ... completed abnormally by read test 8 to 14 Reserved 15 Self test is in progress Off line data collection capability Indicates the method of off line data collection carried out by the drive If the off line data collection capability is 0 it indicates that off line data collection is not supported Bit Meaning 0 Indicates that Execute Off Line Immediate is supported 1 Vendor unique 2 Indicates that ...

Page 121: ...mputer can issue the SMART Read Log Sector sub command FR register D5h SN register 01h and read the SMART error log Table 5 11 SMART error log data format 1 2 Byte Item 00 Error log version number 01 The most recent Error Log point 02 to 31 Reserved 32 Device Control register 33 Features register 34 Sector Count register 35 Sector Number register 36 Cylinder Low register 37 Cylinder High register ...

Page 122: ...x value is incremented and information at the time the error occurred is recorded in the error log area specified by this value When the error log index exceeds 05 it returns to 01 Command data 1 to 5 Indicates five commands data in order received by the device until the error occurs Commands for which an error occurred are included in Command Data 5 Error data Indicates the I O register values wh...

Page 123: ...ART self test log Table 5 12 SMART self test log data format Byte Item 00 01 Self test log data format version number 02 Self test log 1 Self test mode SN Register Value 03 Self test execution status 04 05 Total power on time until the self test is completed hours 06 Self test error No 07 to 0A Error LBA 0B to 19 Vendor unique 1A to 1F9 Self test log 2 to 21 Each log data format is the same as tha...

Page 124: ...ter power on and the occurrence of a hard reset When the VV bit is 0 the value set by this command becomes invalid when the power is turned on or a hard reset occurs and the maximum address returns to the value default value if not set most lately set when VV bit 1 After power on and the occurrence of a hard reset the host can issue this command only once when VV bit 1 If this command with VV bit ...

Page 125: ...H CH CL and SN registers Then it clears BSY and generates an interrupt At command issuance I O registers setting contents 1F7H CM 1 1 1 1 1 0 0 0 1F6H DH L DV xx 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H FR xx xx xx xx xx At command completion I O registers contents to be read 1F7H ST Status information 1F6H DH DV Max head LBA MSB 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H ER Max cylinder MSB Max LBA Max cyl...

Page 126: ...RIFY SECTOR S V V V V V V RECALIBRATE V V V V V SEEK V V V V V INITIALIZE DEVICE PARAMETERS V V V V IDENTIFY DEVICE V V V V IDENTIFY DEVICE DMA V V V V SET FEATURES V V V V SET MULTIPLE MODE V V V V EXECUTE DEVICE DIAGNOSTIC V FORMAT TRACK V V V V V READ LONG V V V V V WRITE LONG V V V V V READ BUFFER V V V V WRITE BUFFER V V V V IDLE V V V V IDLE IMMEDIATE V V V V STANDBY V V V V STANDBY IMMEDIAT...

Page 127: ...rameters to the Features Sector Count Sector Number Cylinder and Device Head registers b The host writes a command code to the Command register c The device sets the BSY bit of the Status register and prepares for data transfer d When one sector or block of data is available for transfer to the host the device sets DRQ bit and clears BSY bit The drive then asserts INTRQ signal e After detecting th...

Page 128: ...lection INTRQ DRQ Min 30 µs 1 Expanded Command f d d e e c b a Command BSY INTRQ DRDY Parameter write DRQ Data transfer Figure 5 2 Read Sector s command protocol Even if the error status exists the drive makes a preparation setting the DRQ bit of data transfer It is up to the host whether data is transferred In other words the host should receive the data of the sector 512 bytes of uninsured dummy...

Page 129: ...on is not guaranteed Transfers dummy data The host should receive 512 byte dummy data or release the DRQ set state by resetting Status read Command BSY INTRQ DRDY Parameter write DRQ Data transfer Figure 5 3 Protocol for command abort 5 4 2 Data transferring commands from host to device The execution of the following commands involves Data transfer from the host to the drive FORMAT TRACK WRITE SEC...

Page 130: ...r is requested the drive sets the DRQ bit g After detecting the INTRQ signal assertion the host reads the Status register h The device resets INTRQ the interrupt signal I If transfer of another sector is requested steps d and after are repeated Figure 5 4 shows an example of WRITE SECTOR S command protocol and Figure 5 3 shows an example protocol for command abort Status read Status read 255 2 1 0...

Page 131: ...ansfer DRQ bit is set or when the host executes resetting the device correct operation is not guaranteed 5 4 3 Commands without data transfer Execution of the following commands does not involve data transfer between the host and the device RECALIBRATE SEEK READY VERIFY SECTOR S EXECUTE DEVICE DIAGNOSTIC INITIALIZE DEVICE PARAMETERS SET FEATURES SET MULTIPLE MODE IDLE IDLE IMMEDIATE STANDBY STANDB...

Page 132: ...ing for the DMA transfer differs the following point a The host writes any parameters to the Features Sector Count Sector Number Cylinder and Device Head register b The host initializes the DMA channel c The host writes a command code in the Command register d The device sets the BSY bit of the Status register e The device asserts the DMARQ signal after completing the preparation of data transfer ...

Page 133: ... E093 01EN 5 68 Status read Expanded g f e c d a Command BSY INTRQ DRDY Parameter write DRQ Data transfer DRQ Multiword DMA transfer DMACK DMARQ IOR or IOW 0 1 Word n 1 n Figure 5 6 Normal DMA data transfer ...

Page 134: ...s of STROBE are used for data transfers so that the frequency of STROBE is limited to the same frequency as the data The highest fundamental frequency on the cable shall be 16 67 million transitions per second or 8 33 MHz the same as the maximum frequency for PIO Mode 4 and DMA Mode 2 Words in the IDENTIFY DEVICE data indicate support of the Ultra DMA feature and the Ultra DMA Modes the device is ...

Page 135: ...ts 1 The host shall keep DMACK in the negated state before an Ultra DMA burst is initiated 2 The device shall assert DMARQ to initiate an Ultra DMA burst After assertion of DMARQ the device shall not negate DMARQ until after the first negation of DSTROBE 3 Steps 3 4 and 5 may occur in any order or at the same time The host shall assert STOP 4 The host shall negate HDMARDY 5 The host shall negate C...

Page 136: ... DD 15 0 until at least tDVH after generating a DSTROBE edge to latch the data 4 The device shall repeat steps 1 2 and 3 until the data transfer is complete or an Ultra DMA burst is paused whichever occurs first 5 5 3 3 Pausing an Ultra DMA data in burst The following steps shall occur in the order they are listed unless otherwise specifically allowed see 5 6 3 4 and 5 6 3 2 for specific timing re...

Page 137: ...ated 3 The device shall release DD 15 0 no later than tAZ after negating DMARQ 4 The host shall assert STOP within tLI after the device has negated DMARQ The host shall not negate STOP again until after the Ultra DMA burst is terminated 5 The host shall negate HDMARDY within tLI after the device has negated DMARQ The host shall continue to negate HDMARDY until the Ultra DMA burst is terminated Ste...

Page 138: ... device shall stop generating DSTROBE edges within tRFS of the host negating HDMARDY 4 If the host negates HDMARDY within tSR after the device has generated a DSTROBE edge then the host shall be prepared to receive zero or one additional data words If the host negates HDMARDY greater than tSR after the device has generated a DSTROBE edge then the host shall be prepared to receive zero one or two a...

Page 139: ...assert DIOR CS0 CS1 DA2 DA1 or DA0 until at least tACK after negating DMACK 5 5 4 Ultra DMA data out commands 5 5 4 1 Initiating an Ultra DMA data out burst The following steps shall occur in the order they are listed unless otherwise specifically allowed see 5 6 3 7 and 5 6 3 2 for specific timing requirements 1 The host shall keep DMACK in the negated state before an Ultra DMA burst is initiated...

Page 140: ...an tCYC for the selected Ultra DMA Mode The host shall not generate two rising or falling HSTROBE edges more frequently than 2 tCYC for the selected Ultra DMA mode 3 The host shall not change the state of DD 15 0 until at least tDVH after generating an HSTROBE edge to latch the data 4 The host shall repeat steps 1 2 and 3 until the data transfer is complete or an Ultra DMA burst is paused whicheve...

Page 141: ...c timing requirements 1 The host shall initiate termination of an Ultra DMA burst by not generating HSTROBE edges 2 The host shall assert STOP no sooner than tSS after it last generated an HSTROBE edge The host shall not negate STOP again until after the Ultra DMA burst is terminated 3 The device shall negate DMARQ within tLI after the host asserts STOP The device shall not assert DMARQ again unti...

Page 142: ...s generated an HSTROBE edge then the device shall be prepared to receive zero or one additional data words If the device negates DDMARDY greater than tSR after the host has generated an HSTROBE edge then the device shall be prepared to receive zero one or two additional data words The additional data words are a result of cable round trip delay and tRFS timing for the host 5 The device shall negat...

Page 143: ...lculated for the return of STROBE to the asserted state after the Ultra DMA burst termination request has been acknowledged e At the end of any Ultra DMA burst the host shall send the results of its CRC calculation function to the device on DD 15 0 with the negation of DMACK f The device shall then compare the CRC data from the host with the calculated value in its own CRC calculation function If ...

Page 144: ...ribes recommended values for series termination at the host and the device Table 5 14 Recommended series termination for Ultra DMA Signal Host Termination Device Termination DIOR HDMARDY HSTROBE 33 ohm 120 ohm A I 1 DIOW STOP 33 ohm 82 ohm CS0 CS1 33 ohm 82 ohm DA0 DA1 DA2 33 ohm 82 ohm DMACK 33 ohm 82 ohm DD15 through DD0 33 ohm 240 ohm A I 1 DMARQ 82 ohm 22 ohm INTRQ 82 ohm 22 ohm IORDY DDMARDY ...

Page 145: ...er selection setup time for DIOR DIOW 25 ns t2 Pulse width of DIOR DIOW 70 ns t2i Recovery time of DIOR DIOW 25 ns t3 Data setup time for DIOW 20 ns t4 Data hold time for DIOW 10 ns t5 Time from DIOR assertion to read data available 50 ns t6 Data hold time for DIOR 5 ns t9 Data register selection hold time for DIOR DIOW 10 ns t10 Time from DIOR DIOW assertion to IORDY low level 35 ns t11 Time from...

Page 146: ...parameter Min Max Unit t0 Cycle time 120 ns tC Delay time from DMACK assertion to DMARQ negation 35 ns tD Pulse width of DIOR DIOW 70 ns tE Data setup time for DIOR 30 ns tF Data hold time for DIOR 5 ns tG Data setup time for DIOW 20 ns tH Data hold time for DIOW 10 ns tI DMACK setup time for DIOR DIOW 0 ns tJ DMACK hold time for DIOR DIOW 5 ns tK Continuous time of high level for DIOR DIOW 25 ns ...

Page 147: ...ntains the values for the timings for each of the Ultra DMA Modes 5 6 3 1 Initiating an Ultra DMA data in burst 5 6 3 2 contains the values for the timings for each of the Ultra DMA Modes Note The definitions for the STOP HDMARDY and DSTROBE signal lines are not in effect until DMARQ and DMACK are asserted Figure 5 10 Initiating an Ultra DMA data in burst ...

Page 148: ...FS 0 230 0 200 0 170 0 130 0 120 First STROBE time for device to first negate DSTROBE from STOP during a data in burst tLI 0 150 0 150 0 150 0 100 0 100 Limited interlock time see Note 3 tMLI 20 20 20 20 20 Interlock time with minimum see Note 3 tUI 0 0 0 0 0 Unlimited interlock time see Note 3 tAZ 10 10 10 10 10 Maximum time allowed for output drivers to release from asserted or negated tZAH 20 2...

Page 149: ...all stop generating STROBE edges t RFS after the negation of DMARDY Both STROBE and DMARDY timing measurements are taken at the connector of the sender 2 All timing measurement switching points low to high and high to low shall be taken at 1 5 V 3 tUI tMLI and tLI indicate sender to recipient or recipient to sender interlocks i e one agent either sender or recipient is waiting for the other agent ...

Page 150: ... Ultra DMA Modes Note DD 15 0 and DSTROBE are shown at both the host and the device to emphasize that cable setting time as well as cable propagation delay shall not allow the data signals to be considered stable at the host until some time after they are driven by the device Figure 5 11 Sustained Ultra DMA data in burst ...

Page 151: ... for each of the Ultra DMA Modes Notes 1 The host may assert STOP to request termination of the Ultra DMA burst no sooner than tRP after HDMARDY is negated 2 If the tSR timing is not satisfied the host may receive zero one or two more data words from the device Figure 5 12 Host pausing an Ultra DMA data in burst ...

Page 152: ...in burst 5 6 3 2 contains the values for the timings for each of the Ultra DMA Modes Note The definitions for the STOP HDMARDY and DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated Figure 5 13 Device terminating an Ultra DMA data in burst ...

Page 153: ...in burst 5 6 3 2 contains the values for the timings for each of the Ultra DMA Modes Note The definitions for the STOP HDMARDY and DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated Figure 5 14 Host terminating an Ultra DMA data in burst ...

Page 154: ... out burst 5 6 3 2 contains the values for the timings for each of the Ultra DMA Modes Note The definitions for the STOP DDMARDY and HSTROBE signal lines are not in effect until DMARQ and DMACK are asserted Figure 5 15 Initiating an Ultra DMA data out burst ...

Page 155: ...ra DMA Modes Note DD 15 0 and HSTROBE signals are shown at both the device and the host to emphasize that cable setting time as well as cable propagation delay shall not allow the data signals to be considered stable at the device until some time after they are driven by the host Figure 5 16 Sustained Ultra DMA data out burst ...

Page 156: ...or each of the Ultra DMA Modes Notes 1 The device may negate DMARQ to request termination of the Ultra DMA burst no sooner than tRP after DDMARDY is negated 2 If the tSR timing is not satisfied the device may receive zero one or two more data words from the host Figure 5 17 Device pausing an Ultra DMA data out burst ...

Page 157: ...ut burst 5 6 3 2 contains the values for the timings for each of the Ultra DMA Modes Note The definitions for the STOP DDMARDY and HSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated Figure 5 18 Host terminating an Ultra DMA data out burst ...

Page 158: ...in burst 5 6 3 2 contains the values for the timings for each of the Ultra DMA Modes Note The definitions for the STOP DDMARDY and HSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated Figure 5 19 Device terminating an Ultra DMA data out burst ...

Page 159: ...et 2 Master and slave devices are present 2 drives configuration tP Clear Reset Slave device Master device tN DASP PDIAG BSY BSY DASP tQ tR tS Symbol Timing parameter Min Max Unit tM Pulse width of RESET 25 µs tN Time from RESET negation to BSY set 400 ns tP Time from RESET negation to DASP or DIAG negation 1 ms tQ Self diagnostics execution time 30 s tR Time from RESET negation to DASP assertion ...

Page 160: ...Address Translation 6 3 Power Save 6 4 Defect Management 6 5 Read Ahead Cache 6 6 Write Cache 6 1 Device Response to the Reset This section describes how the PDIAG and DASP signals responds when the power of the IDD is turned on or the IDD receives a reset or diagnostic command ...

Page 161: ...vice is connected After the slave device device 1 releases its own power on reset state the slave device shall report its presence and the result of power on diagnostics to the master device as described below DASP signal Asserted within 400 ms and negated after the first command is received from the host or within 31 seconds or after executing software reset which ever comes first PDIAG signal Ne...

Page 162: ...e master device recognizes that no slave device is connected After the slave device receives the hardware reset the slave device shall report its presence and the result of the self diagnostics to the master device as described below DASP signal Asserted within 400 ms and negated after the first command is received from the host or within 31 seconds or after executing software reset which ever com...

Page 163: ... presence and the result of the self diagnostics to the master device as described below PDIAG signal negated within 1 ms and asserted within 30 seconds then negated within 31 seconds When the IDD is set to a slave device the IDD asserts the DASP signal when negating the PDIAG signal and negates the DASP signal when asserting the PDIAG signal Max 31 sec Max 30 sec Max 1 ms If the slave device is p...

Page 164: ...CE DIAGNOSTIC command it shall report the result of the self diagnostics to the master device as described below PDIAG signal negated within 1 ms and asserted within 5 seconds then negated within 6 seconds When the IDD is set to a slave device the IDD asserts the DASP signal when negating the PDIAG signal and negates the DASP signal when asserting the PDIAG signal Max 6 sec Max 5 sec Max 1 ms If t...

Page 165: ...ult translation mode The parameters in Table 6 1 are called BIOS specification Table 6 1 Default parameters MPE3043AE MPE3084AE MPE3173AE Number of cylinders 8 959 16 383 Number of head 15 16 Number of sectors track 63 Formatted capacity GB 4 33 8 45 17 34 As long as the formatted capacity of the IDD does not exceed the value shown on Table 6 1 the host can freely specify the number of cylinders h...

Page 166: ...e logical sector from the last sector of the current physical sector Figure 6 5 shows an example assuming there is no track skew LS 63 LH2 LH1 LH0 LS 2 LS 1 LS 1 576 575 574 190 189 64 63 62 3 2 57 56 1 1 127 126 Physical sector Physical sector ex Zone 0 Physical parameter Physical sector 1 to 574 For the rest 2 spare sectors Specification of INITIALIZE DEVICE PARAMETERS command Logical head LH 0 ...

Page 167: ...ysical sector ex Zone 0 Physical parameter Physical sector 1 to 574 For the rest 2 spare sectors Physical cylinder 0 Physical head 0 SP SP LBA 1147 LBA 1146 3 2 1 Physical cylinder 0 Physical head 1 LBA 576 LBA 575 LBA 574 576 575 574 573 576 575 Figure 6 6 Address translation example in LBA mode 6 3 Power Save The host can change the power consumption state of the device by issuing a power comman...

Page 168: ...ut Seek or Write or Read is issued 3 Standby mode In this mode the VCM circuit is turned off and the spindle motor is stopped The device can receive commands through the interface However if a command with disk access is issued response time to the command under the standby mode takes longer than the active or Idle mode because the access to the disk medium cannot be made immediately The drive ent...

Page 169: ...he following condition A SLEEP command is issued Issued commands are invalid ignored in this mode 6 3 2 Power commands The following commands are available as power commands IDLE IDLE IMMEDIATE STANDBY STANDBY IMMEDIATE SLEEP CHECK POWER MODE 6 4 Defect Management Defective sectors of which the medium defect location is registered in the system space are replaced with spare sectors in the formatti...

Page 170: ...ernating defective sectors The two alternating methods described below are available 1 Sector slip processing A defective sector is not used and is skipped and a logical sector address is assigned to the subsequent normal sector physically adjacent sector to the defective sector When defective sector is present the sector slip processing is performed in the formatting Figure 6 7 shows an example w...

Page 171: ...ified the device seeks to cylinder 0 head 0 and continues the processing Defective sector is assigned to unassigned sector unused Sector logical Sector physical Alternate cylinder 2 1 4 3 6 7 299 298 Figure 6 8 Alternate cylinder assignment 3 Automatic alternate assignment The device performs the automatic assignment at following case 1 Automatic alternate assignment is done when a read error is r...

Page 172: ...st can access the data at higher speed 6 5 1 Data buffer configuration The device has a 512 KB data buffer The buffer is used by divided into two and other commands parts for MPU work for read cache of read commands and other commands see Figure 6 9 for WRITE command for READ command for MPU work 305 KB 312 832 bytes 63 KB 64 512 bytes 512 KB 524 288 bytes 132 KB 135 168 bytes Figure 6 9 Data buff...

Page 173: ...object of caching operation The following data are object of caching operation 1 Read ahead data read from the disk medium in the data buffer after completion of the command that are object of caching operation 2 Data transferred to the host system once by requesting with the command that are object of caching operation When the sector data requested by the host does not finish storing in the buff...

Page 174: ...ment Segment only for read DAP HAP 2 Transfers the requested data that already read to the host system with reading the requested data from the disk media Read requested data Stores the read requested data upto this point Empty area DAP HAP 3 After reading the requested data and transferring the requested data to the host system had been completed the disk drive continues to read till a certain am...

Page 175: ... DAP and HAP to the sequential address of the last read command and reads the requested data Empty data Mis hit data 2 The disk drive transfers the requested data that is already read to the host system with reading the requested data Requested data DAP HAP Mis hit data Empty data 3 After completion of the reading and transferring the requested data to the host system the disk drive performs the r...

Page 176: ...sferring data to the host system 1 In the case that the contents of buffer is as follows at receiving a read command Start LBA Last LBA DAP HAP Completion of transferring requested data Hit data Read ahead data 2 The disk drive starts the read ahead operation to the empty area that becomes vacant by data transfer at the same time as the disk drive starts transferring hit data DAP HAP Hit data New ...

Page 177: ...s for example and the previous command is a sequential read command the disk drive sets the HAP to the address of which the hit data is stored HAP set to hit position for data transfer Last position at previous read command Last position at previous read command Cache data Full hit data Cache data 2 The disk drive transfers the requested data but does not perform the read ahead operation stopped H...

Page 178: ...tored and sets the DAP to the address just after the partially hit data HAP DAP Partially hit data Lack data 2 The disk drive starts transferring partially hit data and reads lack data from the disk media at the same time stopped HAP Requested data to be transferred DAP Partially hit data Lack data ...

Page 179: ...vious command had been completed the latency time occurs to search the target sector If the received command is not a sequential write the drive receives data of sectors requested by the host system as same as sequential write The drive generates the interrupt of command complete after completion of data transfer requested by the host system Received data is processed after completion of the write...

Page 180: ...n is enabled the transferred data from the host by the WRITE SECTOR S is not completely written on the disk medium at the time that the interrupt of command complete is generated When the unrecoverable error occurs during the write operation the command execution is stopped Then when the drive receives the next command it generates an interrupt of abnormal end However an interrupt of abnormal end ...

Page 181: ... Almagro 40 28010 Madrid SPAIN TEL 34 91 681 8100 FAX 34 91 681 8125 FUJITSU AUSTRALIA LIMITED 2 Julius Avenue Cnr Delhi Road North Ryde N S W 2113 AUSTRALIA TEL 61 2 9776 4555 FAX 61 2 9776 4556 FUJITSU HONG KONG LTD 10 F Lincoln House 979 King s Road Taikoo Place Island East Hong Kong TEL 852 2827 5780 FAX 852 2827 4724 FUJITSU KOREA LTD Coryo Finance Center Bldg 23 6 YoulDo Dong Young DungPo Gu...

Page 182: ...of this publication What is your occupation Your other comments may be entered here Please be specific and give page paragraph and line number references where applicable Your Name Return Address Sales Operating Installing Maintaining Learning Reference Fair Poor Very Good Good Very Poor Fully covered Well Illustrated Thank you for your interest Please send this sheet to one of the addresses in a ...

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