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Fujitsu MPC3032AT, Product Manual

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Fujitsu MPC3032AT Product Manual Download Page 109

C141-E055-01EN

5 - 46

At command completion (I/O registers contents to be read)

1F7

H

(ST)

Status information

1F6

H

(DH)

×

×

×

DV

xx

1F5

H

(CH)

1F4

H

(CL)

1F3

H

(SN)

1F2

H

(SC)

1F1

H

(ER)

xx
xx
xx
xx

Error information

(27)

CHECK POWER MODE (X'98' or X'E5')

The host checks the power mode of the device with this command.

The host system can confirm the power save mode of the device by analyzing the contents of
the Sector Count and Sector registers.

The device sets the BSY bit and sets the following register value.  After that, the device clears
the BSY bit and generates an interrupt.

Power save mode

Sector Count register

Sector Number register

•  During moving to standby mode
•  Standby mode
•  During returning from the standby mode

X'00'

X'xx'

X'00'

X'FF'

X'FF'

•  Idle mode
•  Active mode

Summary of Contents for MPC3032AT

Page 1: ...C141 E055 03EN MPC3032AT MPC3043AT MPC3064AT MPC3084AT MPC3096AT MPC3102AT DISK DRIVES PRODUCT MANUAL ...

Page 2: ... 02 July 1998 Information related to MPC3102AT added 03 Dec 1998 Pages 1 4 1 9 4 13 to 4 20 5 30 5 31 5 48 5 49 5 73 6 8 to 6 10 revised Specification No C141 E055 EN The contents of this manual is subject to change without prior notice All Rights Reserved Copyright 1998 FUJITSU LIMITED ...

Page 3: ...This page is intentionally left blank ...

Page 4: ...incorporate the hard disk drives into user systems This manual assumes that users have a basic knowledge of hard disk drives and their application in computer systems This manual consists of the following six chapters Chapter 1 DEVICE OVERVIEW Chapter 2 DEVICE CONFIGURATION Chapter 3 INSTALLATION CONDITIONS Chapter 4 THEORY OF DEVICE OPERATION Chapter 5 INTERFACE Chapter 6 OPERATIONS In this manua...

Page 5: ...situation could result in minor or moderate personal injury if the user does not perform the procedure correctly This alert signal also indicates that damages to the product or other property may occur if the user does not perform the procedure correctly This indicates information that could help the user use the product more efficiently In the text the alert signal is centered followed below by t...

Page 6: ...e adjustment repair or replacement Fujitsu is not liable for any other disk drive defects such as those caused by user misoperation or mishandling inappropriate operating environments defects in the power supply or cable problems of the host system or other causes outside the disk drive ...

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Page 8: ... Noise 1 8 1 6 Shock and Vibration 1 9 1 7 Reliability 1 9 1 8 Error Rate 1 10 1 9 Media Defects 1 10 CHAPTER 2 DEVICE CONFIGURATION 2 1 2 1 Device Configuration 2 1 2 2 System Configuration 2 4 2 2 1 ATA interface 2 4 2 2 2 1 drive connection 2 4 2 2 3 2 drives connection 2 5 CHAPTER 3 INSTALLATION CONDITIONS 3 1 3 1 Dimensions 3 1 3 2 Mounting 3 3 3 3 Cable Connections 3 7 3 3 1 Device connector...

Page 9: ... Execution timing of self calibration 4 9 4 5 3 Command processing during self calibration 4 9 4 6 Read write Circuit 4 10 4 6 1 Read write preamplifier PreAMP 4 10 4 6 2 Write circuit 4 10 4 6 3 Read circuit 4 12 4 6 4 Time base generator circuit 4 13 4 7 Servo Control 4 14 4 7 1 Servo control circuit 4 14 4 7 2 Data surface servo format 4 16 4 7 3 Servo frame format 4 17 4 7 4 Actuator motor con...

Page 10: ...urst 5 64 5 5 3 2 The data in transfer 5 65 5 5 3 3 Pausing an Ultra DMA data in burst 5 65 5 5 3 4 Terminating an Ultra DMA data in burst 5 66 5 5 4 Ultra DMA data out commands 5 68 5 5 4 1 Initiating an Ultra DMA data out burst 5 68 5 5 4 2 The data out transfer 5 69 5 5 4 3 Pausing an Ultra DMA data out burst 5 69 5 5 4 4 Terminating an Ultra DMA data out burst 5 70 5 5 5 Ultra DMA CRC rules 5 ...

Page 11: ...er on and reset 5 90 CHAPTER 6 OPERATIONS 6 1 6 1 Device Response to the Reset 6 1 6 1 1 Response to power on 6 2 6 1 2 Response to hardware reset 6 3 6 1 3 Response to software reset 6 4 6 1 4 Response to diagnostic command 6 5 6 2 Address Translation 6 6 6 2 1 Default parameters 6 6 6 2 2 Logical address 6 7 6 3 Power Save 6 8 6 3 1 Power save mode 6 8 6 3 2 Power commands 6 10 6 4 Defect Manage...

Page 12: ... 3 9 3 10 Jumper location 3 9 3 11 Factory default setting 3 10 3 12 Jumper setting of master or slave device 3 10 3 13 Jumper setting of Cable Select 3 11 3 14 Example 1 of Cable Select 3 11 3 15 Example 2 of Cable Select 3 11 4 1 Head structure 4 2 4 2 MPC30xxAT Block diagram 4 5 4 3 Power on operation sequence 4 7 4 4 Read write circuit block diagram 4 11 4 5 Block diagram of servo control circ...

Page 13: ... burst 5 83 5 16 Host terminating an Ultra DMA data in burst 5 84 5 17 Initiating an Ultra DMA data out burst 5 85 5 18 Sustained Ultra DMA data out burst 5 86 5 19 Device pausing an Ultra DMA data out burst 5 87 5 20 Host terminating an Ultra DMA data out burst 5 88 5 21 Device terminating an Ultra DMA data out burst 5 89 5 22 Power on Reset Timing 5 90 6 1 Response to power on 6 2 6 2 Response t...

Page 14: ...ncy and transfer rate of each zone 4 13 5 1 Signal assignment on the interface connector 5 3 5 2 I O registers 5 7 5 3 Command code and parameters 5 14 5 4 Information to be read by IDENTIFY DEVICE command 5 30 5 5 Features register values and settable modes 5 34 5 6 Diagnostic code 5 37 5 7 Features register values subcommands and functions 5 48 5 8 Format of device attribute value data 5 50 5 9 ...

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Page 16: ...disk drive is compact and reliable 1 1 Features 1 1 1 Functions and performance 1 Compact The disk has 1 2 or 3 disks of 95 mm 3 5 inches diameter and its height is 25 4 mm 1 inch 2 Large capacity The disk drive can record up to 3 249 MB formatted on one disk using the 16 17 EPRML recording method and 15 recording zone technology The MPC3032AT MPC3043AT MPC3064AT MPC3084AT MPC3096AT and MPC3102AT ...

Page 17: ...isk drive can be connected to an ATA interface of a personal computer 2 256 KB data buffer The disk drive uses a 256 KB data buffer to transfer data between the host and the disk media In combination with the read ahead cache system described in item 3 and the write cache described in item 6 the buffer contributes to efficient I O processing 3 Read ahead cache system After the execution of a disk ...

Page 18: ...ery The 24 byte ECC has improved buffer error correction for correctable data errors 6 Write cache When the disk drive receives a write command the disk drive posts the command completion at completion of transferring data to the data buffer completion of writing to the disk media This feature reduces the access time at writing ...

Page 19: ...cal Start Stop time Start 0 rpm to Drive Read Stop at Power Down Typical 8 sec Maximum 16 sec Typical 20 sec Maximum 30 sec Interface ATA 3 Maximum Cable length 0 46 m Data Transfer Rate To From Media 11 44 to 19 83 MB s 12 58 to 19 83 MB s To From Host 16 7 MB s Max burst PIO mode 4 burst DMA mode 2 33 3 MB s Max burst ultra DMA mode 2 Data buffer 256 KB Physical Dimensions Height Width Depth 26 ...

Page 20: ...043AT 4325 52 No 6 32UNC CA01675 B331 MPC3064AT 6488 29 No 6 32UNC CA01675 B341 MPC3084AT 8455 20 No 6 32UNC CA01675 B561 MPC3096AT 9747 58 No 6 32UNC CA01675 B361 MPC3102AT 10242 74 No 6 32UNC CA01675 B661 1 3 Power Requirements 1 Input Voltage 5 V 5 12 V 8 2 Ripple 12 V 5 V Maximum 200 mV peak to peak 100 mV peak to peak Frequency DC to 1 MHz DC to 1 MHz 3 Current Requirements and Power Dissipat...

Page 21: ...15 7 16 7 34 8 00 Standby 4 230 1 20 Sleep 4 110 0 60 1 Current is typical rms except for spin up 2 Power requirements reflect nominal values for 12V and 5V power 3 Idle mode is in effect when the drive is not reading writing seeking or executing any commands A portion of the R W circuitry is powered down the spindle motor is up to speed and the Drive ready condition exists 4 R W mode is defined a...

Page 22: ... seconds Figure 1 1 Current fluctuation Typ when power is turned on 5 Power on off sequence The voltage detector circuit monitors 5 V and 12 V The circuit does not allow a write signal if either voltage is abnormal This prevents data from being destroyed and eliminates the need to be concerned with the power on off sequence ...

Page 23: ...densing 29 C Altitude relative to sea level Operating Non operating 60 to 3 000 m 200 to 10 000 ft 60 to 12 000 m 200 to 40 000 ft 1 5 Acoustic Noise Table 1 5 lists the acoustic noise specification Table 1 5 Acoustic noise specification Model MPC3032AT MPC3043AT MPC3064AT MPC3084AT MPC3096AT MPC3102AT Idle mode DRIVE READY 3 5 bels 3 6 bels 3 7 bels Seek mode Random 4 1 bels 4 2 bels 4 2 bels Sou...

Page 24: ...ts refers to defects that involve repair readjustment or replacement Disk drive defects do not include failures caused by external factors such as damage caused by handling inappropriate operating environments defects in the power supply host system or interface cable 2 Mean time to repair MTTR The mean time to repair MTTR is 30 minutes or less if repaired by a specialist maintenance staff member ...

Page 25: ...annot be recovered by maximum 126 times read retries without user s retry and ECC corrections shall occur no more than 10 times when reading data of 1015 bits Read retries are executed according to the disk drive s error recovery procedure and include read retries accompanying head offset operations 2 Positioning error Positioning seek errors that can be recovered by one retry shall occur no more ...

Page 26: ...iguration 2 1 Device Configuration Figure 2 1 shows the disk drive The disk drive consists of a disk enclosure DE read write preamplifier and controller PCA The disk enclosure contains the disk media heads spindle motors actuators and a circulating air filter Figure 2 1 Disk drive outerview ...

Page 27: ...2 disks MPC3084AT 3 disks MPC3096AT 3 disks MPC3102AT 3 disks 2 Head The heads are of the contact start stop CSS type The head touches the disk surface while the disk is not rotating and automatically lifts when the disk starts Figure 2 2 illustrates the configuration of the disks and heads of each model In the disk surface servo information necessary for controlling positioning and read write and...

Page 28: ... are rotated by a direct drive Hall less DC motor 4 Actuator The actuator uses a revolving voice coil motor VCM structure which consumes low power and generates very little heat The head assembly at the tip of the actuator arm is controlled and positioned by feedback of the servo information read by the read write head If the power is not on or if the spindle motor is stopped the head assembly sta...

Page 29: ...ity by preventing errors caused by external noise 7 Controller circuit The controller circuit consists of an LSI chip to improve reliability The high speed microprocessor unit MPU achieves a high performance AT controller 2 2 System Configuration 2 2 1 ATA interface Figures 2 3 and 2 4 show the ATA interface system configuration The drive has a 40 pin PC AT interface connector and supports the PIO...

Page 30: ... and receiver ATA is an abbreviation of AT attachment The disk drive is conformed to the ATA 3 interface At high speed data transfer PIO mode 3 mode 4 DMA mode 2 or ultra DMA mode 2 occurrence of ringing or crosstalk of the signal lines AT bus between the HA and the disk drive may be a great cause of the obstruction of system reliability Thus it is necessary that the capacitance of the signal line...

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Page 32: ...INSTALLATION CONDITIONS 3 1 Dimensions 3 2 Mounting 3 3 Cable Connections 3 4 Jumper Settings 3 1 Dimensions Figure 3 1 illustrates the dimensions of the disk drive and positions of the mounting screw holes All dimensions are in mm ...

Page 33: ...C141 E055 02EN 3 2 Figure 3 1 Dimensions ...

Page 34: ...losure DE body is connected to signal ground SG and the mounting frame is also connected to signal ground These are electrically shorted Note Use No 6 32UNC screw for the mounting screw and the screw length should satisfy the specification in Figure 3 4 3 Limitation of side mounting When the disk drive is mounted using the screw holes on both side of the disk drive use two screw holes shown in Fig...

Page 35: ...e 3 4 Mounting frame structure 5 0 or less 4 5 or less 2 B Frame of system cabinet Details of B Details of A Frame of system cabinet Screw Screw PCA DE 2 5 2 5 2 5 A DE Side surface mounting Bottom surface mounting Do not use this screw holes Use these screw holes ...

Page 36: ... in the cabinet such that the PCA side in particular receives sufficient cooling To check the cooling efficiency measure the surface temperatures of the DE Regardless of the ambient temperature this surface temperature must meet the standards listed in Table 3 1 Figure 3 5 shows the temperature measurement point Figure 3 5 Surface temperature measurement points Table 3 1 Surface temperature measur...

Page 37: ...on Figure 3 6 Service area 6 External magnetic fields Avoid mounting the disk drive near strong magnetic sources such as loud speakers Ensure that the disk drive is not affected by external magnetic fields P side Cable connection Mode setting switches R side Mounting screw hole Mounting screw hole Q side Mounting screw hole ...

Page 38: ...connectors and terminals listed below for connecting external devices Figure 3 7 shows the locations of these connectors and terminals Power supply connector CN1 ATA interface connector CN1 Figure 3 7 Connector locations ATA interface connector Mode Setting Pins Power supply connector CN1 ...

Page 39: ...424 0 AMP Contact 60617 4 AMP Signal cable AWG 18 to 24 Note The cable of twisted pairs and neighboring line separated individually is not allowed to use for the host interface cable It is because that the location of signal lines in these cables is not fixed and so the problem on the crosstalk among signal lines may occur 3 3 3 Device connection Figure 3 8 shows how to connect the devices ATA int...

Page 40: ... 12VDC 4 3 2 1 Figure 3 9 Power supply connector pins CN1 3 4 Jumper Settings 3 4 1 Location of setting jumpers Figure 3 10 shows the location of the jumpers to select drive configuration and functions A39 A40 Interface Connector Mode setting Connector pins Power supply connector C01 C04 B01 02 B06 B05 B05 06 A01 02 A39 40 CN1 A01 A02 B02 C04 C01 B01 Figure 3 10 Jumper location ...

Page 41: ...ult setting 3 4 3 Jumper configuration 1 Device type Master device device 0 or slave device device 1 is selected 06 B02 05 B01 a Master device b Slave device B01 05 06 B02 Figure 3 12 Jumper setting of master or slave device 2 Cable Select CSEL In Cable Select mode the device can be configured either master device or slave device For use of Cable Select function Unique interface cable is needed ...

Page 42: ...the cable and connecting it to ground further the CSEL is set to low level The device is identified as a master device At this time the CSEL of the slave device does not have a conductor Thus since the slave device is not connected to the CSEL conductor the CSEL is set to high level The device is identified as a slave device Open CSEL conductor GND Slave device Master device Host system Figure 3 1...

Page 43: ... No of heads No of sectors MPC3032AT 6 704 15 63 MPC3043AT 8 940 15 63 MPC3064AT 13 410 15 63 MPC3084AT 16 383 16 63 MPC3096AT 16 383 16 63 MPC3102AT 16 383 16 63 b Special mode 2 4 6 1 3 5 2 4 6 Slave Device Master Device 1 3 5 2 4 6 1 3 5 Cable Select Model No of cylinders No of heads No of sectors MPC3032AT 4 092 16 63 MPC3043AT 4 092 16 63 MPC3064AT 4 092 16 63 MPC3084AT 4 092 16 63 MPC3096AT ...

Page 44: ...od 4 2 Subassemblies The disk drive consists of a disk enclosure DE and printed circuit assembly PCA The DE contains all movable parts in the disk drive including the disk spindle actuator read write head and air filter For details see Subsections 4 2 1 to 4 2 5 The PCA contains the control circuits for the disk drive The disk drive has one PCA For details see Sections 4 3 4 2 1 Disk The DE contai...

Page 45: ...4 MPC3084AT MPC3096AT and MPC3102AT has 6 These heads are raised from the disk surface as the spindle motor approaches the rated rotation speed MPC3084AT MPC3096AT MPC3102AT Model MPC3032AT Model Spindle Actuator 0 1 MPC3043AT Model Spindle Actuator 0 1 2 MPC3064AT Model Spindle Actuator 0 1 3 2 Spindle Actuator 0 1 4 3 5 2 Figure 4 1 Head structure ...

Page 46: ...the disk The head carriage position is controlled by feeding back the difference of the target position that is detected and reproduced from the servo information read by the read write head 4 2 5 Air filter There are two types of air filters a breather filter and a circulation filter The breather filter makes an air in and out of the DE to prevent unnecessary pressure around the spindle when the ...

Page 47: ...ains the 16 17 group coded recording GCR encoder and decoder and servo demodulation circuit 2 Servo circuit The position and speed of the voice coil motor are controlled by 2 closed loop servo using the servo information recorded on the data surface The servo information is an analog signal converted to digital for processing by a MPU and then reconverted to an analog signal for control of the voi...

Page 48: ...C141 E055 01EN 4 5 Figure 4 2 MPC30xxAT Block diagram ...

Page 49: ... read write test after enabling response to the ATA bus c After confirming that the spindle motor has reached rated speed the disk drive releases the heads from the actuator magnet lock mechanism by applying current to the VCM This unlocks the heads which are parked at the inner circumference of the disks d The disk drive positions the heads onto the SA area and reads out the system information e ...

Page 50: ...uffer write read test The spindle motor starts Self diagnosis 1 MPU bus test Inner register write read test Work RAM write read test Start Power on Drive ready state command waiting state Execute self calibration Initial on track and read out of system information f e d End Figure 4 3 Power on operation sequence ...

Page 51: ...ation The measured values are stored in the SA cylinder In the self calibration the compensating value is updated using the value in the SA cylinder 2 Compensating open loop gain Torque constant value of the VCM has a dispersion for each drive and varies depending on the cylinder that the head is positioned To realize the high speed seek operation the value that compensates torque constant value c...

Page 52: ...About 30 minutes 3 About 30 minutes About 60 minutes 4 About 30 minutes About 90 minutes 5 About 30 minutes About 120 minutes 6 About 30 minutes About 150 minutes 7 9 Every about 30 minutes 4 5 3 Command processing during self calibration If the disk drive receives a command execution request from the host while executing self calibration according to the timechart the disk drive terminates self c...

Page 53: ...DATA The IC generates a write error sense signal WUS when a write error occurs due to head short circuit or head disconnection 4 6 2 Write circuit The write data is output from the hard disk controller HDC with the NRZ data format and sent to the encoder circuit in the RDC with synchronizing with the write clock The NRZ write data is converted to 16 17 code data by the encoder circuit then sent to...

Page 54: ...C141 E055 01EN 4 11 Figure 4 4 Read write circuit block diagram ...

Page 55: ... frequency boost up function that equalizes the waveform of the read signal Cut off frequency of the low pass filter and boost up gain are controlled from each DAC circuit in read channel by an instruction of the serial data signal from MPU M1 The MPU optimizes the cut off frequency and boost up gain according to the transfer frequency of each zone 3 Adaptive equalizer circuit This circuit is 3 ta...

Page 56: ...4 5 6 7 Cylinder 0 to 980 981 to 1960 1961 to 2960 2961 to 3895 3896 to 4640 4641 to 5370 5371 to 5910 5911 to 6455 Transfer rate MB s 19 83 19 83 19 83 19 06 18 43 17 79 16 80 16 80 Zone 8 9 10 11 12 13 14 Cylinder 6456 to 6895 6896 to 7695 7696 to 8465 8466 to 9105 9106 to 9720 9721 to 10690 10691 to 11115 Transfer rate MB s 16 40 15 63 14 87 14 23 13 60 12 58 11 44 MPC3102AT Zone 0 1 2 3 4 5 6 ...

Page 57: ...escribes the functions of the blocks 5 1 2 3 4 P Amp CSR Current Sense Resistor VCM Voice Coil Motor Spindle motor control DSP unit Servo burst capture SVC MPU CSR Driver DAC ADC Position Sense Head VCM current VCM Spindle motor 7 6 Figure 4 5 Block diagram of servo control circuit 1 Microprocessor unit MPU The MPU includes DSP unit etc and the MPU starts the spindle motor moves the heads to the r...

Page 58: ...outermost circumference cylinder 0 c Seek to specified cylinder Drives the VCM to position the head to the specified cylinder d Calibration Senses and stores the thermal offset between heads and the mechanical forces on the actuator and stores the calibration value Figure 4 6 Physical sector servo configuration on disk surface Servo frame 72 servo frames revolution ...

Page 59: ...or This circuit detects number of revolution of the motor by the interrupt generated periodically compares with the target revolution speed then flows the current into the motor coil according to the differentiation aberration 7 Driver circuit The driver circuit is a power amplitude circuit that receives signals from the spindle motor control circuit and feeds currents to the spindle motor 8 VCM c...

Page 60: ...g operation of radius direction and position detection of circumstance direction The servo frame consists of 5 blocks write read recovery servo mark gray code servo A to D and PAD Figure 4 7 shows the servo frame format PAD Servo D Servo C Servo B Servo A 0 54 µs 1 32 µs 1 32 µs 1 32 µs 1 26 µs 3 06 µs 0 54 µs 2 34 µs Gray code Servo mark Write read recovery Figure 4 7 Servo frame format 1 Write r...

Page 61: ...ation to move the head to the target cylinder to read or write data and the track following operation to position the head onto the target track 1 Operation to move the head to the reference cylinder The MPU moves the head to the reference cylinder when the power is turned The reference cylinder is in the data area When power is applied the heads are moved from the inner circumference shunt zone t...

Page 62: ...otor driver called SVC hereafter The firmware operates on the MPU manufactured by Fujitsu The spindle motor is controlled by sending several signals from the MPU to the SVC There are three modes for the spindle control start mode acceleration mode and stable rotation mode 1 Start mode When power is supplied the spindle motor is started in the following sequence a After the power is turned on the M...

Page 63: ... motor based on the PHASE signal from the SVC The MPU takes a difference between the current time and a time for one revolution at 5 400 rpm that the MPU already recognized Then the MPU keeps the rotational speed to 5 400 rpm by charging or discharging the charge pump for the different time For example when the actual rotational speed is 5 600 rpm the time for one revolution is 10 714 ms And the t...

Page 64: ...C141 E055 01EN 5 1 CHAPTER 5 INTERFACE 5 1 Physical Interface 5 2 Logical Interface 5 3 Host Commands 5 4 Command Protocol 5 5 Ultra DMA feature Set 5 6 Timing ...

Page 65: ...UEST IOCS16 IOCS 16 PDIAG PASSED DIAGNOSTIC IORDY I O CHANNEL READY DASP DEVICE ACTIVE DEVICE 1 PRESENT DIOW I O WRITE DIOR I O READ DMARQ DMA REQUEST DMACK DMA ACKNOWLEDGE IDD Host DD 15 0 DATA BUS DA 0 2 DEVICE ADDRESS CS0 CHIP SELECT 0 CS1 CHIP SELECT 1 RESET RESET CSEL CABLE SELECT GND GROUND Figure 5 1 Interface signals ...

Page 66: ...A12 DATA13 DATA14 DATA15 KEY GND GND GND CSEL GND IOCS16 PDIAG DA2 CS1 GND signal I O Description RESET I Reset signal from the host This signal is low active and is asserted for a minimum of 25 µs during power on DATA 0 15 I O Sixteen bit bi directional data bus between the host and the device These signals are used for data transfer DIOW STOP I DIOW is the strobe signal asserted by the host to w...

Page 67: ...ted or interrupt is disabled IOCS16 O This signal indicates 16 bit data bus is addressed in PIO data transfer This signal is an open collector output When IOCS16 is not asserted 8 bit data is transferred through DATA0 to DATA7 signals When IOCS16 is asserted 16 bit data is transferred through DATA0 to DATA15 signals CS0 I Chip select signal decoded from the host address bus This signal is used by ...

Page 68: ...ce When CSEL signal is open the IDD is a slave device This signal is pulled up with 240 kΩ resistor DMACK I The host system asserts this signal as a response that the host system receive data or to indicate that data is valid DMARQ O This signal is used for DMA transfer between the host system and the device The device asserts this signal when the device completes the preparation of DMA data trans...

Page 69: ...tor Number registers are LBA bits The sector No under the LBA mode proceeds in the ascending order with the start point of LBA0 defined as follows LBA0 Cylinder 0 Head 0 Sector 1 Even if the host system changes the assignment of the CHS mode by the INITIALIZE DEVICE PARAMETER command the sector LBA address is not changed LBA Cylinder No Number of head Head No Number of sector track Sector No 1 5 2...

Page 70: ...nd X 1F7 1 1 X X X Invalid Invalid Control block registers 0 1 1 1 0 Alternate Status Device Control X 3F6 0 1 1 1 1 X 3F7 Notes 1 The Data register for read or write operation can be accessed by 16 bit data bus DATA0 to DATA15 2 The registers for read or write operation other than the Data registers can be accessed by 8 bit data bus DATA0 to DATA7 3 When reading the Drive Address register bit 7 i...

Page 71: ...X ABRT TK0NF AMNF X Unused Bit 7 Interface CRC error ICRC This bit indicates that an interface CRC error has occurred during an Ultra DMA data transfer The content of this bit is not applicable for Multiword DMA transfers Bit 6 Uncorrectable Data Error UNC This bit indicates that an uncorrectable data error has been encountered Bit 5 Unused Bit 4 ID Not Found IDNF This bit indicates an error excep...

Page 72: ...e host system and the device When the value in this register is X 00 the sector count is 256 When this register indicates X 00 at the completion of the command execution this indicates that the command is completed successfully If the command is not completed successfully this register indicates the number of sectors to be transferred to complete the request from the host system That is this regis...

Page 73: ...h order 8 bits of the cylinder address are set to the Cylinder High register Under the LBA mode this register indicates LBA bits 23 to 16 8 Device Head register X 1F6 The contents of this register indicate the device and the head number When executing INITIALIZE DEVICE PARAMETERS command the contents of this register defines the number of heads minus 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit...

Page 74: ... ns after RESET is negated or SRST is set in the Device Control register the BSY bit is set the BSY bit is cleared when the reset process is completed The BSY bit is set for no longer than 15 seconds after the IDD accepts reset b Within 400 ns from the host system starts writing to the Command register c Within 5 µs following transfer of 512 bytes data during execution of the READ SECTOR S WRITE S...

Page 75: ...us command was being executed The Error register indicates the additional information of the cause for the error 10 Command register X 1F7 The Command register contains a command code being sent to the device After this register is written the command execution starts immediately Table 5 3 lists the executable commands and their command codes This table also lists the necessary parameters for each...

Page 76: ...sets both device simultaneously The slave device is not required to execute the DASP handshake Bit 1 nIEN bit enables an interrupt INTRQ signal from the device to the host When this bit is 0 and the device is selected an interruption INTRQ signal can be enabled through a tri state buffer When this bit is 1 or the device is not selected the INTRQ signal is in the high impedance state 5 3 Host Comma...

Page 77: ...Y WRITE SECTOR S 0 0 1 1 0 0 0 R N Y Y Y Y RECALIBRATE 0 0 0 1 X X X X N N N N D SEEK 0 1 1 1 X X X X N N Y Y Y INITIALIZE DEVICE DIAGNOSTIC 1 0 0 1 0 0 0 1 N Y N N Y IDENTIFY DEVICE 1 1 1 0 1 1 0 0 N N N N D IDENTIFY DEVICE DMA 1 1 1 0 1 1 1 0 N N N N D SET FEATURES 1 1 1 0 1 1 1 1 Y N N N D SET MULTIPLE MODE 1 1 0 0 0 1 1 0 N Y N N D EXECUTE DEVICE DIAGNOSTIC 1 0 0 1 0 0 0 0 N N N N D FORMAT TRA...

Page 78: ...1 1 1 N N N N D Notes FR Features Register CY Cylinder Registers SC Sector Count Register DH Drive Head Register SN Sector Number Register R Retry at error 1 Without retry 0 with retry Y Necessary to set parameters Y Necessary to set parameters under the LBA mode N Necessary to set parameters The parameter is ignored if it is set N May set parameters D The device parameter is valid and the head pa...

Page 79: ...B LBA 1F3H SN Start sector No LBA LSB 1F2H SC Transfer sector count 1F1H FR xx At command completion I O registers contents to be read Bit 7 6 5 4 3 2 1 0 1F7H ST Error information 1F6H DH L DV Head No LBA MSB 1F5H CH Start cylinder address MSB LBA 1F4H CL Start cylinder address LSB LBA 1F3H SN Start sector No LBA LSB 1F2H SC X 00 1F1H ER Error information CM Command register FR Features register ...

Page 80: ...he track specified by the host the device performs a implied seek After the head reaches to the specified track the device reads the target sector The DRQ bit of the Status register is always set prior to the data transfer regardless of an error condition Upon the completion of the command execution command block registers contain the cylinder head and sector addresses in the CHS mode or logical b...

Page 81: ...ULTIPLE MODE command should be executed prior to the READ MULTIPLE command When the READ MULTIPLE command is issued the Sector Count register contains the number of sectors requested not a number of the block count or a number of sectors in a block Upon receipt of this command the device executes this command even if the value of the Sector Count register is less than the defined block count the v...

Page 82: ... 1 2 3 4 Partial block Block Block Sector transferred DRQ Figure 5 2 Execution example of READ MULTIPLE command At command issuance I O registers setting contents 1F7H CM 1 1 0 0 0 1 0 0 1F6H DH L DV Start head No LBA MSB 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H FR Start cylinder No MSB LBA Start cylinder No LSB LBA Start sector No LBA LSB Transfer sector count xx At command completion I O registers c...

Page 83: ...he error information is the same as the READ SECTOR S command In LBA mode The logical block address is specified using the start head No start cylinder No and first sector No fields At command completion the logical block address of the last sector and remaining number of sectors of which data was not transferred like in the CHS mode are set The host system can select the DMA transfer mode by usin...

Page 84: ...d execution the command block registers contain the cylinder head and sector number of the last sector verified If an error occurs the verify operation is terminated at the sector where the error occurred The command block registers contain the cylinder the head and the sector addresses in the CHS mode or the logical block address in the LBA mode of the sector where the error occurred The Sector C...

Page 85: ...the device performs a implied seek After the head reaches to the specified track the device writes the target sector The data stored in the buffer and CRC code and ECC bytes are written to the data field of the corresponding sector s Upon the completion of the command execution the command block registers contain the cylinder head and sector addresses of the last sector written If an error occurs ...

Page 86: ... MODE command should be executed prior to the WRITE MULTIPLE command When the WRITE MULTIPLE command is issued the Sector Count register contains the number of sectors requested not a number of the block count or a number of sectors in a block Upon receipt of this command the device executes this command even if the value of the Sector Count register is less than the defined block count the value ...

Page 87: ... Error information Note When the command terminates due to error only the DV bit and the error information field are valid 7 WRITE DMA X CA or X CB This command operates similarly to the WRITE SECTOR S command except for following events The data transfer starts at the timing of DMARQ signal assertion The device controls the assertion or negation timing of the DMARQ signal The device posts a statu...

Page 88: ...No LBA LSB Transfer sector count xx R 0 with Retry R 1 without Retry At command completion I O registers contents to be read 1F7H ST Status information 1F6H DH L DV End head No LBA MSB 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H ER End cylinder No MSB LBA End cylinder No LSB LBA End sector No LBA LSB 00 1 Error information 1 If the command is terminated due to an error the remaining number of sectors of ...

Page 89: ...B LBA End sector No LBA LSB 00 1 Error information 1 If the command is terminated due to an error the remaining number of sectors of which data was not transferred is set in this register 9 RECALIBRATE X 1x x X 0 to X F This command performs the seek operation to the Cylinder 0 Upon receipt of this command the device sets BSY bit of the Status register and performs the seek operation When the devi...

Page 90: ...s the DSC bit Drive Seek Complete status of the Status register to 1 In the LBA mode this command performs the seek operation to the cylinder and head position in which the sector is specified with the logical block address At command issuance I O registers setting contents 1F7H CM 0 1 1 1 x x x x 1F6H DH L DV Head No LBA MSB 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H FR Cylinder No MSB LBA Cylinder No ...

Page 91: ...thin a default area It is recommended that the host system refers the addressable user sectors total number of sectors in word 60 to 61 of the parameter information by the IDENTIFY DEVICE command At command issuance I O registers setting contents 1F7H CM 1 0 0 1 0 0 0 1 1F6H DH DV Max head No 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H FR xx xx xx Number of sectors track xx At command completion I O regi...

Page 92: ...ntents 1F7H CM 1 1 1 0 1 1 0 0 1F6H DH DV xx 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H FR xx xx xx xx xx At command completion I O registers contents to be read 1F7H ST Status information 1F6H DH DV xx 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H ER xx xx xx xx Error information ...

Page 93: ...or X 0007 Enable disable setting of words 54 58 64 70 and 88 7 54 Variable Number of current Cylinders 55 Variable Number of current Head 56 Variable Number of current sectors per track 57 58 Variable Total number of current sectors 59 8 Transfer sector count currently set by READ WRITE MULTIPLE command 60 61 X 0060AB30 X 0080E92C X 00C15DC2 X 00FBFC10 X 01228030 X 01314170 Total number of user ad...

Page 94: ... number ASCII code 40 characters Left justified remainder filled with blank code X 20 One of following model numbers MPC3032AT MPC3043AT MPC3064AT MPC3084AT MPC3096AT MPC3102AT 5 Word 49 Capabilities Bit 15 14 Reserved Bit 13 Standby timer value 0 vendor specific Bit 12 Reserved Bit 11 IORDY support 1 Supported Bit 10 IORDY inhibition 0 Disable inhibition Bit 9 LBA support 1 Supported Bit 8 DMA su...

Page 95: ...e 1 Bit 0 1 Mode 0 10 Word 64 Advance PIO transfer mode support status Bit 15 8 Reserved Bit 7 0 Advance PIO transfer mode Bit 1 1 Mode 4 Bit 0 1 Mode 3 11 Word 80 Major version number Bit 15 4 Reserved Bit 3 ATA 3 Supported 1 Bit 2 ATA 2 Supported 1 Bit 1 ATA 1 Supported 1 Bit 0 Undefined 12 Word 82 Support of command sets Bit 15 4 Reserved Bit 3 Power Management feature set supported 1 Bit 2 Rem...

Page 96: ...formation 14 SET FEATURES X EF The host system issues the SET FEATURES command to set parameters in the Features register for the purpose of changing the device features to be executed For the transfer mode Feature register 03 detail setting can be done using the Sector Count register Upon receipt of this command the device sets the BSY bit of the Status register and saves the parameters in the Fe...

Page 97: ...d WRITE LONG commands X CC Enables the reverting to power on default settings after software reset At power on or after hardware reset the default mode is the same as that is set with a value greater than X AA except for write cache If X 66 is specified it allows the setting value greater than X AA which may have been modified to a new value since power on to remain the same even after software re...

Page 98: ...0 000 X 40 Mode 0 01000 001 X 41 Mode 1 01000 010 X 42 Mode 2 15 SET MULTIPLE MODE X C6 This command enables the device to perform the READ MULTIPLE and WRITE MULTIPLE commands The block count number of sectors in a block for these commands are also specified by the SET MULTIPLE MODE command The number of sectors per block is written into the Sector Count register The IDD supports 2 4 8 16 and 32 ...

Page 99: ...or to software reset is retained after software reset The parameters for the multiple commands which are posted to the host system when the IDENTIFY DEVICE command is issued are listed below See Subsection 5 3 2 for the IDENTIFY DEVICE command Word 47 0020 Word 59 0000 01xx Maximum number of sectors that can be transferred per interrupt by the READ MULTIPLE and WRITE MULTIPLE commands are 32 fixed...

Page 100: ...gister and generates an interrupt The device 1 does not generate an interrupt A diagnostic status of the device 1 is read by the host system When a diagnostic failure of the device 1 is detected the host system can read a status of the device 1 by setting the DV bit selecting the device 1 When device 1 is not present The device 0 posts only the results of its own self diagnosis The device 0 clears...

Page 101: ...e BSY bit However the device does not perform format operation but the drive clears the BYS bit and generates an interrupt soon When the command execution completes the device clears the BSY bit and generates an interrupt The drive supports this command for keep the compatibility with previous drive only 18 READ LONG X 22 or X 23 This command operates similarly to the READ SECTOR S command except ...

Page 102: ... an error this register indicates 01 19 WRITE LONG X 32 or X 33 This command operates similarly to the READ SECTOR S command except that the device writes the data and the ECC bytes transferred from the host system to the disk medium The device does not generate ECC bytes by itself The WRITE LONG command supports only single sector operation The number of ECC bytes to be transferred is fixed to 4 ...

Page 103: ...A Sector No LBA LSB 00 1 Error information 1 If the command is terminated due to an error this register indicates 01 20 READ BUFFER X E4 The host system can read the current contents of the sector buffer of the device by issuing this command Upon receipt of this command the device sets the BSY bit of Status register and sets up the sector buffer for a read operation Then the device sets the DRQ bi...

Page 104: ...it of the Status register Then the device sets the DRQ bit of Status register and clears the BSY bit when the device is ready to receive the data After that 512 bytes of data is transferred from the host and the device writes the data to the sector buffer then generates an interrupt At command issuance I O registers setting contents 1F7H CM 1 1 1 1 1 0 0 0 1F6H DH DV xx 1F5H CH 1F4H CL 1F3H SN 1F2...

Page 105: ...ns that the device automatically enters the standby mode after a certain period of time When the device enters the idle mode the timer starts countdown If any command is not issued while the timer is counting down the device automatically enters the standby mode If any command is issued while the timer is counting down the timer is initialized and the command is executed The timer restarts countdo...

Page 106: ... the Status register and enters the idle mode Then the device clears the BSY bit and generates an interrupt This command does not support the automatic power down function At command issuance I O registers setting contents 1F7H CM X 95 or X E1 1F6H DH DV xx 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H FR xx xx xx xx xx At command completion I O registers contents to be read 1F7H ST Status information 1F6H...

Page 107: ... the Sector Count register is 0 the automatic power down function is disabled Under the standby mode the spindle motor is stopped Thus when the command involving a seek such as the READ SECTOR s command is received the device processes the command after driving the spindle motor At command issuance I O registers setting contents 1F7H CM X 96 or X E2 1F6H DH DV xx 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F...

Page 108: ...ceipt of this command the device sets the BSY bit of the Status register and enters the sleep mode The device then clears the BSY bit and generates an interrupt The device generates an interrupt even if the device has not fully entered the sleep mode In the sleep mode the spindle motor is stopped and the ATA interface section is inactive All I O register outputs are in high impedance state The onl...

Page 109: ...th this command The host system can confirm the power save mode of the device by analyzing the contents of the Sector Count and Sector registers The device sets the BSY bit and sets the following register value After that the device clears the BSY bit and generates an interrupt Power save mode Sector Count register Sector Number register During moving to standby mode Standby mode During returning ...

Page 110: ...FR register is supported the Aborted Command error is posted It is necessary for the host to set the keys CL 4Fh and CH C2h in the CL and CH registers prior to issuing this command If the keys are set incorrectly the Aborted Command error is posted In the default setting the failure prediction feature is disabled In this case the Aborted Command error is posted in response to subcommands other tha...

Page 111: ...ta then clears the BSY bit X D4 SMART Execute Off line Immediate The subcommand causes the device to immediately initiate the optical set of activities that collect SMART data in an off line mode and then save this data to the device s non volatile memory X D8 SMART Enable Operations This subcommand enables the failure prediction feature The setting is maintained even when the device is turned off...

Page 112: ...is below the insurance failure threshold value the device is about to fail or the device is nearing the end of it life In this case the host recommends that the user quickly backs up the data At command issuance I O registers setting contents 1F7H CM 1 0 1 1 0 0 0 0 1F6H DH DV xx 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H FR Key C2h Key 4Fh xx xx Subcommand At command completion I O registers setting co...

Page 113: ...e SMART Read Attribute Thresholds subcommand FR register D1h Table 5 8 Format of device attribute value data Byte Item 00 01 Data format version number 02 Attribute 1 Attribute ID 03 04 Status flag 05 Current attribute value 06 Attribute value for worst case so far 07 to 0C Raw attribute value 0D Reserved 0E to 169 Attribute 2 to attribute 30 The format of each attribute value is the same as that ...

Page 114: ...ormat of each threshold value is the same as that of bytes 02 to 0D 16A to 17B Reserved 17C to 1FE Unique to vendor 1FF Check sum Data format version number The data format version number indicates the version number of the data format of the device attribute values or insurance failure thresholds The data format version numbers of the device attribute values and insurance failure thresholds are t...

Page 115: ...ttribute is within the insurance range of the device when the attribute exceeds the threshold If this bit is 0 the attribute is outside the insurance range of the device when the attribute exceeds the threshold Bits 1 to 15 Reserved bits Current attribute value The current attribute value is the normalized raw attribute data The value varies between 01h and 64h The closer the value gets to 01h the...

Page 116: ...e Bit 1 The device automatically saves the attribute value data to a medium after the previously set operation Bits 2 to 15 Reserved bits Check sum Two s complement of the lower byte obtained by adding 511 byte data one byte at a time from the beginning Insurance failure threshold The limit of a varying attribute value The host compares the attribute values with the thresholds to identify a failur...

Page 117: ... command may take longer than 30 s to complete If the command is not supported the device shall set the ABRT bit to one An unrecoverable error encountered during execution of writing data results in the termination of the command and the Command Block registers contain the sector address of the sector where the first unrecoverable error occurred The sector is removed from the cache Subsequent FLUS...

Page 118: ...TE VERIFY V V V V V V READ VERIFY SECTOR S V V V V V V RECALIBRATE V V V V V SEEK V V V V V INITIALIZE DEVICE PARAMETERS V V V V IDENTIFY DEVICE V V V V IDENTIFY DEVICE DMA V V V V SET FEATURES V V V V SET MULTIPLE MODE V V V V EXECUTE DEVICE DIAGNOSTIC V FORMAT TRACK V V V V V READ LONG V V V V V WRITE LONG V V V V V READ BUFFER V V V V WRITE BUFFER V V V V IDLE V V V V IDLE IMMEDIATE V V V V STA...

Page 119: ...rameters to the Features Sector Count Sector Number Cylinder and Device Head registers b The host writes a command code to the Command register c The device sets the BSY bit of the Status register and prepares for data transfer d When one sector or block of data is available for transfer to the host the device sets DRQ bit and clears BSY bit The drive then asserts INTRQ signal e After detecting th...

Page 120: ...lection INTRQ DRQ Min 30 µs 1 Expanded Command f d d e e c b a Command BSY INTRQ DRDY Parameter write DRQ Data transfer Figure 5 3 Read Sector s command protocol Even if the error status exists the drive makes a preparation setting the DRQ bit of data transfer It is up to the host whether data is transferred In other words the host should receive the data of the sector 512 bytes of uninsured dummy...

Page 121: ...ion is not guaranteed Transfers dummy data The host should receive 512 byte dummy data or release the DRQ set state by resetting Status read Command BSY INTRQ DRDY Parameter write DRQ Data transfer Figure 5 4 Protocol for command abort 5 4 2 Data transferring commands from host to device The execution of the following commands involves Data transfer from the host to the drive FORMAT TRACK WRITE SE...

Page 122: ...r is requested the drive sets the DRQ bit g After detecting the INTRQ signal assertion the host reads the Status register h The device resets INTRQ the interrupt signal I If transfer of another sector is requested steps d and after are repeated Figure 5 5 shows an example of WRITE SECTOR S command protocol and Figure 5 4 shows an example protocol for command abort Status read Status read 255 2 1 0...

Page 123: ...e command even if the drive requests the data transfer DRQ bit is set or when the host executes resetting the device correct operation is not guaranteed 5 4 3 Commands without data transfer Execution of the following commands does not involve data transfer between the host and the device RECALIBRATE SEEK READY VERIFY SECTOR S EXECUTE DEVICE DIAGNOSTIC INITIALIZE DEVICE PARAMETERS SET FEATURES SET ...

Page 124: ...g for the DMA transfer differs the following point a The host writes any parameters to the Features Sector Count Sector Number Cylinder and Device Head register b The host initializes the DMA channel c The host writes a command code in the Command register d The device sets the BSY bit of the Status register e The device asserts the DMARQ signal after completing the preparation of data transfer Th...

Page 125: ...255 2 1 0 Word IOR or IOW DMACK DMARQ DRQ Expanded Single Word DMA transfer Command BSY INTRQ DRDY Parameter write DRQ Data transfer DRQ Multiword DMA transfer DMACK DMARQ IOR or IOW 0 1 Word n 1 n Figure 5 7 Normal DMA data transfer ...

Page 126: ...s of STROBE are used for data transfers so that the frequency of STROBE is limited to the same frequency as the data The highest fundamental frequency on the cable shall be 16 67 million transitions per second or 8 33 MHz the same as the maximum frequency for PIO Mode 4 and DMA Mode 2 Words in the IDENTIFY DEVICE data indicate support of the Ultra DMA feature and the Ultra DMA Modes the device is ...

Page 127: ...nts 1 The host shall keep DMACK in the negated state before an Ultra DMA burst is initiated 2 The device shall assert DMARQ to initiate an Ultra DMA burst After assertion of DMARQ the device shall not negate DMARQ until after the first negation of DSTROBE 3 Steps 3 4 and 5 may occur in any order or at the same time The host shall assert STOP 4 The host shall negate HDMARDY 5 The host shall negate ...

Page 128: ... least tDVH after generating a DSTROBE edge to latch the data 4 The device shall repeat steps 1 2 and 3 until the data transfer is complete or an Ultra DMA burst is paused whichever occurs first 5 5 3 3 Pausing an Ultra DMA data in burst The following steps shall occur in the order they are listed unless otherwise specifically allowed see 5 6 4 4 and 5 6 4 2 for specific timing requirements a Devi...

Page 129: ...ated 3 The device shall release DD 15 0 no later than tAZ after negating DMARQ 4 The host shall assert STOP within tLI after the device has negated DMARQ The host shall not negate STOP again until after the Ultra DMA burst is terminated 5 The host shall negate HDMARDY within tLI after the device has negated DMARQ The host shall continue to negate HDMARDY until the Ultra DMA burst is terminated Ste...

Page 130: ... device shall stop generating DSTROBE edges within tRFS of the host negating HDMARDY 4 If the host negates HDMARDY within tSR after the device has generated a DSTROBE edge then the host shall be prepared to receive zero or one additional data words If the host negates HDMARDY greater than tSR after the device has generated a DSTROBE edge then the host shall be prepared to receive zero one or two a...

Page 131: ...assert DIOR CS0 CS1 DA2 DA1 or DA0 until at least tACK after negating DMACK 5 5 4 Ultra DMA data out commands 5 5 4 1 Initiating an Ultra DMA data out burst The following steps shall occur in the order they are listed unless otherwise specifically allowed see 5 6 4 7 and 5 6 4 2 for specific timing requirements 1 The host shall keep DMACK in the negated state before an Ultra DMA burst is initiated...

Page 132: ...an tCYC for the selected Ultra DMA Mode The host shall not generate two rising or falling HSTROBE edges more frequently than 2 tCYC for the selected Ultra DMA mode 3 The host shall not change the state of DD 15 0 until at least tDVH after generating an HSTROBE edge to latch the data 4 The host shall repeat steps 1 2 and 3 until the data transfer is complete or an Ultra DMA burst is paused whicheve...

Page 133: ...c timing requirements 1 The host shall initiate termination of an Ultra DMA burst by not generating HSTROBE edges 2 The host shall assert STOP no sooner than tSS after it last generated an HSTROBE edge The host shall not negate STOP again until after the Ultra DMA burst is terminated 3 The device shall negate DMARQ within tLI after the host asserts STOP The device shall not assert DMARQ again unti...

Page 134: ...s generated an HSTROBE edge then the device shall be prepared to receive zero or one additional data words If the device negates DDMARDY greater than tSR after the host has generated an HSTROBE edge then the device shall be prepared to receive zero one or two additional data words The additional data words are a result of cable round trip delay and tRFS timing for the host 5 The device shall negat...

Page 135: ...lculated for the return of STROBE to the asserted state after the Ultra DMA burst termination request has been acknowledged e At the end of any Ultra DMA burst the host shall send the results of its CRC calculation function to the device on DD 15 0 with the negation of DMACK f The device shall then compare the CRC data from the host with the calculated value in its own CRC calculation function If ...

Page 136: ...e following table describes recommended values for series termination at the host and the device Table 5 11 Recommended series termination for Ultra DMA Signal Host Termination Device Termination DIOR HDMARDY HSTROBE 33 ohm Inductor DIOW STOP 33 ohm Inductor CS0 CS1 33 ohm Inductor DA0 DA1 DA2 33 ohm 82 ohm DMACK 33 ohm 82 ohm DD15 through DD0 33 ohm Inductor DMARQ 82 ohm 33 ohm INTRQ 82 ohm 33 oh...

Page 137: ...C141 E055 01EN 5 74 5 6 Timing 5 6 1 PIO data transfer Figure 5 9 shows of the data transfer timing between the device and the host system ...

Page 138: ...Data setup time for DIOW 20 ns t4 Data hold time for DIOW 10 ns t5 Time from DIOR assertion to read data available 20 ns t6 Data hold time for DIOR 5 ns t7 Time from Data register selection to IOCS16 assertion 40 ns t8 Time from Data register selection reset to IOCS16 negation 30 ns t9 Data register selection hold time for DIOR DIOW 10 ns t10 Time from DIOR DIOW assertion to IORDY low level 35 ns ...

Page 139: ...IOW DMACK DMARQ Symbol Timing parameter Min Max Unit t0 Cycle time 240 ns tC Delay time from DMACK assertion to DMARQ negation 80 ns tD Pulse width of DIOR DIOW 120 ns tE Data setup time for DIOR 60 ns tF Data hold time for DIOR 5 ns tG Data setup time for DIOW 35 ns tH Data hold time for DIOW 20 ns tI DMACK setup time for DIOR DIOW 0 ns tJ DMACK hold time for DIOR DIOW 0 ns Figure 5 10 Single wor...

Page 140: ...parameter Min Max Unit t0 Cycle time 120 ns tC Delay time from DMACK assertion to DMARQ negation 35 ns tD Pulse width of DIOR DIOW 70 ns tE Data setup time for DIOR 30 ns tF Data hold time for DIOR 5 ns tG Data setup time for DIOW 20 ns tH Data hold time for DIOW 10 ns tI DMACK setup time for DIOR DIOW 0 ns tJ DMACK hold time for DIOR DIOW 5 ns tK Continuous time of high level for DIOR DIOW 25 ns ...

Page 141: ...ntains the values for the timings for each of the Ultra DMA Modes 5 6 4 1 Initiating an Ultra DMA data in burst 5 6 4 2 contains the values for the timings for each of the Ultra DMA Modes Note The definitions for the STOP HDMARDY and DSTROBE signal lines are not in effect until DMARQ and DMACK are asserted Figure 5 12 Initiating an Ultra DMA data in burst ...

Page 142: ...E from STOP during a data in burst tLI 0 150 0 150 0 150 Limited interlock time see Note 1 tMLI 20 20 20 Interlock time with minimum see Note 1 tUI 0 0 0 Unlimited interlock time see Note 1 tAZ 10 10 10 Maximum time allowed for output drivers to release from being asserted or negated tZAH 20 20 20 tZAD 0 0 0 tENV 20 70 20 70 20 70 Envelope time from DMACK to STOP and HDMARDY during data in burst i...

Page 143: ...nder to recipient or recipient to sender interlocks that is one agent either sender or recipient is waiting for the other agent to respond with a signal before proceeding tUI is an unlimited interlock that has no maximum time value tMLI is a limited time out that has a defined minimum tLI is a limited time out that has a defined maximum 2 All timing parameters are measured at the connector of the ...

Page 144: ... Ultra DMA Modes Note DD 15 0 and DSTROBE are shown at both the host and the device to emphasize that cable setting time as well as cable propagation delay shall not allow the data signals to be considered stable at the host until some time after they are driven by the device Figure 5 13 Sustained Ultra DMA data in burst ...

Page 145: ... for each of the Ultra DMA Modes Notes 1 The host may assert STOP to request termination of the Ultra DMA burst no sooner than tRP after HDMARDY is negated 2 If the tSR timing is not satisfied the host may receive zero one or two more data words from the device Figure 5 14 Host pausing an Ultra DMA data in burst ...

Page 146: ...in burst 5 6 4 2 contains the values for the timings for each of the Ultra DMA Modes Note The definitions for the STOP HDMARDY and DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated Figure 5 15 Device terminating an Ultra DMA data in burst ...

Page 147: ...in burst 5 6 4 2 contains the values for the timings for each of the Ultra DMA Modes Note The definitions for the STOP HDMARDY and DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated Figure 5 16 Host terminating an Ultra DMA data in burst ...

Page 148: ... out burst 5 6 4 2 contains the values for the timings for each of the Ultra DMA Modes Note The definitions for the STOP DDMARDY and HSTROBE signal lines are not in effect until DMARQ and DMACK are asserted Figure 5 17 Initiating an Ultra DMA data out burst ...

Page 149: ...ra DMA Modes Note DD 15 0 and HSTROBE signals are shown at both the device and the host to emphasize that cable setting time as well as cable propagation delay shall not allow the data signals to be considered stable at the device until some time after they are driven by the host Figure 5 18 Sustained Ultra DMA data out burst ...

Page 150: ...or each of the Ultra DMA Modes Notes 1 The device may negate DMARQ to request termination of the Ultra DMA burst no sooner than tRP after DDMARDY is negated 2 If the tSR timing is not satisfied the device may receive zero one or two more data words from the host Figure 5 19 Device pausing an Ultra DMA data out burst ...

Page 151: ...ut burst 5 6 4 2 contains the values for the timings for each of the Ultra DMA Modes Note The definitions for the STOP DDMARDY and HSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated Figure 5 20 Host terminating an Ultra DMA data out burst ...

Page 152: ...in burst 5 6 4 2 contains the values for the timings for each of the Ultra DMA Modes Note The definitions for the STOP DDMARDY and HSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated Figure 5 21 Device terminating an Ultra DMA data out burst ...

Page 153: ...et 2 Master and slave devices are present 2 drives configuration tP Clear Reset Slave device Master device tN DASP PDIAG BSY BSY DASP tQ tR tS Symbol Timing parameter Min Max Unit tM Pulse width of RESET 25 µs tN Time from RESET negation to BSY set 400 ns tP Time from RESET negation to DASP or DIAG negation 1 ms tQ Self diagnostics execution time 30 s tR Time from RESET negation to DASP assertion ...

Page 154: ...Address Translation 6 3 Power Save 6 4 Defect Management 6 5 Read Ahead Cache 6 6 Write Cache 6 1 Device Response to the Reset This section describes how the PDIAG and DASP signals responds when the power of the IDD is turned on or the IDD receives a reset or diagnostic command ...

Page 155: ...rm assertion of the DASP signal within 450 ms the master device recognizes that no slave device is connected After the slave device device 1 releases its own power on reset state the slave device shall report its presence and the result of power on diagnostics to the master device as described below DASP signal Asserted within 400 ms PDIAG signal Negated within 1 ms and asserted within 30 seconds ...

Page 156: ...agnostics If the master device cannot confirm assertion of the DASP signal within 450 ms the master device recognizes that no slave device is connected After the slave device receives the hardware reset the slave device shall report its presence and the result of the self diagnostics to the master device as described below DASP signal Asserted within 400 ms PDIAG signal Negated within 1 ms and ass...

Page 157: ...hall report its presence and the result of the self diagnostics to the master device as described below PDIAG signal negated within 1 ms and asserted within 30 seconds When the IDD is set to a slave device the IDD asserts the DASP signal when negating the PDIAG signal and negates the DASP signal when asserting the PDIAG signal Max 31 sec Max 30 sec Max 1 ms If the slave device is preset DASP is ch...

Page 158: ...he EXECUTE DEVICE DIAGNOSTIC command it shall report the result of the self diagnostics to the master device as described below PDIAG signal negated within 1 ms and asserted within 5 seconds When the IDD is set to a slave device the IDD asserts the DASP signal when negating the PDIAG signal and negates the DASP signal when asserting the PDIAG signal Max 6 sec Max 5 sec Max 1 ms If the slave device...

Page 159: ...1 are called BIOS specification Table 6 1 Default parameters MPC 3102AT MPC 3096AT MPC 3084AT MPC 3064AT MPC 3043AT MPC 3032AT Number of cylinders 16 383 16 383 16 383 13 410 8 940 6 704 Number of head 16 15 Number of sectors track 63 Formatted capacity MB 8 455 2 8 455 2 8 455 2 6 488 2 4 325 5 3 243 6 As long as the formatted capacity of the IDD does not exceed the value shown on Table 6 1 the h...

Page 160: ...ubsequent physical sector is the consecutive logical sector from the last sector of the current physical sector Figure 6 5 shows an example assuming there is no track skew 127 126 64 62 63 3 2 LS1 LS 63 LH5 LH2 LH1 LH0 LS1 1 Physical sector Physical head 0 ex Zone 0 Physical parameter Physical sector 1 to 336 Specification of INITIALIZE DEVICE PARAMETERS command Logical head LH 0 to 14 or 15 Logic...

Page 161: ...linder 0 LBA 334 LBA 2 LBA 1 LBA 0 336 335 3 2 1 LBA 335 Physical sector ex Zone 0 Physical parameter Physical sector 1 to 336 336 335 3 2 1 Physical head 1 Physical cylinder 0 LBA 338 LBA 337 LBA 336 LBA 670 LBA 671 Figure 6 6 Address translation example in LBA mode 6 3 Power Save The host can change the power consumption state of the device by issuing a power command to the device 6 3 1 Power sa...

Page 162: ...mmands through the interface However if a command with disk access is issued response time to the command under the standby mode takes longer than the active or Idle mode because the access to the disk medium cannot be made immediately The drive enters the standby mode under the following conditions A STANDBY or STANDBY IMMEDIATE command is issued in the active or idle mode When automatic power do...

Page 163: ...he following condition A SLEEP command is issued Issued commands are invalid ignored in this mode 6 3 2 Power commands The following commands are available as power commands IDLE IDLE IMMEDIATE STANDBY STANDBY IMMEDIATE SLEEP CHECK POWER MODE 6 4 Defect Management Defective sectors of which the medium defect location is registered in the system space are replaced with spare sectors in the formatti...

Page 164: ...r slip processing A defective sector is not used and is skipped and a logical sector address is assigned to the subsequent normal sector physically adjacent sector to the defective sector When defective sector is present the sector slip processing is performed in the formatting Figure 6 7 shows an example where physical sector 5 is defective on head 0 in cylinder 0 2 1 Index Head 0 Defective secto...

Page 165: ...alternate cylinders are provided for each head in zone 13 inner side When an access request to sector 5 is specified the device accesses the alternated sector in the alternate cylinder instead of sector 5 When an access request to sectors next to sector 5 is specified the device seeks to cylinder 0 head 0 and continues the processing Defective sector is assigned to unassigned sector unused Sector ...

Page 166: ... reads the subsequent data blocks automatically and stores the data to the data buffer When the next command requests to read the read ahead data the data can be transferred from the data buffer without accessing the disk medium The host can thus access data at higher speed 6 5 1 Data buffer configuration The drive has a 256 KB data buffer The buffer is used by divided into three parts for read co...

Page 167: ... operation 2 Data transferred to the host system once by requesting with the command that are object of caching operation except for the cache invalid data by some reasons 3 Remaining data in the data buffer for write command transferred from the host system by the command that writes data onto the disk medium such as the WRITE SECTOR S WRITE DMA WRITE MULTIPLE Followings are definition of in case...

Page 168: ...e state that the write data is kept in the data buffer for write command as a caching data new write command is issued write data kept until now are invalidated 6 5 3 Usage of read segment This subsection explains the usage of the read segment buffer at following cases 1 Miss hit no hit A lead block of the read requested data is not stored in the data buffer The requested data is read from the dis...

Page 169: ...isk media Read requested data Stores the read requested data upto this point Empty area DAP HAP 3 After reading the requested data and transferring the requested data to the host system had been completed the disk drive stops command execution without performing the read ahead operation Read requested data Empty area DAP stopped stopped HAP 4 Following shows the cache enabled data for next read co...

Page 170: ...ceived command is a sequential command and performs the read ahead operation after reading the requested data 1 At receiving the sequential read command the disk drive sets the DAP and HAP to the sequential address of the last read command and reads the requested data Empty data Mis hit data 2 The disk drive transfers the requested data that is already read to the host system with reading the requ...

Page 171: ...fers the hit data in the buffer to the host system The disk drive performs the read ahead operation of the new continuous data to the empty area that becomes vacant by data transfer at the same time as the disk drive starts transferring data to the host system 1 In the case that the contents of buffer is as follows at receiving a read command Start LBA Last LBA DAP HAP Completion of transferring r...

Page 172: ...quential read command read ahead operation and more than ten non sequential read commands are received after that continuously the read ahead operation is stopped refer to item 1 Processing is the same as item a above 3 Full hit hit all All requested data are stored in the data buffer The disk drive starts transferring the requested data from the address of which the requested data is stored After...

Page 173: ...does not perform the read ahead operation stopped HAP Cache data Full hit data Cache data 3 The cache data for next read command is as follows Cache data 4 Partially hit A part of requested data including a lead sector are stored in the data buffer The disk drive starts the data transfer from the address of the hit data corresponding to the lead sector of the requested data and reads remaining req...

Page 174: ...artially hit data Lack data 2 The disk drive starts transferring partially hit data and reads lack data from the disk media at the same time However the disk drive does not perform the read ahead operation newly stopped HAP stopped Requested data to be transferred DAP Partially hit data Lack data 3 The cache data for next read command is as follows Cache data Last LBA Start LBA ...

Page 175: ...vious command had been completed the latency time occurs to search the target sector If the received command is not a sequential write the drive receives data of sectors requested by the host system as same as sequential write The drive generates the interrupt of command complete after completion of data transfer requested by the host system Received data is processed after completion of the write...

Page 176: ...n is enabled the transferred data from the host by the WRITE SECTOR S is not completely written on the disk medium at the time that the interrupt of command complete is generated When the unrecoverable error occurs during the write operation the command execution is stopped Then when the drive receives the next command it generates an interrupt of abnormal end However an interrupt of abnormal end ...

Page 177: ...AÑA S A Almagro 40 28010 Madrid SPAIN TEL 34 91 681 8100 FAX 34 91 681 8125 FUJITSU AUSTRALIA LIMITED 2 Julius Avenue Cnr Delhi Road North Ryde N S W 2113 AUSTRALIA TEL 61 2 9776 4555 FAX 61 2 9776 4556 FUJITSU HONG KONG LTD Room 2521 Sun Hung Kai Centre 30 Harbour Road HONG HONG TEL 852 2827 5780 FAX 852 2827 4724 FUJITSU KOREA LTD Coryo Finance Center Bldg 23 6 YoulDo Dong Young DungPo Gu Seoul ...

Page 178: ...of this publication What is your occupation Your other comments may be entered here Please be specific and give page paragraph and line number references where applicable Your Name Return Address Sales Operating Installing Maintaining Learning Reference Fair Poor Very Good Good Very Poor Fully covered Well Illustrated Thank you for your interest Please send this sheet to one of the addresses in a ...

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