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Fujitsu MHV2160BT, Product Manual

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Interface 

 

*14 WORD 79 

Bits 15-7:  Reserved 

Bit 6:  

'1' = Enables the software settings preservation. 

Bit 5: 

Reserved 

Bit 4: 

'1' = Enables the in-order data delivery. 

Bit 3: 

'1' = Enables the Power Management initiation function from Bit 

2: 

 

'1' = Enables the Auto-Activate optimization function in the 

DMA Setup FIS. 

Bit 1: 

'1' = Enables the non-zero buffer offset function in the DMA 

Setup FIS. 

Bit 0: 

Reserved 

*15 WORD 80 

Bits 15-8:  Reserved 

Bit 7: 

'1' = ATA/ATAPI-7 supported 

Bit 6: 

'1' = ATA/ATAPI-6 supported 

Bit 5: 

'1' = ATA/ATAPI-5 supported 

Bit 4: 

'1' = ATA/ATAPI-4 supported  

Bit 3: 

'1' = ATA-3 supported  

Bit 2: 

'1' = ATA-2 supported  

Bits 1-0: 

Undefined 

*16 WORD 82 

Bit 15: 

Undefined 

Bit 14: 

'1' = Supports the NOP command. 

Bit 13: 

'1' = Supports the READ BUFFER command. 

Bit 7: 

'1' = Supports the release interrupt. 

Bit 12: 

'1' = Supports the WRITE BUFFER command. 

Bit 11: 

Undefined 

Bit 10: 

'1' = Supports the Host Protected Area feature set. 

Bit 9: 

'1' = Supports the DEVICE RESET command. 

Bit 8: 

'1' = Supports the SERVICE interrupt. 

5-112 

C141-E244 

Summary of Contents for MHV2160BT

Page 1: ...C141 E244 01EN MHV2200BT MHV2160BT DISK DRIVES PRODUCT MANUAL ...

Page 2: ...ncidental or consequential damages arising therefrom FUJITSU DISCLAIMS ALL WARRANTIES REGARDING THE INFORMATION CONTAINED HEREIN WHETHER EXPRESSED IMPLIED OR STATUTORY FUJITSU reserves the right to make changes to any products described herein without further notice and without obligation This product is designed and manufactured for use in standard applications such as office work personal device...

Page 3: ...Revision History 1 1 Edition Date Revised section 1 Added Deleted Altered Details 01 2006 04 24 1 Section s with asterisk refer to the previous edition when those were deleted C141 E244 ...

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Page 5: ...gives an overview of the disk drive and describes their features CHAPTER 2 Device Configuration This chapter describes the internal configurations of the disk drive and the configuration of the systems in which they operate CHAPTER 3 Installation Conditions This chapter describes the external dimensions installation conditions and switch settings of the disk drive CHAPTER 4 Theory of Device Operat...

Page 6: ...entered followed below by the indented message A wider line space precedes and follows the alert message to show where the alert message begins and ends The following is an example Example Data corruption Avoid mounting the disk drive near strong magnetic sources such as loud speakers Ensure that the disk drive is not affected by external magnetic fields The main alert messages in the text are als...

Page 7: ... this manual and forward it to the address described in the sheet Liability Exception Disk drive defects refers to defects that involve adjustment repair or replacement Fujitsu is not liable for any other disk drive defects such as those caused by user misoperation or mishandling inappropriate operating environments defects in the power supply or cable problems of the host system or other causes o...

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Page 9: ...edure correctly Task Alert message Page Normal Operation Data corruption Avoid mounting the disk near strong magnetic sources such as loud speakers Ensure that the disk drive is not affected by external magnetic fields Damage Do not press the cover of the disk drive Pressing it too hard the cover and the spindle motor contact which may cause damage to the disk drive Static When handling the device...

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Page 11: ...L C141 E244 This manual Device Overview Device Configuration Installation Conditions Theory of Device Operation Interface Operations MHV2200BT MHV2160BT DISK DRIVES MAINTENANCE MANUAL C141 F080 Maintenance and Diagnosis Removal and Replacement Procedure C141 E244 vii ...

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Page 13: ...cifications 1 9 1 5 Acoustic Noise 1 9 1 6 Shock and Vibration 1 10 1 7 Reliability 1 11 1 8 Error Rate 1 12 1 9 Media Defects 1 12 1 10 Load Unload Function 1 12 1 10 1 Recommended power off sequence 1 13 1 11 Advanced Power Management APM 1 13 1 12 Interface Power Management IPM 1 15 1 12 1 Host initiated interface power management HIPM 1 15 1 12 2 Device initiated interface power management DIP...

Page 14: ... cable connection 3 10 3 3 5 Note about SATA interface cable connection 3 10 CHAPTER 4 Theory of Device Operation 4 1 4 1 Outline 4 2 4 2 Subassemblies 4 2 4 2 1 Disk 4 2 4 2 2 Spindle 4 2 4 2 3 Actuator 4 2 4 2 4 Air filter 4 3 4 3 Circuit Configuration 4 3 4 4 Power on Sequence 4 5 4 5 Self calibration 4 7 4 5 1 Self calibration contents 4 7 4 5 2 Execution timing of self calibration 4 8 4 5 3 C...

Page 15: ...ions 5 7 5 1 4 Connector pinouts 5 10 5 1 5 P11 function 5 11 5 1 5 1 Staggered Spin up 5 11 5 1 5 2 Driving Ready LED 5 11 5 1 6 Hot Plug 5 13 5 2 Logical Interface 5 14 5 2 1 Communication layers 5 15 5 2 2 Outline of the Shadow Block Register 5 16 5 2 3 Outline of the frame information structure FIS 5 17 5 2 3 1 FIS types 5 17 5 2 3 2 Register Host to Device 5 17 5 2 3 3 Register Device to Host...

Page 16: ... MICROCODE X 92 5 45 10 STANDBY IMMEDIATE X 94 or X E0 5 47 11 IDLE IMMEDIATE X 95 or X E1 UNLOAD IMMEDIATE X 95 or X E1 5 48 12 STANDBY X 96 or X E2 5 50 13 IDLE X 97 or X E3 5 51 14 CHECK POWER MODE X 98 or X E5 5 53 15 SLEEP X 99 or X E6 5 54 16 SMART X B0 5 55 17 DEVICE CONFIGURATION X B1 5 85 18 READ MULTIPLE X C4 5 90 19 WRITE MULTIPLE X C5 5 93 20 SET MULTIPLE MODE X C6 5 95 21 READ DMA X C...

Page 17: ... X 35 5 152 44 SET MAX ADDRESS EXT X 37 5 153 45 WRITE MULTIPLE EXT X 39 5 155 46 WRITE LOG EXT X 3F 5 156 47 READ VERIFY SECTOR S EXT X 42 5 160 48 FLUSH CACHE EXT X EA 5 161 49 WRITE MULTIPLE FUA EXT X CE 5 162 50 WRITE DMA FUA EXT X 3D 5 163 51 READ FP DMA QUEUED X 60 5 164 52 WRITE FP DMA QUEUED X 61 5 165 5 3 3 Error posting 5 166 5 4 Command Protocol 5 168 5 4 1 Non data command protocol 5 1...

Page 18: ...e mode 6 8 6 2 2 Power commands 6 10 6 3 Power Save Controlled by Interface Power Management IPM 6 11 6 3 1 Power save mode of the interface 6 11 6 4 Read ahead Cache 6 13 6 4 1 Data buffer structure 6 13 6 4 2 Caching operation 6 14 6 4 3 Using the read segment buffer 6 16 6 4 3 1 Miss hit 6 16 6 4 3 2 Sequential hit 6 17 6 4 3 3 Full hit 6 17 6 4 3 4 Partial hit 6 19 6 5 Write Cache 6 20 6 5 1 C...

Page 19: ...ion 4 4 Figure 4 2 Circuit configuration 4 5 Figure 4 3 Power on operation sequence 4 6 Figure 4 4 Read write circuit block diagram 4 9 Figure 4 5 Frequency characteristic of programmable filter 4 10 Figure 4 6 Block diagram of servo control circuit 4 12 Figure 4 7 Physical sector servo configuration on disk surface 4 16 Figure 4 8 Servo frame format 4 17 Figure 5 1 Interface signals 5 2 Figure 5 ...

Page 20: ... 173 Figure 5 17 DMA data out command protocol 5 174 Figure 5 18 READ FP DMA QUEUED command protocol 5 176 Figure 5 19 WRITE FP DMA QUEUED command protocol 5 177 Figure 5 20 Power on sequence 5 178 Figure 5 21 COMRESET sequence 5 179 Figure 6 1 Response to power on when the host is powered on earlier than the device 6 2 Figure 6 2 Response to power on when the device is powered on earlier than the...

Page 21: ... code 5 43 Table 5 8 Operation of DOWNLOAD MICROCODE 5 45 Table 5 9 Example of rewriting procedure of data 512K Bytes 80000h Bytes of microcode 5 46 Table 5 10 Features Field values subcommands and functions 5 56 Table 5 11 Format of device attribute value data 5 60 Table 5 12 Format of guarantee failure threshold value data 5 60 Table 5 13 Off line data collection status 5 63 Table 5 14 Self test...

Page 22: ... IDENTIFY DEVICE command 5 106 Table 5 35 Features field values and settable modes 5 118 Table 5 36 Contents of SECURITY SET PASSWORD data 5 124 Table 5 37 Relationship between combination of Identifier and Security level and operation of the lock function 5 124 Table 5 38 Contents of security password 5 132 Table 5 39 Data format of Read Log Ext log page 10h 5 147 Table 5 40 Tag field information...

Page 23: ...a Defects 1 10 Load Unload Function 1 11 Advanced Power Management APM 1 12 Interface Power Management IPM Overview and features are described in this chapter and specifications and power requirement are described The disk drive is 2 5 inch hard disk drives with built in disk controllers These disk drives use the SATA interface protocol which has a high speed interface data transfer rate C141 E244...

Page 24: ...ata rate up to 51 8 MB s The disk drive supports an external data rate 1 5 Gbps 150 MB s Serial ATA Generation 1 And the disk drive realizes a high performance by high speed transfer rate combined with Native Command Queuing NCQ 5 Average positioning time Use of a rotary voice coil motor in the head positioning mechanism greatly increases the positioning speed The average positioning time is 12 ms...

Page 25: ... of a disk read command the disk drive automatically reads the subsequent data block and writes it to the data buffer read ahead operation This cache system enables fast data access The next disk read command would normally cause another disk access But if the read ahead data corresponds to the data requested by the next read command the data in the buffer can be transferred instead 4 Error correc...

Page 26: ...imum Full 1 5 ms typ Read 12 ms typ 22 ms typ Start time 3 5 sec typ Interface Compliant with ATA ATAPI 7 SATA II Ext to SATA1 0a SATA II Electrical Spec 1 0 Data Transfer Rate 2 To From Media To From Host 51 8 MB s Max 1 5 Gbps 150 MB s Data Buffer Size 3 8 MB 8 388 608 bytes Physical Dimensions Height Width Depth 12 5 mm 100 0 mm 70 0 mm 4 Weight 135 g Max 1 Capacity under the LBA mode 2 1 GB is...

Page 27: ...r Table 1 2 lists the model names and product numbers of the disk drive The model name does not necessarily correspond to the product number as listed in Table 1 2 since some models have been customized and have specifications that are different from those for the standard model If a disk drive is ordered as a replacement drive the product number must be the same as that of the drive being replace...

Page 28: ...ximum 100 mV peak to peak Frequency DC to 1 MHz 3 Slope of an input voltage at rise The following figure shows the restriction of the slope which is 5 V input voltage at rise The permissible range of 5 V slope is from 1V 20 µsec to 1V 20 msec under the voltage range is between 2 0V and 4 5V Figure 1 1 Permissible range of 5V rise slope 1 6 C141 E244 ...

Page 29: ...re isn t to occur at 5 V when power is turned off and a thing with no ringing Permissible level 0 2 V Voltage V 5 0 100 200 300 400 500 600 700 800 Time ms 4 3 2 1 0 1 Figure 1 2 The example of negative voltage waveform at 5 V when power is turned off C141 E244 1 7 ...

Page 30: ...nk E MHV2200BT 0 0031 W GB rank E MHV2160BT 1 Maximum current and power at starting spindle motor 2 Current and power level when the operation command that accompanies a transfer of 63 sectors is executed 3 times in 100 ms 3 Power requirements reflect typical values for 5 V power 4 Energy efficiency based on the Law concerning the Rational Use of Energy indicates the value obtained by dividing pow...

Page 31: ...fications Item Specification Temperature Operating Non operating Thermal Gradient 5 C to 55 C ambient 5 C to 60 C disk enclosure surface 40 C to 65 C 20 C h or less Humidity Operating Non operating Maximum Wet Bulb 8 to 90 RH Non condensing 5 to 95 RH Non condensing 29 C Operating 40 C Non operating Altitude relative to sea level Operating Non operating 300 to 3 000 m 300 to 12 000 m 1 5 Acoustic ...

Page 32: ...d vibration specification Table 1 6 Shock and vibration specification Item Specification Vibration Swept sine 1 4 octave per minute Operating Non operating 5 to 500 Hz 9 8m s2 0 peak 1G 0 peak without non recovered errors 5 to 500 Hz 49m s2 0 peak 5G 0 peak no damage Shock half sine pulse Operating Non operating 2940 m s2 0 peak 300G 0 peak 2ms duration without non recovered errors 8820 m s2 0 pea...

Page 33: ...TR is 30 minutes or less if repaired by a specialist maintenance staff member 3 Service life In situations where management and handling are correct the disk drive requires no overhaul for five years when the DE surface temperature is less than 48 C When the DE surface temperature exceeds 48 C the disk drives requires no overhaul for five years or 20 000 hours of operation whichever occurs first R...

Page 34: ...ns 1 9 Media Defects Defective sectors are replaced with alternates when the disk drive is formatted prior to shipment from the factory low level format Thus the hosts see a defect free device Alternate sectors are automatically accessed by the disk drive The user need not be concerned with access to alternate sectors 1 10 Load Unload Function The Load Unload function is a mechanism that loads the...

Page 35: ...Head Unload Standby Immediate command execution 3 Wait Status Checking whether bit 7 of the status field was set to 0 wait to complete STANDBY IMMEDIATE command 4 HDD power supply cutting 1 11 Advanced Power Management APM The disk drive automatically shifts to the power saving mode according to the setting of the APM mode under the idle condition The APM mode can be chosen with a Sector Count fie...

Page 36: ... Mode 0 Mode shifts from Active condition to Active Idle in 0 2 1 2 and to Low Power Idle in 15 minutes Mode 1 Mode shifts from Active condition to Active Idle in 0 1 0 2 seconds and to Low Power Idle in 10 0 27 5 seconds Mode 2 Mode shifts from Active condition to Active Idle in 0 1 0 2 seconds and to Low Power Idle in 10 0 27 5 seconds After 10 0 40 0 seconds in Low Power Idle the mode shifts to...

Page 37: ...IPM modes automatically under the Idle condition 1 Partial mode PMREQ_P is sent when the disk drive requests the Partial mode 2 Slumber mode PMREQ_S is sent when the disk drive requests the Slumber mode I F power states 1 Active state The SATA interface is active and data can be sent and received 2 Partial state The SATA interface is in the Power Down state In this state the interface is switched ...

Page 38: ...4 Table 1 8 Interface power management IPM Mode I F power state Return time to active I F condition Active Active State Active Partial Partial State 5 to 10 µs maximum Power Down Slumber Slumber State 5 to 10 ms maximum Power Down ...

Page 39: ...ice Configuration 2 1 Device Configuration 2 2 System Configuration This chapter describes the internal configurations of the hard disk drives and the configuration of the systems in which they operate C141 E244 2 1 ...

Page 40: ...L type The head unloads the disk out of while the disk is not rotating and loads on the disk when the disk starts 3 Spindle motor The disks are rotated by a direct drive Sensor less DC motor 4 Actuator The actuator uses a revolving voice coil motor VCM structure which consumes low power and generates very little heat The head assembly at the edge of the actuator arm is controlled and positioned by...

Page 41: ...ip for the read write preamplifier It improves data reliability by preventing errors caused by external noise 7 Controller circuit The controller circuit supports Serial ATA interface and it realized a high performance by integration into LSI 2 2 System Configuration 2 2 1 SATA interface Figure 2 2 shows the SATA interface system configuration The disk drive complies with ATA ATAPI 7 SATA II Exten...

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Page 43: ... 3 1 Dimensions 3 2 Mounting 3 3 Connections with Host System This chapter gives the external dimensions installation conditions surface temperature conditions cable connections and switch settings of the hard disk drives C141 E244 3 1 ...

Page 44: ...ot included in these dimensions 2 Dimension from the center of the user tap to the base of the connector pins 3 Length of the connector pins 4 Dimension from the outer edge of the user tap to the center of the connector pins 5 Dimension from the outer edge of the user tap to the innermost edge of the connector pins Figure 3 1 Dimensions 3 2 C141 E244 ...

Page 45: ...fy the specification in Figure 3 2 The tightening torque must be 0 49N m 5kgf cm When attaching the HDD to the system frame do not allow the system frame to touch parts cover and base other than parts to which the HDD is attached 3 Limitation of mounting Note These dimensions are recommended values if it is not possible to satisfy them contact us Screw Screw Details of A 3 0 or less 3 0 or less Fr...

Page 46: ...reather hole mounted to the HDD do not allow this to close during mounting Locating of breather hole is shown as Figure 3 3 For breather hole of Figure 3 3 at least do not allow it around φ 2 4 to block Figure 3 3 Location of breather 3 4 C141 E244 ...

Page 47: ...ng 60 C Provide air circulation in the cabinet such that the PCA side in particular receives sufficient cooling To check the cooling efficiency measure the surface cover temperatures of the DE Regardless of the ambient temperature this surface cover temperature must meet the standards listed in Table 3 1 Figure 3 4 shows the temperature measurement point 1 Figure 3 4 Surface cover temperature meas...

Page 48: ...is not affected by external magnetic fields Damage Do not press the cover of the disk drive Pressing it too hard the cover and the spindle motor contact which may cause damage to the disk drive Static When handling the device disconnect the body ground 500 kΩ or greater Do not touch the printed circuit board but hold it by the edges 6 Handling cautions Please keep the following cautions and handle...

Page 49: ... falling down Do not drop Figure 3 6 Handling cautions Installation 1 Please use the driver of a low impact when you use an electric driver HDD is occasionally damaged by the impact of the driver 2 Please observe the tightening torque of the screw strictly M3 0 49N m 5 kgf cm Recommended equipments Contents Model Maker Wrist strap JX 1200 3056 8 SUMITOMO 3M ESD ESD mat SKY 8A Color Seiden Mat Achi...

Page 50: ...1 Device connector The disk drive has the SATA interface connectors listed below for connecting external devices Figure 3 7 shows the locations of these connectors and terminals SATA interface and power connectors PCA Figure 3 7 Connector locations 3 8 C141 E244 ...

Page 51: ...al segment View from the connector side View from the PCA side Signal segment Figure 3 8 Power supply pins CN1 3 3 3 Connector specifications for host system Table 3 2 lists the recommended specifications for the host interface connectors Table 3 2 The recommended connector specifications for the host system Segment Name Model Manufacturer SATA interface and power supply Host receptacle 67492 0220...

Page 52: ...able connection Take note of the following precaution about plugging a SATA interface cable into the SATA interface connector of the disk drive and plugging the connector into a host receptacle When plugging together the disk drive SATA interface connector and the host receptacle or SATA interface cable connector do not apply more than 10 kgf of force in the connection direction once they are snug...

Page 53: ...guration 4 4 Power on Sequence 4 5 Self calibration 4 6 Read write Circuit 4 7 Servo Control This chapter explains basic design concepts of the disk drive Also this chapter explains subassemblies of the disk drive each sequence servo control and electrical circuit blocks C141 E244 4 1 ...

Page 54: ...n outer diameter of 65 mm and an inner diameter of 20 mm Servo data is recorded on each cylinder total 162 Servo data written at factory is read out by the read head For servo data see Section 4 7 4 2 2 Spindle The spindle consists of a disk stack assembly and spindle motor The disk stack assembly is activated by the direct drive sensor less DC spindle motor which has a speed of 4 200 rpm 1 The sp...

Page 55: ...SI with MCU and HDC The PreAMP consists of the write current switch circuit that flows the write current to the head coil and the voltage amplifier circuit that amplitudes the read output from the head The RDC is the read demodulation circuit using the Modified Extended Partial Response MEEPR and contains the Viterbi detector programmable filter adaptable transversal filter times base generator da...

Page 56: ... Major functions are listed below Serial ATA interface control and data transfer control Data buffer management Sector format control Defect management ECC control Error recovery and self diagnosis Figure 4 1 Power supply configuration 4 4 C141 E244 ...

Page 57: ...4 4 Power on Sequence Figure 4 2 Circuit configuration 4 4 Power on Sequence Figure 4 3 describes the operation sequence of the disk drive at power on The outline is described below C141 E244 4 5 ...

Page 58: ... the heads onto the SA area and reads out the system information e The drive becomes ready The host can issue commands f The disk drive executes self calibration This collects data for VCM torque and mechanical external forces applied to the actuator and updates the calibrating value End d Initial on track and read out of system information e Execute self calibration f Drive ready state command wa...

Page 59: ...n The measured values are stored in the SA cylinder In the self calibration the compensating value is updated using the value in the SA cylinder 2 Compensating open loop gain Torque constant value of the VCM has dispersion for each drive and varies depending on the cylinder that the head is positioned To realize the high speed seek operation the value that compensates torque constant value change ...

Page 60: ... command without waiting for a long time even when the disk drive is performing self calibration The command execution wait time is about maximum 72 ms When the error rate of data reading writing or seeking becomes lower than the specified value self calibration is performed to maintain disk drive stability If the disk drive receives a command execution request from the host while performing self ...

Page 61: ...o that abnormal write does not occur 4 6 2 Write circuit The write data is transferred from the hard disk controller HDC to the RDC in LSI The write data is sent to the PreAMP as differential signal from LSI and the data is written onto the media 1 Write precompensation Write precompensation compensates during a write process for write non linearity generated at reading RDX RDY WDX WDY Servo Burst...

Page 62: ... amplifier output is maintained at a constant level even when the head output fluctuates due to the head characteristics or outer inner head positions 2 Programmable filter circuit The programmable filter circuit has a low pass filter function that eliminates unnecessary high frequency noise component and a high frequency boost up function that equalizes the waveform of the read signal Cut off fre...

Page 63: ...s data according to the survivor path sequence 4 6 4 Digital PLL circuit The drive uses constant density recording to increase total capacity This is different from the conventional method of recording data with a fixed data transfer rate at all data area In the constant density recording method data area is divided into zones by radius and the data transfer rate is set so that the recording densi...

Page 64: ... the track containing the desired data To turn the disk at a constant velocity the actuator motor is controlled according to the servo data that is written on the data side beforehand 4 7 1 Servo control circuit Figure 4 6 is the block diagram of the servo control circuit The following describes the functions of the blocks Figure 4 6 Block diagram of servo control circuit 4 12 C141 E244 ...

Page 65: ...ead position from the servo data on the data surface From the servo area on the data area surface via the data head the burst signals of EVEN1 ODD EVEN2 are output as shown in Figure 4 8 in subsequent to the servo mark gray code that indicates the cylinder position and index information The servo signals do A D convert by Fourier demodulator in the servo burst capture circuit At that time the AGC ...

Page 66: ...plitude circuit that receives signals from the spindle motor control circuit and feeds currents to the spindle motor 7 VCM current sense resistor CSR This resistor controls current at the power amplifier by converting the VCM current into voltage and feeding back 4 14 C141 E244 ...

Page 67: ... band This area is located inside the user area and the rotational speed of the VCM can be controlled on this cylinder area for head moving 2 Data area This area is used as the user data area and SA area 3 Outer guard band This area is located at outer position of the user data area and the rotational speed of the spindle can be controlled on this cylinder area for head moving C141 E244 4 15 ...

Page 68: ...Theory of Device Operation Figure 4 7 Physical sector servo configuration on disk surface 4 16 C141 E244 ...

Page 69: ...t 1 Write read recovery This area is used to absorb the write read transient and to stabilize the AGC 2 Servo mark This area generates a timing for demodulating the gray code and position demodulating the burst signal by detecting the servo mark 3 Gray code including sector address bits This area is used as cylinder address The data in this area is converted into the binary data by the gray code d...

Page 70: ...e head is stopped at the reference cylinder from there Track following control starts 2 Seek operation Upon a data read write request from the host the MPU confirms the necessity of access to the disk If a read write instruction is issued the MPU seeks the desired track The MPU feeds the VCM current via the D A converter and power amplifier to move the head The MPU calculates the difference speed ...

Page 71: ...ase U phase to W phase and V phase to W phase after that repeating this order d During phase switching the spindle motor starts rotating in low speed and generates a counter electromotive force The SVC detects this counter electromotive force and reports to the MPU using a PHASE signal for speed detection e The MPU is waiting for a PHASE signal When no phase signal is sent for a specific period th...

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Page 73: ...rface 5 1 Physical Interface 5 2 Logical Interface 5 3 Host Commands 5 4 Command Protocol 5 5 Power on and COMRESET This chapter gives details about the interface and the interface commands and timings C141 E244 5 1 ...

Page 74: ...log front end GND Figure 5 1 Interface signals An explanation of each signal is provided below TX TX These signals are the outbound high speed differential signals that are connected to the serial ATA cable RX RX These signals are the inbound high speed differential signals that are connected to the serial ATA cable TxData Serially encoded 10b data attached to the high speed serial differential li...

Page 75: ...MWAKE out of band signal is being detected COMRESET COMINIT Host Signal from the out of band detector that indicates the COMINIT out of band signal is being detected Device Signal from the out of band detector that indicates the COMRESET out of band signal is being detected 5VDC GND 5VDC 5 V power supply to the disk drive GND Ground for each signal and 5 V power supply C141 E244 5 3 ...

Page 76: ... During OOB signaling transmissions the differential and common mode levels of the signal lines shall comply with the same electrical specifications as for in band data transmission specified as follows COMRESET COMINIT 106 7 ns 320 ns COMWAKE 106 7 ns 106 7 ns 5 4 C141 E244 ...

Page 77: ...he transmitter does not have the next payload data ready for transmission HOLD is also transmitted on the backchannel when a receiver is not ready to receive additional payload data HOLDA Hold acknowledge This primitive is sent by a transmitter as long the HOLD primitive is received by its companion receiver PMNAK Power management denial Sent in response to a PMREQ_S or PMREQ_P when a receiving no...

Page 78: ...ent node host or device is ready to receive payload SOF Start of frame Start of a frame Payload and CRC follow to EOF SYNC Synchronization Synchronizing primitive always idle WTRM Wait for frame termination After transmission of any of the EOF the transmitter will transmit WTRM while waiting for reception status from receiver X_RDY Transmission data ready Current node host or device has payload re...

Page 79: ... 6667 666 4333 670 2333 ftol TX Frequency Long Term Stability ppm 350 350 fSSC Spread Spectrum Modulation Frequency kHz 30 33 SSCtol Spread Spectrum Modulation Deviation ppm 5000 0 Vcm dc DC Coupled Common Mode Voltage mV 250 200 450 Vcm ac coupled AC Coupled Common Mode Voltage mV 0 2000 Zdiff Nominal Differential Impedance ohm 100 Cac coupling AC Coupling Capacitance nF 12 tsettle cm Common Mode...

Page 80: ...TX TX Differential Output Voltage mVppd 500 400 600 Differential nominal measured at Serial ATA connector on transmit side 250mV differential seria l ATA connector t20 80TX TX Rise Fall Time ps UI 0 15 20 80 0 41 20 80 Rise 20 80 at transmitter Fall 80 20 at transmitter tskewTX TX Differential Skew ps 20 TJ at Connector Data Data 5UI UI 0 355 DJ at Connector Data Data 5UI UI 0 175 TJ at Connector ...

Page 81: ... Vthresh OOB Signal Detection Threshold mVppd 100 50 200 UIOOB UI During OOB Signaling ps 666 67 646 67 686 67 COMINIT COMRESET and COMWAKE Transmit Burst Length UIOOB 160 COMINIT COMRESET Transmit Gap Length UIOOB 480 COMWAKE Transmit Gap Length UIOOB 160 Units May detect Shall detect Shall not detect Comments COMWAKE Gap Detection Windows ns 55 T 175 101 3 T 112 T 55 or 175 COMINIT COMRESET Gap ...

Page 82: ...charge 2nd mate P8 V5 5 V power P9 V5 5 V power P10 Gnd 2nd mate P11 Staggered Spin up Mode Ready LED Staggered Spin up mode detect for input Ready LED drive for output For the specification of P11 see Section 5 1 5 in next page When the host system does not use these function the corresponding pin to be mated with P11 in the power cable receptacle connector shall be grounded P12 Gnd 1st mate P13 ...

Page 83: ...e Enable The disk drive does not spin up until after successful Phy initialization at power on Default setting b P11 Grounded 0 8 V or less Staggered Mode Disable The disk drive spins up at power on c P11 High level The P11 line in the host system is pulled up by resistor recommended value 1 to 5 1 kΩ to power supply in the host system Recommended voltage 2V 3 3V or less Staggered Mode Enable The ...

Page 84: ...Interface Table 5 3 Requirements for P11 as an output pin Asserted Deasserted VACT 0 7V 0 7V IACT 50uA Figure 5 2 Example of the circuit for driving Ready LED 5 12 C141 E244 ...

Page 85: ...valent circuit of 5V power supply at Hot Plugging is in the following figure It is necessary to choose pre charge resistor RL value which is in permissible range of 5V power supply specification at the host system Refer to the equivalent circuit when the optimized value of pre charge resistor RL It is recommended to choose the minimum value which is in permissible range of 5V power supply specific...

Page 86: ...ice and between layers at the same level that link the host and device Figure 5 3 is a conceptual diagram of the communication layers Host Software control Buffer Memory DMA engine s Host located layers Physical Layer Link Layer Transport Layer Device located layers Physical Layer Link Layer Transport Layer Device Software control Buffer memory DMA engine s Application layer 4 Transport layer 3 Li...

Page 87: ...uests between the host system and device Encodes serial data as 10 or 8 bit data then converts it into DWORD data Inserts auxiliary signals SOF CRC and EOF deletes auxiliary signals and communicates with the transport and physical layers Transport layer Exchanges data in communication with the link layer and builds the frame information structure FIS Contains a Shadow Block Register Reflects the F...

Page 88: ...unt exp Sector Count Sector Number exp Sector Number Sector Number exp Sector Number Cylinder Low exp Cylinder Low Cylinder Low exp Cylinder Low Cylinder High exp Cylinder High Cylinder High exp Cylinder High Device Head Status Command Control Block registers Alternate Status Device Control Note Each of the Sector Count Sector Number Cylinder Low and Cylinder High fields has a higher order field u...

Page 89: ...or Host to Device Bidirectional DMA Setup Set Device Bits Device to Host SetDB BIST Active Bidirectional BIST Active PIO Setup Device to Host PIO Setup Data Host to Device or Device to Host Bidirectional DATA 5 2 3 2 Register Host to Device The Register Host to Device FIS has the following layout 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 ...

Page 90: ... 1 Reserved 0 LBA High exp LBA Mid exp LBA Low exp 0 2 Reserved 0 Reserved 0 Sector Count exp Sector Count 3 Reserved 0 Reserved 0 Reserved 0 Reserved 0 4 Figure 5 5 Register Device to Host FIS layout The Register Device to Host FIS is used when information concerning the Shadow Register Block in the host adapter is updated This FIS indicates that the device has completed a command operation Furth...

Page 91: ...0 2 Reserved 0 3 DMA Buffer Offset 4 DMA Transfer Count 5 Reserved 0 6 Figure 5 7 DMA Setup Device to Host or Host to Device FIS layout The DMA Setup Device to Host or Host to Device FIS communicates the start of a first party DMA access to the host system This FIS is used to request the host system or device to set up the DMA controller before the start of a DMA data transfer A Auto Active bit If...

Page 92: ...IS can be sent by either the host system or device The following combinations of pattern definitions are supported Table 5 5 BIST combinations T A S L F P V SC Reg Contents 1 1 09h SATA Phy Analog Loopback Mode 1 10h Far End Retimed Loopback Mode 1 1 C0h No ALIGN Transmit_only Mode Scramble ON 1 1 1 1 E0h No ALIGN Transmit_only Mode Scramble OFF 1 1 1 C4h No ALIGN Transmit_only with primitive Mode...

Page 93: ...Type 5Fh 0 Dev Head Cyl High Cyl Low Sector Number 1 Reserved 0 Cyl High exp Cyl Low exp Sector Num exp 0 2 E_Status Reserved 0 Sector Count exp Sector Count 3 Reserved 0 Transfer Count 4 Figure 5 10 PIO Setup Device to Host FIS layout The PIO Setup FIS is a device to host FIS FIS Type 5Fh The PIO Setup FIS is used by the device to provide the host adapter with the data transfer count and DRQ bloc...

Page 94: ...r Block E_Status Contains the new value of the status field of the task file block for correct synchronization of data transfers to host Error Contains the new value of the Error field of the Command Block at the conclusion of all subsequent Data to Device frames I Interrupt bit This bit reflects the interrupt bit line of the device R Reserved 0 Sector Count Holds the contents of the sector count ...

Page 95: ...tate if both the BSY bit and the DRQ bit in the shadow Status field are zero when the frame is received Error Contains the new value of the Error register of the Shadow Field Block Status Hi Contains the new value of bits 6 5 and 4 of the Status field of the Shadow Field Block Status Lo Contains the new value of bits 2 1 and 0 of the Status field of the Shadow Field Block SActive The SActive field...

Page 96: ...ble error and SB not found Or SATA Frame Error Write SFRW This bit indicates that a SATA communication error has been encountered during the write process In this case bit4 and bit2 are set both Bit 3 SATA Frame Error Read SF RR This bit indicates that a SATA communication error has been encountered during the read process In this case bit3 and bit2 are set both Bit 2 Aborted Command ABRT This bit...

Page 97: ... number of remaining sectors that the data has not been transferred due to the error However as of the last sector of PIO transfer SC 1 indicates the normal completion The contents of this field also have other definitions Refer to 5 4 4 Sector Number Field exp The contents of this field indicates the starting sector number for the subsequent command The sector number should be between X 01 and th...

Page 98: ...this field indicate the device and the head number When executing INITIALIZE DEVICE PARAMETERS command the contents of this field defines the number of heads minus 1 a maximum head No Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 X L X X HS3 HS2 HS1 HS0 Bit 7 Unused Bit 6 L 0 for CHS mode and 1 for LBA mode Bit 5 Unused Bit 4 Unused Bit 3 HS3 CHS mode head address 3 2 3 bit 27 for LBA mode Unuse...

Page 99: ...e Ready DRDY bit This bit indicates that the device is capable to respond to a command The IDD checks its status when it receives a command If an error is detected not ready state the IDD clears this bit to 0 This is cleared to 0 at power on and it is cleared until the rotational speed of the spindle motor reaches the steady speed Bit 5 Device Write Fault DF bit This bit indicates that a device fa...

Page 100: ...uired to execute the DASP handshake 11 E_Status Field This field is in the PIO Setup FIS The field contents are the same as those described in 8 Status Field However the values in the Status field are those before a PIO data transfer and the values in the E_Status field are those when a PIO data transfer is completed 12 DMA Buffer Offset Field This field is in the DMA Setup FIS representing byte o...

Page 101: ...eters Table 5 6 lists the supported commands command code and the related fields to be written necessary parameters at command execution Table 5 6 Command code and parameters 1 3 COMMAND CODE Bit PARAMETER USED COMMAND NAME 7 6 5 4 3 2 1 0 FR SC SN CY DH RECALIBRATE 0 0 0 1 X X X X N N N N D READ SECTOR S 0 0 1 0 0 0 0 R N Y Y Y Y WRITE SECTOR S 0 0 1 1 0 0 0 R N Y Y Y Y WRITE VERIFY 0 0 1 1 1 1 0...

Page 102: ... 0 0 N N N N D FLUSH CACHE 1 1 1 0 0 1 1 1 N N N N D WRITE BUFFER 1 1 1 0 1 0 0 0 N N N N D IDENTIFY DEVICE 1 1 1 0 1 1 0 0 N N N N D IDENTIFY DEVICE DMA 1 1 1 0 1 1 1 0 N N N N D SET FEATURES 1 1 1 0 1 1 1 1 Y N N N D SECURITY SET PASSWORD 1 1 1 1 0 0 0 1 N N N N D SECURITY UNLOCK 1 1 1 1 0 0 1 0 N N N N D SECURITY ERASE PREPARE 1 1 1 1 0 0 1 1 N N N N D SECURITY ERASE UNIT 1 1 1 1 0 1 0 0 N N N ...

Page 103: ...D FLUSH CACHE EXT 1 1 1 0 1 0 1 0 N N N N D WRITE MULTIPLE FUA EXT 1 1 0 0 1 1 1 0 N Y Y Y D WRITE DMA FUA EXT 0 0 1 1 1 1 0 1 N Y Y Y D READ FP DMA QUEUED 0 1 1 0 0 0 0 0 Y Y Y Y D WRITE FP DMA QUEUED 0 1 1 0 0 0 0 1 Y Y Y Y D CY cylinder field DH device head field FR features field SC sector count field SN sector number field R Retry at error 1 Without retry 0 With retry Y Necessary to set param...

Page 104: ... 8 SN EXP LBA 31 24 SN EXP LBA 31 24 SN Start sector No LBA 7 0 SN End sector No LBA 7 0 SC EXP Transfer sector count 15 8 SC EXP X 00 SC Transfer sector count 7 0 SC X 00 FR EXP xx FR xx ER Error information CH EXP Cylinder High Field EXP CL EXP Cylinder Low Field EXP CM Command Field DH Device Head Field ER Error Field FR EXP Features Field EXP L LBA Logical Block Address setting bit SN EXP Sect...

Page 105: ...ditions 1 An error was detected during head positioning ST 51h ER 02h 2 A SATA communication error occurred ST 51h ER 14h At command issuance Shadow Block Registers setting contents CM 0 0 0 1 x x x x DH x x x x xx CH CL SN SC FR xx xx xx xx xx At command completion Shadow Block Registers contents to be read ST Status information DH x x x x xx CH CL SN SC ER xx xx xx xx Error information Note Also...

Page 106: ... contain the cylinder head and sector addresses in the CHS mode or logical block address in the LBA mode of the last sector read If an unrecoverable disk read error occurs in a sector the read operation is terminated at the sector where the error occurred Shadow block registers contain the cylinder the head and the sector addresses of the sector in the CHS mode or the logical block address in the ...

Page 107: ...ector No LBA LSB Transfer sector count xx R Retry At command completion Shadow Block Registers contents to be read ST Status information DH x L x x HDNo LBA CH CL SN SC ER End cylinder No MSB LBA End cylinder No LSB LBA End sector No LBA LSB 01 1 Error information 1 If the command is terminated due to an error the remaining number of sectors of which data was not transferred C141 E244 5 35 ...

Page 108: ...es of the last sector written If an disk error occurs during multiple sector write operation the write operation is terminated at the sector where the error occurred Shadow block registers contain the cylinder the head the sector addresses in the CHS mode or the logical block address in the LBA mode of the sector where the error occurred Error reporting conditions 1 A specified address exceeds the...

Page 109: ...LBA LSB Transfer sector count xx R Retry At command completion Shadow Block Registers contents to be read ST Status information DH x L x x HDNo LBA CH CL SN SC ER End cylinder No MSB LBA End cylinder No LSB LBA End sector No LBA LSB 00 1 Error information 1 If the command was terminated because of an error the number of sectors for which data has not been written is set in this field C141 E244 5 3...

Page 110: ...ansfer of dummy data ST 51h ER 10h 3 A write fault was detected when the write cache was disabled ST 71h ER 10h 4 While the write cache is enabled if the status indicating a completed transfer STS 50h is returned and a data write operation failed because a write fault was detected during the data write operation Abort will be returned for all subsequent ATA commands ST 71h ER 04h This state is cle...

Page 111: ...on DH x L x x HDNo LBA CH CL SN SC ER Start cylinder No MSB LBA Start cylinder No LSB LBA Start sector No LBA LSB 00 1 Error information 1 If the command is terminated because of an error the number of remaining sectors for which data has not been written or verified is set in this field C141 E244 5 39 ...

Page 112: ...e LBA mode of the sector where the error occurred The Sector Count field indicates the number of sectors that have not been verified Error reporting conditions 1 A specified address exceeds the range where read operations are allowed ST 51h ER 10h 2 The range where read operations are allowed will be exceeded by an address during a read operation ST 51h ER 10h 3 An uncorrectable disk read error oc...

Page 113: ...information DH x L x x HDNo LBA CH CL SN SC ER Start cylinder No MSB LBA Start cylinder No LSB LBA Start sector No LBA LSB 00 1 Error information 1 If the command is terminated due to an error the remaining number of sectors of which data was not transferred is set in this field C141 E244 5 41 ...

Page 114: ...range where the head can be positioned ST 51h ER 10h 2 Head positioning is not possible because an error occurred ST 51h ER 10h 3 A SATA communication error occurred ST 51h ER 14h At command issuance Shadow Block Registers setting contents CM 0 1 1 1 x x x x DH x L x x HD No LBA CH CL SN SC FR Start cylinder No MSB LBA Start cylinder No LSB LBA Start sector No LBA LSB xx xx At command completion S...

Page 115: ... detected HDC diagnostic error Data buffer diagnostic error Memory diagnostic error Reading the system area is abnormal Calibration abnormal Note The device responds to this command with the result of power on diagnostic test Error reporting conditions 1 A SATA communication error occurred ST 51h ER 14h At command issuance Shadow Block Registers setting contents CM 1 0 0 1 0 0 0 0 DH x x x x HD No...

Page 116: ...even after soft reset and COMRESET issuance or power save operation regardless of the setting of disabling the reverting to default setting The operation is always performed in CHS mode with the command ignoring any setting of LBA mode Error reporting conditions 1 00h is specified in the SC field ST 51h ER 04h 2 A SATA communication error occurred ST 51h ER 14h At command issuance Shadow Block Reg...

Page 117: ...iting according to Subcommand code Rewriting is also possible simultaneously with the data transfer Refer to Table 5 8 In the data transfer of Subcommand code 01h transfer by which data is divided into multiple times is possible Refer to Table 5 9 After the designation of rewriting by Subcommand code 07h reactivates in the device for the update of the rewriting microcode of the microcode Table 5 8...

Page 118: ...nsfer of 512 KB Firmware rewriting execution Transfer example 3 1 CMD 92h SN SC 0400h FR 07h Transfer of 512 KB and Firmware rewriting execution Transfer example 4 1 CMD 92h SN SC 0100h FR 0lh 2 CMD 92h SN SC 0100h FR 0lh 3 CMD 92h SN SC 0100h FR 0lh 4 CMD 92h SN SC 0100h FR 07h Transfer of 128 KB 0 to 127 KB from the beginning Transfer from 128 to 255 KB Transfer from 256 to 383 KB Transfer from ...

Page 119: ...t support the APS timer function Error reporting conditions 1 A SATA communication error occurred ST 51h ER 14h At command issuance Shadow Block Registers setting contents CM X 94 or X E0 DH x x x x Xx CH CL SN SC FR xx xx xx xx Xx At command completion Shadow Block Registers contents to be read ST Status information DH x x x x Xx CH CL SN SC ER xx xx xx xx Error information C141 E244 5 47 ...

Page 120: ...Y bit and generates an interrupt This command does not support the APS timer function At command issuance I O registers setting contents 1F7H CM X 95 or X E1 1F6H DH x x x DV xx 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H FR xx xx xx xx xx At command completion I O registers contents to be read 1F7H ST Status information 1F6H DH x x x DV xx 1F5H CH 1F4H CL 1F3H SN 1F2H SC 1F1H ER xx xx xx xx Error inform...

Page 121: ...unt per the device life Even if the device executes reading look ahead operation or executes writing operation the device unloads the head s to the ramp position as soon as possible when received the IDLE IMMEDIATE command with the Unload Feature When the writing operation is stopped the device keeps the unwritten data And the device keeps the unloaded state until receiving a Soft Reset COMRESET o...

Page 122: ... the period specified as the APS timer value the device automatically enters Standby mode If the Sector Count field value is 0 the APS timer is disabled when the command is received Under the standby mode the spindle motor is stopped Thus when the command involving a seek such as READ SECTOR s command is received the device processes the command after driving the spindle motor Error reporting cond...

Page 123: ...andby mode The APS timer is set to prohibition if the Sector Count field s value was 0 when device has received this command The period of timer count is set depending on the value of the Sector Count field as shown below Sector Count field value Point of timer 0 X 00 Timeout disabled 1 to 240 X 01 to X F0 Value 5 seconds 241 to 251 X F1 to X FB Value 240 30 min 252 X FC 21 minutes 253 X FD 8 hrs ...

Page 124: ...Interface At command completion Shadow Block Registers contents to be read ST Status information DH x x x x xx CH CL SN SC ER xx xx xx xx Error information 5 52 C141 E244 ...

Page 125: ...ts the status to the host system Power save mode Sector Count field During moving to Standby mode Standby mode X 00 Idle mode X FF Active mode X FF Error reporting conditions 1 A SATA communication error occurred ST 51h ER 14h At command issuance Shadow Block Registers setting contents CM X 98 or X E5 DH x x x x xx CH CL SN SC FR xx xx xx xx xx At command completion Shadow Block Registers contents...

Page 126: ...In the sleep mode the spindle motor is stopped The only way to release the device from sleep mode is to execute a software or COMRESET Error reporting conditions 1 A SATA communication error occurred ST 51h ER 14h At command issuance Shadow Block Registers setting contents CM X 99 or X E6 DH x x x x xx CH CL SN SC FR xx xx xx xx xx At command completion Shadow Block Registers contents to be read S...

Page 127: ...ylinder Low field and C2h in the Cylinder High field If the key values are incorrect the Aborted Command error is issued If the failure prediction function is disabled the device returns the Aborted Command error to subcommands other than those of the SMART Enable Operations with the Features field set to D8h If the failure prediction function is enabled the device collects and updates data on spe...

Page 128: ...utes were saved then the attributes are saved However if the automatic attribute save function is disabled the attributes are not saved Upon receiving this subcommand a device enables or disables the automatic attribute save function and transfers the RegDH then reports the status It is assumed that it permits in the factory shipment in this drive X D3 SMART SAVE ATTRIBUTE VALUES When the device r...

Page 129: ...ormat See Table 5 22 concerning the SMART selective self test log data format See Table 5 25 concerning the SCT Status Request data format X D6 SMART WRITE LOG A device which receives this sub command when it has prepared to receive data from the host computer it transfers the PIOSU Next it receives data from the host computer and writes the specified log sector in the Sector Number Field SN SC Lo...

Page 130: ...bled when the Sector Count field specification 00 state This setting is preserved whether the drive s power is switched on or off If 24 hours have passed since the power was switched on or since the last time that off line data were collected off line data collection is performed without relation to any command from the host computer The host must regularly issue the SMART READ DATA subcommand Fea...

Page 131: ...atus C2h 2Ch Key failure prediction status 4Fh F4h xx xx Error information The attribute value information is 512 byte data the format of this data is shown the following Table 5 11 The host can access this data using the SMART READ DATE subcommand Features field D0h The guarantee failure threshold value data is 512 byte data the format of this data is shown the following Table 5 12 The host can a...

Page 132: ...ta collection capability 170 171 Trouble prediction capability flag 172 Error logging capability 173 Self test error detection point 174 Simple self test Quick Test execution time min 175 Comprehensive self test Comprehensive Test execution time min 176 Conveyance self test execution time min 177 to 181 Reserved 182 to 1FE Vendor unique 1FF Check sum Table 5 12 Format of guarantee failure threshol...

Page 133: ... Indicates unused attribute data 1 Read Error Rate 2 Throughput Performance 3 Spin Up Time 4 Start Stop Count 5 Reallocated Sector Count 7 Seek Error Rate 8 Seek Time Performance 9 Power On Hours Count 10 Spin Retry Count 12 Drive Power Cycle Count 192 Emergency Retract Cycle Count 193 Load Unload Cycle Count 194 HDA Temperature 195 ECC On the Fly Count 196 Reallocated Event Count 197 Current Pend...

Page 134: ...T is disabled 6 to 15 Reserve bit Current attribute value It indicates the normalized value of the original attribute value The value deviates in a range of 01h to 64h range of 01h to C8h for the Ultra ATA CRC error rate and communication error rate It indicates that the closer the value is to 01h the higher the possibility of a failure The host compares the attribute value with the threshold valu...

Page 135: ...us Table 5 14 Self test execution status Bit Meaning 0 to 3 Remainder of the self test is indicated as a percentage in a range of 0h to 9h corresponding to 0 to 90 4 to 7 Self test execution status 0h Self test has ended successfully or self test has not been executed 1h Self test is suspended by the host 2h Self test is interrupted by a soft reset COMRESET from the host 3h Self test cannot be exe...

Page 136: ...is supported 4 If this bit is 1 it indicates that the SMART Self test function is supported 5 If this bit is 1 it indicates that the SMART Conveyance Self test is supported 6 If this bit is 1 it indicates that the SMART Selective Self test is supported 7 Reserved bits Failure prediction capability flag Table 5 16 Failure prediction capability flag Bit Meaning 0 If this bit is 1 it indicates that t...

Page 137: ...of sector 101 Address 80h Reserved 102 to 13F Address 81h to Address 9Fh 102 and 13F are both the same format as 100 101 140 to 1FF Reserved SMART error logging If the device detects an unrecoverable error during execution of a command received from the host the device registers the error information in the SMART Summary Error Log see Table 5 19 and the SMART Comprehensive Error Log see Table 5 20...

Page 138: ...ld value 34 Sector Count field value 35 Sector Number field value 36 Cylinder Low field value 37 Cylinder High field value 38 Drive Head field value 39 Command field value 3A to 3D Command data structure Elapsed time after the power on sequence unit ms 3E Reserved 3F Error field value 40 Sector Count field value 41 Sector Number field value 42 Cylinder Low field value 43 Cylinder High field value ...

Page 139: ...atus field when an error occurs Total number of drive errors Indicates total number of errors registered in the error log Checksum Two s complement of the lower byte obtained by adding 511 byte data one byte at a time from the beginning Status Bits 0 to 3 Indicates the drive status when received error commands according to the following table Bits 4 to 7 Vendor unique Status Meaning 0 Unclear stat...

Page 140: ...A 1C3 5 th Error Log Data Structure5 Error Log Data Structure 5n 5 1C4 1C5 Total number of drive errors Reserved 1C6 1FE Reserved Reserved 1FF Check sum Check sum n indicates sector number in the Error Log The first sector is 0 SMART Self Test The host computer can issue the SMART Execute Off line Immediate sub command Features field D4h and cause the device to execute a self test When the self te...

Page 141: ...1F9 Self test log 2 to 21 Each log data format is the same as that in byte 02 to 19 1FA 1FB Vendor unique 1FC Self test index 1FD 1FE Reserved 1FF Check sum Self test number Indicates the type of self test executed Self test execution status Same as byte 16Bh of the attribute value Self test index If this is 00h it indicates the status where the self test has never been executed Checksum Two s com...

Page 142: ...der Unique 1Ech 1F3h Current LBA under test 1F4h 1F5h Current Span under test 1F6h 1F7h Feature Flags 1F8h Offline Execution Flag 1F9h Selective Offline Scan Number 1FAh 1FBh Vender Unique Reserved 1FCh 1FDh Selective Self test pending time min 1FEh 1FFh Checksum Test Span Selective self test log provides for the definition of up to five test spans If the starting and ending LBA values for a test ...

Page 143: ...or specific unused 3 When set to one off line scan after selective test is pending 4 When set to one off line scan after selective test is active 5 15 Reserved Bit l shall be written by the host and returned unmodified by the device Bit 3 4 shall be written as zeros by the host and the device shall modify them as the test progress Selective Self test pending time min The selective self test pendin...

Page 144: ...and and the Key Sector Format data of 512 bytes is received from the host and a device execute the specific operation for which the action code For information about the format of the Key Sector Format see Table 5 28 to Table 5 31 X E1 X D5 SCT READ DATA A device that received this subcommand transfers the data table of the number of sectors specified with Sector Count field to the host It is nece...

Page 145: ...Table 5 25 of the device At command issuance Shadow Block Registers setting CM 1 0 1 1 0 0 0 0 DH x x x DV Xx CH CL SN SC FR Key C2h Key 4Fh E0h 01h D5h At command completion Shadow Block Registers contents to be read ST Status information DH x x x DV xx CH CL SN SC ER xx xx xx xx Error information C141 E244 5 73 ...

Page 146: ...if the capacity of the drive is changed via SET MAX EXT DCO 1 It initialized it by data pattern in which all LBA was defined by the LBA SEGMENT ACCESS command action code 0x0002 00Ah Drive State 00h Active 01h not support Standby 02h not support Sleep 03h DST executing in background 04h SMART Off line Data collection executing in background 05h SCT command executing in background 06h FFh Reserved ...

Page 147: ...of SCT command executing in background 030h to 0C7h Reserved 0C8h HDA Temp C Current drive HDA temperature 0C9h Reserved 0CAh Max Temp C Maximum HDA temperature this power cycle 0CBh Reserved 0CCh Life Max Temp C Maximum HDA temperature the life of the device 0CDh to 1DFh Reserved 1E0h to 1FFh Vender specific C141 E244 5 75 ...

Page 148: ...ost command 0009h Background SCT command was terminated because of unrecoverable error 000Ah Invalid function code in LONG SECTOR ACCESS command 000Bh SCT data transfer command was issued without first issuing an SCT command Invalid function code in Feature Control command 000Dh Invalid Feature Code in Feature Control command 000Eh Invalid New State in Feature Control command 000Fh Invalid Option ...

Page 149: ...d executes each function to show in Table 5 28 to Table 5 31 28 bit command At command issuance Shadow Block Registers setting CM 1 0 1 1 0 0 0 0 DH x x Xx x DV CH CL FR E0h SN SC Key C2h Key 4Fh 01h D6h At command completion Shadow Block Registers contents to be read ST Status information DH x x x DV xx CH CL SN SC ER xx xx Error information xx xx C141 E244 5 77 ...

Page 150: ...d 0002h LBA SEGMENT ACCESS See Table 5 28 Write Table 5 28 LBA SEGMENT ACCESS 1 2 Byte Name Value Description 000h 001h Action Code 0002h LBA SEGMENT ACCESS 0001h Repeat Write Pattern It initializes it by data pattern of 32bit specified with byte 014h 017h 002h 003h Function Code 0002h Repeat Sector Pattern It initializes it by data pattern of 1sct transfer by the SCT Write data 004h to 00Bh LBA 8...

Page 151: ...RROR RECOVERY CONTROL 0001h Set New Value The retry processing when making an error in the specified timer 002h 003h Function Code 0002h Return Current Value The timer value of the error recovery being set now is displayed in SN SC field 0001h Read Timer 004h 005h Selection Code 0002h Write Timer 006h 007h Value 2 byte Set to Timer Value x 100 ms Minimum value is 10 sec ex 0000h Disable timeout 00...

Page 152: ... Cache 0001h Allow write cache operation to be determined by ATA Set Feature command 0002h Force Write Cache enabled 0003h Force Write Cache disable Feature Code 0002h Set Write Reordering 0001h Enable Write Reordering 0002h Disable Write Reordering 007h New State 2 byte Feature Code 0003h Set time interval 0000h Invalid 0001h FFFFh Logging interval in minutes ex 0001h Temperature data collection ...

Page 153: ...1h Action Code 0005h SCT DATA TABLE 002h 003h Function Code 0001h Read Data Table 0000h Invalid 0001h Reserved 0002h HAD Temperature History Table See Table 5 30 0003h to CFFFh Reserved 004h 005h Table ID D000h to FFFFh Vender Specific 006h to 1FFh Reserved Reserved C141 E244 5 81 ...

Page 154: ... Max Operation Limit C 007h Over Limit C 008h Min Operation Limit C 009h Under Limit C 00Ah to 01Dh Reserved 01Eh to 01Fh Number of logs that can be recorded in temperature log 020h 021h Index of temperature log 022h to 0A1h Temperature log 128 data Entry 80h temperature log at Power cycle and default value is 80h 022h Temp Log No 0 023h Temp Log No 1 to 0A1h Temp Log No 127 0A2h 1FFh 006h Reserve...

Page 155: ...tting CM 1 0 1 1 0 0 0 0 DH x x x DV Xx CH CL SN SC FR Key C2h Key 4Fh D5h E1h xx At command completion Shadow Block Registers contents to be read ST Status information DH x x x DV xx CH CL SN SC ER xx xx xx xx Error information SCT READ DATA Command issue procedure 1 Issue the SCT set command of action code 0005h 2 Issue the SCT READ DATA command and receive the HDA temperature data from the devi...

Page 156: ...egisters setting CM 1 0 1 1 1 1 1 1 DH x x x DV Xx CH CL SN SC FR Key C2h Key 4Fh E1h D6h xx At command completion Shadow Block Registers contents to be read ST Status information DH x x x DV xx CH CL SN SC ER xx xx xx xx Error information SCT WRITE DATA Command issue procedure 1 Issue the SCT set command of action code 0002h and function code 0002h 2 Issue the SCT write command and the write data...

Page 157: ...d command error is posted FR field Command C0h DEVICE CONFIGURATION RESTORE C1h DEVICE CONFIGURATION FREEZE DEVICE CONFIGURATION IDENTIFY C3h Reserved C2h DEVICE CONFIGURATION SET 00h BFh C4h FFh At command issuance Shadow Block Registers setting contents CM 1 0 1 1 0 0 0 1 x x x x xx CH CL SN SC xx xx xx xx FR DH C0h C1h C2h C3h At command completion Shadow Block Registers contents to be read ST ...

Page 158: ...3 The SET MAX ADDRESS EXT command F9h 37h has been specified with a value in the Host Protected Area ST 51h ER 04h 4 A SATA communication error occurred ST 51h ER 14h DEVICE CONFIGURATION FREEZE LOCK Features Field C1h The DEVICE CONFIGURATION FREEZE LOCK command prevents accidental modification of the Device Configuration Overlay settings After successful execution of a DEVICE CONFIGURATION FREEZ...

Page 159: ...in IDENTIFY information When the bits in these words are cleared the device no longer supports the indicated command mode or feature set If a bit is set in the overlay transmitted by the device that is not set in the overlay received from a DEVICE CONFIGURATION IDENTIFY command no action is taken for that bit After execution of this command the settings are kept regardless of the power on COMRESET...

Page 160: ... and below are supported Bit 0 1 Ultra DMA mode 0 is supported 3 to 6 Maximum LBA address Reflected in IDENTIFY information WORD60 61 WORD100 103 7 X 79CF Command set feature set supported Reflected in IDENTIFY information WORD82 87 Bit 15 Reserved Bit 14 1 Write Read Verify feature supported Bit 13 1 SMART Conveyance self test supported Bit 12 1 SMART Selective self test supported Bit 2 1 SMART e...

Page 161: ...e command queuing supported Bits 15 5 Reserved Bit 4 1 Software Settings Preservation supported Bit 1 1 Non zero buffer offsets in DMA Setup FIS supported 9 X 0000 Reserved for Serial ATA 10 to 254 X 0000 Reserved 255 X xxA5 Bits 15 8 Check sum code This is obtained by calculating the sum of all upper bytes and lower bytes in WORD 0 to 256 and the byte consisting of bits 7 to 0 in WORD 255 and the...

Page 162: ...number of sectors per block is defined by a successful SET MULTIPLE MODE Command The SET MULTIPLE MODE command should be executed prior to the READ MULTIPLE command If the READ MULTIPLE command is issued when the READ MULTIPLE command is disabled the device rejects the READ MULTIPLE command with an ABORTED COMMAND error If an uncorrectable disk read error occurs the read operation stops at the sec...

Page 163: ...e of READ MULTIPLE command Error reporting conditions 1 A specified address exceeds the range where read operations are allowed ST 51h ER 10h 2 The range where read operations are allowed will be exceeded by an address during a read operation ST 51h ER 10h 3 An uncorrectable disk read error occurred ST 51h ER 40h 4 The sync byte indicating the beginning of a sector was not found ST 51h ER 01h 7 An...

Page 164: ...completion Shadow Block Registers contents to be read ST Status information DH x L x x HDNo LBA CH CL SN SC ER End cylinder No MSB LBA End cylinder No LSB LBA End sector No LBA LSB 1 Error information 1 If the command is completed normally the number of remaining sectors is set in this field If the command is terminated because of an error the number of sectors for which data has not been transfer...

Page 165: ...write operation has been attempted for the transferred blocks and partial block The write operation stops at the sector where the error occurred even if the write operation has not reached the end of the block At this time the number of remaining sectors the error sector and subsequent sectors and either cylinder head and sector addresses of the error sector CHS mode or the logical block address o...

Page 166: ... Transfer sector count xx R Retry At command completion Shadow Block Registers contents to be read ST Status information DH x L x x HDNo LBA CH CL SN SC ER Start cylinder No MSB LBA Start cylinder No LSB LBA Start sector No LBA LSB 00 1 Error information 1 If the command was terminated because of an error the number of sectors for which data has not been written is set in this field 5 94 C141 E244...

Page 167: ...ed If the value of the Sector Count field is not a supported block count an ABORTED COMMAND error is posted and the READ MULTIPLE and WRITE MULTIPLE commands are disabled If the contents of the Sector Count field is 0 when the SET MULTIPLE MODE command is issued the READ MULTIPLE and WRITE MULTIPLE commands are disabled When the SET MULTIPLE MODE command operation is completed the device reports t...

Page 168: ...Interface At command completion Shadow Block Registers contents to be read ST Status information DH x x x x xx CH CL SN SC ER xx xx xx Sector count block Error information 5 96 C141 E244 ...

Page 169: ...and either cylinder head and sector addresses CHS mode or the logical block address LBA mode of the sector where the error was detected are stored in the Shadow Block Register 7 An error other than the above errors occurred ST 51h ER 04h When the command is completed either cylinder head and sector addresses CHS mode or the logical block address LBA mode of the last sector is stored in the Shadow ...

Page 170: ...LSB Transfer sector count xx At command completion Shadow Block Registers contents to be read ST Status information DH x L x x HDNo LBA SN SC ER Start cylinder No MSB LBA Start cylinder No LSB LBA Start sector No LBA LSB Error information CH CL 00 1 1 If the command is terminated due to an error the remaining number of sectors of which data was not transferred is set in this field 5 98 C141 E244 ...

Page 171: ...or was detected and either cylinder head and sector addresses CHS mode or the logical block address LBA mode of the sector where the error was detected are stored in the Shadow Block Register A host system can select the following transfer mode using the SET FEATURES command however the transfer speed does not change Multiword DMA transfer mode 0 to 2 Ultra DMA transfer mode 0 to 5 Error reporting...

Page 172: ... LSB Transfer sector count xx At command completion Shadow Block Registers contents to be read ST Status information DH x L HDNo LBA x x CH CL SN SC ER Start sector No LBA LSB Start cylinder No MSB LBA Start cylinder No LSB LBA 00 1 Error information 1 If the command was terminated because of an error the number of sectors for which data has not been written is set in this field 5 100 C141 E244 ...

Page 173: ...ts of the data buffer of the device by issuing this command Error reporting conditions 1 A SATA communication error occurred ST 51h ER 0Ch At command issuance Shadow Block Registers setting contents CM 1 1 1 0 0 1 0 0 DH x x x x xx CH CL SN SC FR xx xx xx xx xx At command completion Shadow Block Registers contents to be read ST Status information DH x x x x xx CH CL SN SC ER xx xx xx xx Error info...

Page 174: ...n case a non recoverable disk write error has occurred while the data is being read the error generation address is put into the shadow block register before ending the command This error sector is deleted from the write cache data Error reporting conditions 1 A SATA communication error occurred ST 51h ER 14h At command issuance Shadow Block Registers setting contents 1 1 0 1 1 1 DH x x x x xx CH ...

Page 175: ...is transferred from the host and the device writes the data to the buffer then reports the status Error reporting conditions 1 A SATA communication error occurred ST 51h ER 14h At command issuance Shadow Block Registers setting contents CM 1 1 1 0 1 0 0 0 DH x x x x xx CH CL SN SC FR xx xx xx xx xx At command completion Shadow Block Registers contents to be read ST Status information DH x x x x xx...

Page 176: ... the device sends the PIO Setup FIS to the host then sends the parameter information including a 512 byte date Table 5 34 shows the values of the parameter words and the meaning in the buffer Error reporting conditions 1 A SATA communication error occurred ST 51h ER 0Ch CM 1 1 1 0 0 1 1 0 DH x x x x xx CH CL SN SC FR xx xx xx xx xx At command completion Shadow Block Registers contents to be read S...

Page 177: ...vice command Error reporting conditions 1 A SATA communication error occurred ST 51h ER 0Ch At command issuance Shadow Block Registers setting contents CM 1 1 1 0 1 1 1 0 DH x x x x xx CL SN SC FR xx xx xx xx CH xx At command completion Shadow Block Registers contents to be read ST Status information DH x x x x xx CH CL SN SC ER xx xx xx xx Error information C141 E244 5 105 ...

Page 178: ... 27 46 Set by a device Model name ASCII code 40 characters left 47 X 8010 Maximum number of sectors per block on READ WRITE MULTIPLE command 48 X 0000 Reserved 49 X 2F00 Capabilities 4 50 X 4000 Capabilities 5 51 X 0200 PIO data transfer mode 6 52 X 0200 Reserved 53 X 0007 Enable disable setting of words 54 58 and 64 70 88 7 54 Variable Number of current Cylinders 55 Variable Number of current Hea...

Page 179: ...on number 11 81 X 0021 Minor version number 82 X 346B Support of command sets 12 83 X 7F09 Support of command sets 13 84 X 60xx Support of command sets function 14 85 15 Valid of command sets function 15 86 16 Valid of command sets function 16 87 17 Default of command sets function 17 88 X xx3F Ultra DMA transfer mode 18 89 Set by a device Security Erase Unit execution time 1 LSB 2 min 19 90 X 000...

Page 180: ...209 X 0000 Reserved 210 211 X xxxx Option Number of verify sectors when Write Read Verify function Mode 3 is specified 31 212 213 X xxxx Option Number of verify sectors when Write Read Verify function Mode 2 is specified 32 214 254 X 0000 Reserved 255 X xxA5 Check sum The 2 complement of the lower order byte resulting from summing bits 7 to 0 of word 0 to 254 and word 255 in byte units 1 Word 0 Ge...

Page 181: ... sequence in order to spin up The Identify information is incomplete 8C73h The device requires the SET FEATURES sub command after the power on sequence in order to spin up The Identify information is incomplete C837h The device requires the SET FEATURES sub command after the power on sequence in order to spin up The Identify information is incomplete Others Reserved 4 Word 49 Capabilities Bits 15 ...

Page 182: ... the word 54 58 8 Word 59 Transfer sector count currently set by READ WRITE MULTIPLE command Bits 15 9 Reserved Bit 8 1 Enable the multiple sector transfer Bits 7 0 Transfer sector count currently set by READ WRITE MULTIPLE command without interrupt supports 2 4 8 and 16 sectors 9 Word 63 Multiword DMA transfer mode Bits 15 11 Reserved Bit 10 1 multiword DMA mode 2 is selected Bit 9 1 multiword DM...

Page 183: ...the Native command queueing Bits 7 4 Reserved Bit 3 Reserved for SATA Bit 2 1 Supports the Gen 2 signaling speed Bit 1 1 Supports the Gen 1 signaling speed 1 5 Gbps Bit 0 Reserved 13 WORD 78 Bits 15 7 Reserved Bit 6 1 Supports the software settings preservation Bit 5 Reserved Bit 4 1 Supports the in order data delivery Bit 3 1 Supports the Power Management initiation from the device to the host sy...

Page 184: ...ved 15 WORD 80 Bits 15 8 Reserved Bit 7 1 ATA ATAPI 7 supported Bit 6 1 ATA ATAPI 6 supported Bit 5 1 ATA ATAPI 5 supported Bit 4 1 ATA ATAPI 4 supported Bit 3 1 ATA 3 supported Bit 2 1 ATA 2 supported Bits 1 0 Undefined 16 WORD 82 Bit 15 Undefined Bit 14 1 Supports the NOP command Bit 13 1 Supports the READ BUFFER command Bit 7 1 Supports the release interrupt Bit 12 1 Supports the WRITE BUFFER c...

Page 185: ...ic Acoustic Management feature set Bit 8 1 Supports the SET MAX Security extending command Bit 7 Reserved Bit 6 1 When the power is turned on spin is started by the SET FEATURES sub command Bit 5 1 Supports the Power Up In Standby set Bit 4 1 Supports the Removable Media Status Notification feature set Bit 3 1 Supports the Advanced Power Management feature set Bit 2 1 Supports the CFA Compact Flas...

Page 186: ... function Bit 9 1 Supports the DEVICE RESET command Bit 8 1 Enables the SERVICE interrupt From the SET FEATURES command Bit 7 1 Enables the release interrupt From the SET FEATURES command Bit 6 1 Enables the read cache function From the SET FEATURES command Bit 5 1 Enables the write cache function Bit 4 1 Enables the P PACKET command set Bit 3 1 Supports the Power Management function Bit 2 1 Suppo...

Page 187: ... always returns the fixed value indicated on the left Bits 13 0 Same definition as WORD 84 22 WORD 88 Bits 15 8 Currently used Ultra DMA transfer mode Bit 14 1 Mode 6 is selected Bit 13 1 Mode 5 is selected Bit 12 1 Mode 4 is selected Bit 10 1 Mode 2 is selected Bit 9 1 Mode 1 is selected Bit 8 1 Mode 0 is selected Bits 7 0 Supportable Ultra DMA transfer mode Bit 6 1 Supports the Mode 6 Bit 5 1 Su...

Page 188: ...xed value indicated on the left Bit 14 1 The device always returns the fixed value indicated on the left Bit 13 1 Each device has several logical sectors per physical sector Bit 12 1 Logical sector of the device is grater than 256 Words Bits 11 4 Reserved Bits 3 0 Logical sector size per physical sector Bit 15 0 Bit 14 1 Bits 13 2 0 Bit 1 1 Write Read Verify feature set is supported Bit 0 1 DRQ bi...

Page 189: ...Table AC5 Supported Bit 4 1 Features Control cmd AC4 Supported Bit 3 1 Error Recovery Control AC3 Supported Bit 2 1 LBA Segment Access AC2 Supported Bit 0 1 SCT command set Supported includes SCT status 31 WORD 210 211 T B D T13 Proposal Verify sector number display when Write Read Verify mode 3 is selected by SET FEATURES command Value 0x0000 0400 to 0x0004 0000 sectors When Mode 3 has not been s...

Page 190: ...e 1 X 04 Enables the automatic reassign Note X 05 Enables the advanced power management function 2 X 06 Enables the Power Up In Standby function Note X 07 Spin up the Power Up In Standby status device Note X 10 Enables the Serial ATA function 3 X 0B Enable Write Read Verify T13 Proposal 5 X 33 Undefined Note X 42 Enables the Acoustic management function 4 X 54 Undefined Note X 55 Disables the read...

Page 191: ...DF Disable DRQ bit shall be zero when ERR bit is one T13 Proposal There is a dummy transferring when the error occurs by Read system command of PIO Note It does not actually function only by displaying Identify Device Note Although there is a response to the command nothing is done At power on the default mode is set as follows Write cache function Enabled Transfer mode PIO Mode 4 Multiworld DMA M...

Page 192: ...Mode The host sets X 03 to the Features field By issuing this command with setting a value to the Sector Count field the transfer mode can be selected Upper 5 bits of the Sector Count register defines the transfer type and lower 3 bits specifies the binary mode value The IDD supports following values in the Sector Count field value If other value than below is specified an ABORTED COMMAND error is...

Page 193: ...d DMA transfer mode X Ultra DMA transfer mode X 2 Advanced Power Management APM The host writes the Sector Count field with the desired power management level and executes this command with the Features field X 05 and then Advanced Power Management is enabled The drive automatically shifts to power saving mode up to the specified APM level when the drive does not receive any commands for a specifi...

Page 194: ...terface power state Transitions 03h 3 Guaranteed In Order Data Delivery 04h 1 Asynchronous Notification 05h 1 Software Settings Preservation 06h 4 1 The device normally responds to the command but performs no operation 2 This feature is disabled when power is on While this function is enabled the device does not return the DMA Activate FIS for the first data sector after the WRITE FP DMA QUEUED co...

Page 195: ...k mode by this command is applied to the seek operation in all command processing 5 Write Read Verify feature sector counts option Specified value of SN Specified value of SC Description 00h Mode 0 Always enable 01h Mode 1 The first 65 536 sectors written by the host after every spin up will be verified 02h Mode 2 It arbitrarily decides it with the device Model 1 is the same in this drive 03h Mode...

Page 196: ... Master password version number 18 to 255 Reserved Table 5 37 Relationship between combination of Identifier and Security level and operation of the lock function Identifier Level Description User High The specified password is set as a new user password The lock function is enabled after the device is turned off and then on LOCKED MODE can be canceled using the user password or the master passwor...

Page 197: ...1h ER 04h 3 A SATA communication error occurred ST 51h ER 14h At command issuance Shadow Block Registers setting contents CM 1 1 1 1 0 0 0 1 DH x x x x xx CH CL SN SC FR xx xx xx xx xx At command completion Shadow Block Register contents to be read ST Status information DH x x x x xx CH CL SN SC ER xx xx xx xx Error information C141 E244 5 125 ...

Page 198: ...ed with the user password already set If the passwords are the same LOCKED MODE is canceled Otherwise the Aborted Command error is returned If the password comparison fails the device decrements the UNLOCK counter The UNLOCK counter initially has a value of five When the value of the UNLOCK counter reaches zero this command or the SECURITY ERASE UNIT command causes the Aborted Command error until ...

Page 199: ...5 3 Host Commands At command completion Shadow Block Register contents to be read ST Status information DH x x x x xx CH CL SN SC ER xx xx xx xx Error information C141 E244 5 127 ...

Page 200: ...rily by the SECURITY ERASE UNIT command Error reporting conditions 1 The device is in Security Frozen mode ST 51h ER 04h 2 A SATA communication error occurred ST 51h ER 14h At command issuance Shadow Block Registers setting contents 1 1 1 1 0 0 1 1 DH x x x x xx CH CL SN SC FR xx xx xx xx xx CM At command completion Shadow Block Registers contents to be read ST Status information DH x x x x xx CH ...

Page 201: ... password or master password already set The device erases user data invalidates the user password and releases the lock function if the passwords are the same To recover the master password issue the SECURITY SET PASSWORD command and reset the user password Error reporting conditions 2 The Security Erase Prepare command did not complete normally beforehand ST 51h ER 04h 3 The device is in Securit...

Page 202: ...E is canceled when the power is turned off If this command is reissued in FROZEN MODE the command is completed and FROZEN MODE remains unchanged The following medium access commands return the Aborted Command error when the device is in LOCKED MODE READ DMA EXT READ MULTIPLE EXT READ SECTORS EXT READ VERIFY SECTORS EXT WRITE DMA EXT WRITE SECTORS EXT WRITE MULTIPLE EXT WRITE VERIFY SECURITY DISABL...

Page 203: ...MA QUEUED Error reporting conditions 2 A SATA communication error occurred ST 51h ER 14h At command issuance Shadow Block Registers setting contents CM 1 1 1 1 0 1 0 1 DH x x x x xx CH CL SN SC FR xx xx xx xx xx At command completion Shadow Block Registers contents to be read information x x x x xx CH CL SN SC ER xx xx xx xx Error information ST Status DH C141 E244 5 131 ...

Page 204: ...aster password is retained To recover the master password issue the SECURITY SET PASSWORD command and reset the user password If the user password or master password transferred from the host does not match the Aborted Command error is returned Issuing this command while in LOCKED MODE or FROZEN MODE returns the Aborted Command error The section about the SECURITY FREEZE LOCK command describes LOC...

Page 205: ...Security Locked mode ST 51h ER 04h 4 A SATA communication error occurred ST 51h ER 14h At command issuance Shadow Block Registers setting contents CM 1 1 1 1 0 1 1 0 DH x x x x xx CH CL SN SC FR xx xx xx xx xx At command completion Shadow Block Registers contents to be read ST Status information DH x x x x xx CH CL SN SC ER xx xx xx xx Error information C141 E244 5 133 ...

Page 206: ...hen reports the status to the host system Error reporting conditions 1 A SATA communication error occurred ST 51h ER 14h At command issuance Shadow Block Registers setting contents CM 1 1 1 1 0 0 1 0 DH x L x x xx CH CL SN SC FR xx xx xx xx xx At command completion Shadow Block Registers contents to be read ST Status information DH x x x x Max head LBA MSB CH CL SN SC ER CYL No MSB LBA CYL No LSB ...

Page 207: ... command is held even after power on When the VV bit is 0 the value set by this command becomes invalid when the power is turned on and the maximum address returns to the value most lately set when VV bit 1 When the command with VV 1 has not issued before the maximum address returns to the default value When the READ NATIVE MAX ADDRESS command has been issued immediately preceding this command thi...

Page 208: ...ck Registers setting contents CM 1 1 1 1 1 0 0 1 DH x L x x HD No LBA CH CL SN CYL No MSB LBA CYL No LSB LBA SCT No LBA LSB SC xx VV FR xx At command completion Shadow Block Registers contents to be read ST Status information DH x x x x xx SN SC CYL No MSB LBA CYL No LSB LBA xx Error information CH CL ER SCT No LBA LSB SET MAX SET PASSWORD Features Field 01h This command requests a transfer of 1 s...

Page 209: ...ER 14h At command issuance Shadow Block Registers setting contents CM 1 1 1 1 1 0 0 1 DH x x x x xx CL SN SC FR xx xx xx xx 01 CH At command completion Shadow Block Registers contents to be read ST Status information DH CH CL SN SC ER xx xx xx xx xx Error information Password information Words Contents 0 Reserved 1 to 16 Password 32 bytes 17 to 255 Reserved C141 E244 5 137 ...

Page 210: ...il a power cycle or the acceptance of SET MAX UNLOCK or SET MAX FREEZE LOCK command Error reporting conditions 1 The device is in Set Max Locked mode or Set Max Freeze Locked mode ST 51h ER 04h 2 A SATA communication error occurred ST 51h ER 14h At command issuance Shadow Block Registers setting contents CM 1 1 1 1 1 0 0 1 DH x x x x xx CH CL SN SC FR xx xx xx xx 02 At command completion Shadow Bl...

Page 211: ...er reaches zero then SET MAX UNLOCK command returns command aborted until a power cycle If the password compare matches then the device makes a transition to the Set Max Unlocked state and all SET MAX commands will be accepted Error reporting conditions 1 The device is in Set Max Locked mode or Set Max Freeze Locked mode ST 51h ER 04h 2 The device is in Set Max Unlocked mode ST 51h ER 04h 3 A SATA...

Page 212: ...SET PASSWORD SET MAX LOCK SET MAX UNLOCK SET MAX FREEZE LOCK Error reporting conditions 1 The device is in Set Max Locked mode or Set Max Freeze Locked mode ST 51h ER 04h 2 A SATA communication error occurred ST 51h ER 14h At command issuance Shadow Block Registers setting contents CM 1 1 1 1 1 0 0 1 DH x x x x xx CH CL SN SC xx FR xx xx xx 04 At command completion Shadow Block Registers contents ...

Page 213: ...was issued in CHS mode ST 51h ER 04h The other error reporting conditions are the same as those of the READ SECTOR S command At command issuance Shadow Block Registers setting contents 0 0 0 0 0 DH 1 L 1 x xx CH EXP CH CL EXP SN FR EXP LBA 23 16 LBA 31 24 CL SN EXP SC EXP SC FR LBA 47 40 LBA 39 32 LBA 15 8 LBA 7 0 Sector count 15 8 Sector count 7 0 xx xx CM 1 0 1 At command completion Shadow Block...

Page 214: ...d in CHS mode ST 51h ER 04h The other error reporting conditions are the same as those of the READ DAM command At command issuance Shadow Block Registers setting contents CM 0 0 1 0 0 1 0 1 DH 1 L 1 x xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC FR EXP FR LBA 47 40 LBA 23 16 LBA 39 32 LBA 15 8 LBA 31 24 LBA 7 0 Sector count 15 8 Sector count 7 0 xx xx At command completion Shadow Block Registers con...

Page 215: ...SATA communication error occurred ST 51h ER 14h At command issuance Shadow Block Registers setting contents CM 0 0 1 0 0 1 1 1 DH 1 L 1 x xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC FR EXP FR xx xx xx xx xx xx xx xx xx xx At command completion Shadow Block Registers contents to be read ST Status information DH 1 L 1 x xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC ER Native max address LBA 47 40 Native...

Page 216: ...issued in CHS mode ST 51h ER 04h The other error reporting conditions are the same as those of the READ MULTIPLE command At command issuance Shadow Block Registers setting contents 0 0 1 1 0 1 1 L 1 x xx CH EXP CH Sector count 15 8 Sector count 7 0 xx CL EXP CL SN EXP SN SC EXP SC FR EXP FR LBA 47 40 LBA 23 16 LBA 39 32 LBA 15 8 LBA 31 24 LBA 7 0 xx CM 0 0 DH At command completion Shadow Block Reg...

Page 217: ...pecified sector The number of sectors to be transferred is specified as the Sector count The events of the PHY level on an interface are collected and it registers with Read Log Extend page 11h This Read Log Ext log page can be read by specifying Sector offset 00h Sector count 01h and Log address 11h For the data format of Read Log Ext log page 11h see Table 5 41 If this command is not supported o...

Page 218: ...EXP SN Sector count 15 8 Sector count 7 0 SC EXP SC FR EXP FR xx xx Sector offset 15 8 Sector offset 7 0 xx Log address xx xx At command completion Shadow Block Registers contents to be read information x x x xx CH EXP CH CL EXP SN ER xx xx xx Error information CL SN EXP SC EXP SC xx xx xx xx xx ST Status DH x 5 146 C141 E244 ...

Page 219: ...alue Sector Number Exp field value 09 Cylinder Low Exp field value 0A Cylinder High Exp field value 0B Reserved 0D Sector Count Exp field value Reserved Vendor Unique 1FF 00 Tag 08 0C Sector Count field value 0E to FF 100 to 1FE Check sum Table 5 40 Tag field information Bit Description 0 4 If bit 7 is 0 this field has an error tag number 6 7 5 Reserved If this bit is 0 the field consisting of bit...

Page 220: ...ommand failed due to an ICRC error 2 Data FIS R_ERR ending status transmitted Data FIS R_ERR ending status received 5 Non data FIS R_ERR ending status transmitted and received 6 Non data FIS R_ERR ending status transmitted 8 Non data FIS retries transmitted 9 Transitions from drive PhyRdy to drive PhyNRdy A Signature Device to Host Register FIS sent due to a COMRESET B CRC errors within the FIS re...

Page 221: ...tting CM 0 0 1 0 1 1 1 1 DH 1 L 1 DV xx CH EXP CH CL EXP SC 00h 01h CL SN EXP SN SC EXP FR EXP FR xx xx 00h xx E0h 00h xx xx At command completion Shadow Block Registers contents to be read ST Status information DH x x x DV xx CH EXP CH CL EXP CL SC xx SN EXP SN SC EXP ER xx xx xx xx xx xx xx Error information C141 E244 5 149 ...

Page 222: ...ing CM 0 0 1 0 1 1 1 1 DH 1 L 1 DV xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC FR EXP FR xx xx 00h 00h xx E1h xx xx xx xx At command completion Shadow Block Registers contents to be read ST Status information DH x x x DV xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC ER xx xx xx xx xx xx xx xx Error information 5 150 C141 E244 ...

Page 223: ... was issued in CHS mode ST 51h ER 04h The other error reporting conditions are the same as those of the WRITE SECTOR S command At command issuance Shadow Block Registers setting contents CM 0 0 1 1 0 1 0 0 DH 1 L 1 x xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC FR EXP FR LBA 47 40 LBA 23 16 LBA 39 32 LBA 15 8 LBA 31 24 LBA 7 0 Sector count 15 8 Sector count 7 0 xx xx At command completion Shadow Blo...

Page 224: ...ed in CHS mode ST 51h ER 04h The other error reporting conditions are the same as those of the WRITE DMA command At command issuance Shadow Block Registers setting contents CM 0 0 1 1 0 1 0 1 DH 1 L 1 x xx CH EXP CH CL EXP CL Sector count 7 0 SN EXP SN SC EXP SC FR EXP FR LBA 15 8 LBA 47 40 LBA 23 16 LBA 39 32 LBA 31 24 LBA 7 0 Sector count 15 8 xx xx At command completion Shadow Block Registers c...

Page 225: ...e command with VV 1 has not issued before the maximum address returns to the default value After power on the host can issue this command only once when VV bit 1 If this command with VV bit 1 is issued twice or more any command following the first time will result in an ID Not Found error When the SET MAX ADDRESS EXT command is executed SET MAX ADDRESS command is aborted The address value returns ...

Page 226: ...MAX LBA 39 32 SET MAX LBA 15 8 SET MAX LBA 31 24 SET MAX LBA 7 0 xx SC xx VV FR EXP FR xx xx At command completion Shadow Block Registers contents to be read ST Status information DH 1 L 1 x xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC ER SET MAX LBA 47 40 SET MAX LBA 23 16 SET MAX LBA 39 32 SET MAX LBA 15 8 SET MAX LBA 31 24 SET MAX LBA 7 0 xx xx Error information 5 154 C141 E244 ...

Page 227: ... was issued in CHS mode ST 51h ER 04h The other error reporting conditions are the same as those of the WRITE MULTIPLE command At command issuance Shadow Block Registers setting contents CM 0 0 1 1 1 0 0 1 DH 1 L 1 x xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC FR EXP FR LBA 47 40 LBA 23 16 LBA 39 32 LBA 15 8 LBA 31 24 LBA 7 0 Sector count 15 8 Sector count 7 0 xx xx At command completion Shadow Blo...

Page 228: ... the Aborted Command error occurs Error reporting conditions 1 An error was detected during power on processing ST 51h ER 04h 2 An error was detected during wake up processing in cases where wake up processing is required before execution of this command ST 51h ER 04h 3 A write fault was detected while the write cache was disabled ST 71h ER 10h 4 While the write cache is enabled if the status indi...

Page 229: ... SN EXP SN SC EXP SC FR EXP FR xx xx Sector offset 15 8 Sector offset 7 0 xx Log address Sector count 15 8 Sector count 7 0 xx xx At command completion Shadow Block Registers contents to be read ST Status information DH x x x x xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC ER xx xx xx xx xx xx xx xx Error information C141 E244 5 157 ...

Page 230: ... CM 0 0 1 1 1 1 1 1 DH 1 L 1 DV xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC FR EXP FR xx xx 00h 00h xx E0h 00h 01h xx xx At command completion Shadow Block Registers contents to be read ST Status information DH x x x DV xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC ER xx xx xx xx xx xx xx xx Error information 5 158 C141 E244 ...

Page 231: ...ting CM 0 0 1 1 0 0 0 0 DH 1 L 1 DV xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC FR EXP FR xx xx 00h 00h xx E1h xx xx xx xx At command completion Shadow Block Registers contents to be read information DH x x x DV xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC ER xx xx xx xx xx xx xx xx Error information ST Status C141 E244 5 159 ...

Page 232: ...nd was issued in CHS mode ST 51h ER 04h The other error reporting conditions are the same as those of the READ VERIFY SECTOR S command At command issuance Shadow Block Registers setting contents CM 0 1 0 0 0 0 1 0 DH 1 L 1 x xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC FR EXP FR LBA 47 40 LBA 23 16 LBA 39 32 LBA 15 8 LBA 31 24 LBA 7 0 Sector count 15 8 Sector count 7 0 xx xx At command completion Sh...

Page 233: ...ommunication error occurred ST 51h ER 14h At command issuance Shadow Block Registers setting contents CM 1 1 1 0 1 0 1 0 DH 1 L 1 x xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC FR EXP FR xx xx xx xx xx xx xx xx xx xx At command completion Shadow Block Registers contents to be read ST Status information DH 1 L 1 x xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC ER xx xx xx xx xx xx xx xx Error information...

Page 234: ...the WRITE MULTIPLE EXT command At command issuance Shadow Block Registers setting contents CM 1 1 0 0 1 1 1 0 DH 1 L 1 x xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC FR EXP FR LBA 47 40 LBA 23 16 LBA 39 32 LBA 15 8 LBA 31 24 LBA 7 0 Sector count 15 8 Sector count 7 0 xx xx At command completion Shadow Block Registers contents to be read ST Status information DH 1 L 1 x xx CH EXP CH CL EXP CL SN EXP ...

Page 235: ... the WRITE DMA EXT command At command issuance Shadow Block Registers setting contents CM 0 0 1 1 1 1 0 1 DH 1 L 1 x xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC FR EXP FR LBA 47 40 LBA 23 16 LBA 39 32 LBA 15 8 LBA 31 24 LBA 7 0 Sector count 15 8 Sector count 7 0 xx xx At command completion Shadow Block Registers contents to be read ST Status information DH 1 L 1 x xx CH EXP CH CL EXP CL SN EXP SN S...

Page 236: ... LBA 47 40 LBA 23 16 LBA 39 32 LBA 15 8 LBA 31 24 LBA 7 0 xx SC TAG xx FR EXP FR xx xx At command completion Shadow Block Registers contents to be read ST Status information DH 1 L 1 x xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC ER xx xx xx xx xx xx xx xx Error information FUA If this bit is 1 the device always reads data from media regardless of whether the data requested by the host is in the cac...

Page 237: ... EXP CL SN EXP SN SC EXP LBA 47 40 LBA 23 16 LBA 39 32 LBA 15 8 LBA 31 24 LBA 7 0 xx SC TAG xx FR EXP FR xx xx At command completion Shadow Block Registers contents to be read ST Status information DH 1 L 1 x xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC ER xx xx xx xx xx xx xx xx Error information FUA If this bit is 1 the device always reports the status after data is written to a medium TAG Number ...

Page 238: ...ITIALIZE DEVICE PARAMETERS V V V V V DOWNLOAD MICROCODE V V V V V STANDBY IMMEDIATE V V V V V IDLE UNLOAD IMMEDIATE V V V V V STANDBY V V V V V IDLE V V V V V CHECK POWER MODE V V V V V SLEEP V V V V V SMART V V V V V V V DEVICE CONFIGURATION V V V V V V READ MULTIPLE V V V V V V V WRITE MULTIPLE V V V V V V SET MULTIPLE MODE V V V V V READ DMA V V V V V V V V V V V V V V V V V FLUSH CACHE V V V V...

Page 239: ...V V V READ MULTIPLE EXT V V V V V V V WRITE LOG EXT V V V V V V V V V V V V V V V V V SET MAX ADDRESS EXT V V V V V V V V V V V READ LOG EXT V V V V V V V V V V V FLUSH CACHE EXT V V V V V V V V V V V WRITE DMA FUA EXT V V V V V V READ FP DMA QUEUED V V V V V V V WRITE FP DMA QUEUED V V V V V V READ NATIVE MAX ADDRESS V READ DMA EXT V WRITE SECTOR S EXT WRITE DMA EXT V WRITE MULTIPLE EXT V V V V R...

Page 240: ...is section FIS Frame Information Structure type Abbreviation Register Host to Device RegHD Register Device to Host RegDH DMA Active Device to Host DMA Active DMA Setup Device to Host or Host to Device Bidirectional DMA Setup Set Device Bits Device to Host SetDB BIST Active Bidirectional BIST Active PIO Setup Device to Host PIO Setup Data Host to Device or Device to Host Bidirectional DATA 5 4 1 No...

Page 241: ... FREEZE LOCK FLUSH CACHE EXT SLEEP DEVICE CONFIGRATION RESTORE FREEZE LOCK The following is the protocol for command execution without data transfer 1 The device receives a non data command with the RegHD FIS 2 The device executes the received command 3 Command execution is completed 4 The device reports the completion of command execution by sending to the host the RegDH FIS with 1 set in the I b...

Page 242: ...cution the device sends the RegDH FIS with 1 set in the I bit 3 When the device is ready to send data it sets 0 in the BSY bit 1 in the DRQ bit and 1 in the I bit of the Status field of the PIO Setup FIS then sends this FIS to the host At this time if the requested data is read from the last sector to be processed the device sets 0 in both the BSY bit and DRQ bit of the E_Status field Otherwise th...

Page 243: ...ves data transfers from the host system to the device WRITE SECTOR S EXT WRITE MULTI EXT FUA EXT WRITE BUFFER WRITE VERIFY SMART WRITE LOG SECTOR SECURITY DISABLE PASSWORD SECURITY ERASE UNIT SECURITY SET PASSWORD SECURITY UNLOCK DOWNLOAD MICROCODE DEVICE CONFIGRATION SET WRITE LOG EXT Data of one or more sectors is transferred from the host to the device C141 E244 5 171 ...

Page 244: ... to the first sector while it sets 1 in the I bit for a data transfer to any sector other than the first sector Then it sends this FIS to the host In the E_Status field the device sets 1 in the BSY bit and 0 in the DRQ bit 4 The device receives the DATA FIS from the host 5 When all data has been transferred the device sends the RegDH FIS with 1 set in the I bit to complete execution of the command...

Page 245: ...A data in command with the RegHD FIS 2 If an error remaining in the device prevents command execution the device sends the RegDH FIS with 1 set in the I bit 3 When the device is ready to send data it sends the Data FIS to the host 4 When all data has been transferred the device sends the RegDH FIS with 1 set in the I bit to complete execution of the command If any data remains to be sent by the de...

Page 246: ...maining in the device prevents command execution the device sends the RegDH FIS with 1 set in the I bit 3 When the device is ready to receive data it sends the DMA Active FIS to the host 4 The device receives the Data FIS from the host 5 When all data has been transferred the device sends the RegDH FIS with 1 set in the I bit to complete execution of the command If any data remains to be received ...

Page 247: ...r of the READ FP DMA QUEUED command it sends to the host the DMA Setup FIS with the settings of TAG D bit 1 I bit 0 and A bit 0 and it then sends the Data FIS to the host The Data FIS is transferred in units of up to 8 KB 5 For the data transfer of the WRITE FP DMA QUEUED command if the DMA Setup Auto Activate function is disabled the device sends to the host the DMA Setup FIS with the settings of...

Page 248: ... The device reports abort for other commands 10 If the device receives the READ LOG EXT command with page 10h specified queued commands are aborted Then after the device sends to the host the SetDB FIS ERR 0 ERRReg 0 I 0 and SActive 0xFFFFFFFF it sends to the host the log data for the READ LOG EXT command with page 10h specified and reports the status of this command Next the command queuing funct...

Page 249: ...5 4 Command Protocol Device Host RegHD RegDH DMA Setup SetDB DATA DMACT Figure 5 19 WRITE FP DMA QUEUED command protocol C141 E244 5 177 ...

Page 250: ...stablished the host sets 0xFFh in the Status field of the Shadow Block Register The device completes the power on sequence within 10 ms so that communication with the SATA interface can be established Device TX Host RX Host TX Device RX Host power on Host ComReset Host releases ComReset Host calibrate Host ComWake Host releases ComWake Host Align Host data Device ComInit Device releases ComInit De...

Page 251: ...Host device on Host ComReset Host releases ComReset Host calibrate Host ComWake Host releases ComWake Host Align Host data Device ComInit Device releases ComInit Device Calibrate Device ComWake Device Align Device data Figure 5 21 COMRESET sequence C141 E244 5 179 ...

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Page 253: ...Operations 6 1 Reset and Diagnosis 6 2 Power Save 6 3 Power Save Controlled by Interface Power Management IPM 6 4 Read ahead Cache 6 5 Write Cache This chapter explains each of the above operations C141 E244 6 1 ...

Page 254: ...ication with the SATA interface is established the host sets 0xFFh in the Status field of the Shadow Block The device establishes communication with the SATA interface PHY Ready within 10 ms The device sends the FIS STS 50h to notify the host that the device is ready Note Figure 6 1 assumes that power is turned on after the power off state continued for more than five seconds Figure 6 1 Response t...

Page 255: ...6 1 Reset and Diagnosis Figure 6 2 Response to power on when the device is powered on earlier than the host C141 E244 6 3 ...

Page 256: ...e when power is turned on and a power on reset is then cancelled The device establishes communication with the SATA interface PHY Ready and sends the RegDH FIS STS 50h to notify the host that the device is ready Then the COMRESET sequence is completed Figure 6 3 Response to COMRESET 6 4 C141 E244 ...

Page 257: ... refer to Section 5 3 2 28 If a device supports software settings preservation the feature shall be enabled by default 6 1 2 2 COMRESET preservation requirements The software settings that shall be preserved across COMRESET are listed below The device is only required to preserve the indicated software setting if it supports the particular feature command the setting is associated with INITIALIZE ...

Page 258: ...h SET FEATURES Advanced Power Management Enable Disable The advanced power management enable disable setting established by the SET FEATURES command with subcommand code of 05h or 85h The advanced power management level established in the Sector Count field when advanced power management is enabled SET FEATURES subcommand code 05h shall also be preserved SET FEATURES Read Look Ahead The read look ...

Page 259: ...reset When a software reset is accepted the device performs a self diagnosis and it sends the RegDH FIS STS 50h to notify the host that the device is ready Then the software reset sequence is completed Figure 6 4 Response to a software reset C141 E244 6 7 ...

Page 260: ...mode all the electric circuit in the device are active or the device is under seek read or write operation A device enters the active mode under the following conditions The media access system is received 2 Active idle mode In this mode circuits on the device is set to power save mode The device enters the Active idle mode under the following conditions After completion of the command execution o...

Page 261: ... the low power idle state APM Mode 2 The time specified by the STANDBY or IDLE command has elapsed after completion of the command A reset is issued in the sleep mode When one of following commands is issued the command is executed normally and the device is still stayed in the standby mode Reset hardware or software STANDBY command STANDBY IMMEDIATE command INITIALIZE DEVICE PARAMETERS command CH...

Page 262: ...Operations 6 2 2 Power commands The following commands are available as power commands IDLE IDLE IMMEDIATE STANDBY STANDBY IMMEDIATE SLEEP CHECK POWER MODE SET FEATURES APM setting 6 10 C141 E244 ...

Page 263: ...ich the device must switch to Active mode from the Interface Power Down state Period in which the device must switch to Active mode Partial mode Maximum 10 µs Slumber mode Maximum 10 ms 1 Active mode The interface is in the Active state and commands can be accepted 2 Partial mode In this mode shallow Power Save mode is set for the interface circuit The device switches to Partial mode when the foll...

Page 264: ...h the PMACK signal The device sends the PMREQ_S signal and the host responds with PMACK signal The device cannot switch to Slumber mode if the following condition is satisfied The device responds with the PMNAK signal because it is not waiting for commands The device returns to Active mode from Slumber mode when the following condition is satisfied The device receives the COMRESET or ComWake signa...

Page 265: ...fer can be transferred without accessing the disk media As the result faster data access becomes possible for the host 6 4 1 Data buffer structure This device contains a data buffer This buffer is divided into two areas one area is used for MPU work and the other is used as a read cache for another command See Figure 6 5 8 MB buffer Figure 6 5 Data buffer structure The read ahead operation is done...

Page 266: ...nction is prohibited by the SET FEATURES command the caching operation is not performed 2 Data that is a target of caching The data that is a target of caching are as follows 1 Read ahead data that is read from disk media and saved to the data buffer upon completion of execution of a command that is a target of caching 2 Pre read data that is read from disk media and saved to the data buffer befor...

Page 267: ...RES SECURITY ERASE UNIT DEVICE CONFIGURATION DOWNLOAD MICROCODE UNSUPPORT COMMAND INVALID COMMAND 1 2Commands that partially invalidate caching data READ DMA READ MULTIPLE READ SECTOR S READ DMA EXT READ MULTIPLE EXT READ SECTOR S EXT READ FP DMA QUEUED WRITE DMA WRITE MULTIPLE WRITE SECTOR S WRITE DMA EXT WRITE MULTIPLE EXT WRITE SECTOR S EXT WRITE DMA FUA EXT WRITE MULTIPLE FUA EXT WRITE FP DMA ...

Page 268: ...e requested data reading position Read segment HAP host address pointer DAP disk address pointer 2 During reading of read requested data the request data that has already been read is sent to the host system Read requested data Free space HAP DAP Read requested data is stored until this point 3 When reading of read requested data is completed and transfer of the read requested data to the host sys...

Page 269: ... data the request data that has already been read is sent to the host system Cache valid data Free space Read requested data DAP disk address pointer HAP host address pointer 3 When reading of read requested data is completed and transfer of the read requested data to the host system is completed the read ahead operation continues until a certain amount of data is stored Read ahead data Cache vali...

Page 270: ... ahead operation is in progress 1 An example is the state shown below where the previous read command is executing sequential reading First HAP is set at the location where hit data is stored HAP It is reset to the hit data location for transfers HAP end location of the previous read command DAP end location of the previous read command Cache data Full hit data Cache data HAP DAP 2 The read reques...

Page 271: ...T LBA LAST LBA 1 HAP is set at the address where partial hit data is stored and Transfer is started Cache valid data Partial hit data HAP host address pointer 2 DAP and HAP are set at the head of Buffer newly allocated and insufficient data is read Read segment HAP host address pointer DAP disk address pointer 3 When reading the read requested data ends and the transmission of the read requested d...

Page 272: ...aching function is prohibited by the SET FEATURES command 2 Invalidation of cached data If an error occurs during writing onto media write processing is repeated up to as many times as specified for retry processing If retry fails for a sector because the retry limit is reached automatic alternate sector processing is executed for the sector If the automatic alternate sector processing fails the d...

Page 273: ...re reset is received while cached data is stored on the data buffer data of the data buffer is written on the media and reset processing is then performed This is true for both a hard reset and soft reset 6 Cashing function when power supply is turned on The cashing function is invalid until Calibration is done after the power supply is turned on about 10 sec It is effective in Default after that ...

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Page 275: ...ers The BIOS of a PC AT cannot make full use of the physical specifications of these drivers To make the best use of these drives a BIOS that can handle the standard parameters of these drives is required Command Commands are instructions to input data to and output data from a drive Commands are written in command field Connector Connector Plug Host system side It means a host receptacle describe...

Page 276: ...ower on time by the number of failures in the disk drive during operation MTTR Mean time to repair The MTTR is the average time required for a service person to diagnose and repair a faulty drive PIO Programmed input output Mode to transfer data under control of the host CPU Positioning Sum of the seek time and mean rotational delay Power save mode The power save modes are idle mode standby mode a...

Page 277: ...ATA physical storage interface The parallel data transfer of Parallel ATA is changed to the serial data transfer in Serial ATA for obtaining greater data transfer speed Slave Device 1 The slave is a second drive that can operate on the AT bus The slave is daisy chained with the first drive operating in conformity with the ATA standard Status The status is a piece of one byte information posted fro...

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Page 279: ...t E ECC Error checking and correction ER Error field ERR Error EU European Union F FR Feature field H HA Host adapter HDD Hard disk drive I IDNF ID not found IRQ14 Interrupt request 14 L LED Light emitting diode M MB Mega byte MB S Mega byte per seconds MPU Micro processor unit P PCA Printed circuit assembly PIO Programmed input output R RLL Run length limited RoHS The Restrictions of the use of c...

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Page 281: ...r 5 29 area service 3 6 command data structure 5 67 attribute ID 5 61 command description 5 32 attribute value command execution status after 5 24 current 5 62 command field 5 28 raw 5 62 command for caching 6 14 6 20 worst case 5 62 command processing during self calibration 4 8 automatic acoustic management 5 122 average positioning time 1 2 command protocol 5 168 DMA data in 5 173 B DMA data ou...

Page 282: ...ew 2 2 D disk enclosure 2 3 DMA active device to host 5 18 D A converter DAC 4 13 DMA buffer offset field 5 28 data host to device or device to host bidirectional 5 21 DMA data in command protocol 5 173 DMA data out command protocol 5 174 data area 4 15 DMA setup device to host or host to device bidirectional 5 19 data assurance in the event of power failure 1 11 DMA transfer count field 5 28 data...

Page 283: ...61 C3h 5 87 identifier and security level relationship between 5 124 features field value 5 118 filter IDENTIFY DEVICE 5 104 circulation 2 3 IDENTIFY DEVICE command information to be read by 5 106 FIR circuit 4 11 FIS type 5 17 IDENTIFY DEVICE DMA 5 105 flag IDLE 5 51 failure prediction capability 5 64 IDLE IMMEDIATE 5 48 status 5 62 information to be read by IDENTIFY DEVICE command 5 106 FLUSH CA...

Page 284: ...nector 5 10 mode PIO data in command protocol 5 170 5 171 active 6 8 6 11 active idle 6 8 PIO data out command protocol 5 171 5 172 low power idle 6 8 partial 6 11 PIO setup device to host 5 21 power save 6 8 positioning error 1 12 settable 5 118 Post code MHV2200BT only 4 17 sleep 6 9 power amplifier 4 13 slumber 6 12 power command 6 10 standby 6 9 power management model and product number 1 5 in...

Page 285: ...te circuit 2 3 4 3 4 9 service area 3 6 read write circuit block diagram 4 9 service life 1 11 read write preamplifier PreAMP 4 9 servo burst capture circuit 4 13 read ahead cache 6 13 servo circuit 4 3 read ahead cache system 1 3 servo control 4 12 RECALIBRATE 5 33 servo control circuit 4 12 recommended equipment 3 7 servo frame format 4 17 recommended power off sequence 1 13 servo mark 4 17 regi...

Page 286: ...tatus off line data collection 5 62 structure data buffer 6 13 subassembly 4 2 subcommand 5 56 surface temperature measurement point 3 5 surface temperature standard value 3 5 system configuration 2 3 T tag field information 5 147 5 148 temperature ambient 3 5 test span 5 70 theory of device operation 4 1 total number of drive error 5 67 track following operation 4 18 U UNLOAD IMMEDIATE 5 48 unrec...

Page 287: ...ppearance Technical level Organization Clarity Accuracy Illustration Glossary Acronyms Abbreviations Index Comments Suggestions List any errors or suggestions for improvement Page Line Contents Please send this form to the address below We will use your comments in planning future editions Address Fujitsu Learning Media Limited 37 10 Nishikamata 7 chome Oota ku Tokyo 144 0051 JAPAN Fax 81 3 3730 3...

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Page 289: ...MHV2200BT MHV2160BT DISK DRIVES PRODUCT MANUAL C141 E244 01EN MHV2200BT MHV2160BT DISK DRIVES PRODUCT MANUAL C141 E244 01EN ...

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