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Preliminary

27(30)

Prepared

Document Number

Manfred Ortmann

Approved

Checked

Date

Revision

Storage

2008-05-23

PA 6.2

Mycable01

2.3

Hardware Variants

Up to now only PCB version PA6 without variants is available.

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Summary of Contents for MB 86276

Page 1: ...fred Ortmann Approved Checked Date Revision Storage 2008 05 23 PA 6 2 Mycable01 Receiver Info M Carstens Behrens mycable GmbH Manual MB 91F467 MB 86276 Evaluation Board Version PA 6 2 May 23 2008 http www fujitsu com emea services microelectronics ...

Page 2: ...Preliminary 2 30 Prepared Document Number Manfred Ortmann Approved Checked Date Revision Storage 2008 05 23 PA 6 2 Mycable01 ...

Page 3: ...cal information for system architects hardware and software developers who work with the MB 91F467 MB 86276 Evaluation board version PA6 for evaluation and development purpose Enclosures None Product Information The MB 91F467 MB 86276 Evaluation board is populated with the 32 bit CPU MB91F467 graphic display controller MB 86276 also called LIME Flash memory SDRAM SRAM interfaces as UART Ethernet C...

Page 4: ...2008 05 23 PA 6 2 Mycable01 Revision History Version Date Sign Description PA 6 1 2008 05 06 mo Create this document PA 6 2 2008 05 23 mo First preliminary distributed version Contact Information mycable GmbH Michael Carstens Behrens hardware and commercial Email mcb mycable de Tel 49 4321 55956 55 ...

Page 5: ...276 EVALUATION BOARD 7 2 1 System Architecture 7 2 2 Function Units 9 2 2 1 Power Supply 10 2 2 2 Reset 11 2 2 3 CPU MB91F467DA 11 2 2 4 Graphic Display Controller MB86276 LIME 14 2 2 5 Buttons 16 2 2 6 LEDs 16 2 2 7 Serial Ports 17 2 2 8 Ethernet 18 2 2 9 CAN Interfaces 19 2 2 10 Video Inputs 21 2 2 11 Video Outputs 22 2 2 12 GPIOs 25 2 3 Hardware Variants 27 2 4 Placement of Components 28 2 5 Me...

Page 6: ...dware and software developers covering System architecture description and users manual Hardware architecture Mechanical information It is the engineer s reference for evaluation system development and prototyping based on the module This document covers all available hardware versions regarding their configuration options and revision state 1 2 Putting into Operation Connect the MB 91F467 MB 8627...

Page 7: ...vision Storage 2008 05 23 PA 6 2 Mycable01 2 MB 91F467 MB 86276 Evaluation Board 2 1 System Architecture The system architecture of the MB 91F467 MB 86276 Evaluation board is shown in picture 2 1 Block diagram has to be added Pic 2 1 MB 91F467 MB 86276 Evaluation board block diagram ...

Page 8: ...pared Document Number Manfred Ortmann Approved Checked Date Revision Storage 2008 05 23 PA 6 2 Mycable01 Picture 2 2 MB 91F467 MB 86276 Evaluation Board top side Picture 2 3 MB 91F467 MB 86276 Evaluation Board bottom side ...

Page 9: ...nt Number Manfred Ortmann Approved Checked Date Revision Storage 2008 05 23 PA 6 2 Mycable01 2 2 Function Units Overview in the available interfaces 10 100 Ethernet 2x serial ports 2x CAN Power supply Video Inputs Video Outputs GPIOs ...

Page 10: ... correct polarity as shown in picture 2 5 Pic 2 5 Polarity of the power supply connector A protection against wrong polarity D109 and overcurrent F100 is implemented but a too high current can damage the power supply or can produce great heat The step down switching regulator LT3481 from Linear Technology U101 regulates from the input voltage the 5 V on the board The required voltages 3 3 V and 1 ...

Page 11: ...om Fujitsu U500 is used External 2x 1 Gbit Flash Memory U580 U581 2x 128Mx16 SDRAM U590 U591 and 512kx16 SRAM U592 are connected The mode pins of the CPU MD_2 and MD_1 are set fixed to logical 0 The logical level of mode pin MD_0 can be set with switch SW500 If the switch is open the MD_0 pin is logical 1 If the switch is closed the MD_0 pin is logical 0 MD 2 0 000 Internal ROM Vector mode Reset v...

Page 12: ...MPU ch Flash external 1024 kB 64 kB Flash Protection D bus RAM 32 kB GP RAM 32 kB Direct mapped cache 8 kB Boot ROM 4 kB RTC 1 ch Free Running Timer 8 ch ICU 8 ch OCU 8 ch Reload Timer 8 ch PPG 12 ch PFM 1 ch Sound Generator 1 ch UpDown Counter 3 ch C_CAN 3 ch 32 msg buffer LIN USART 5 ch 4 ch FIFO I2C 3 ch FR external bus 32 bit address 32 bit data 26 bit address 32 bit data External Interrupts 1...

Page 13: ...ared Document Number Manfred Ortmann Approved Checked Date Revision Storage 2008 05 23 PA 6 2 Mycable01 Following picture shows the block diagram of the CPU More details see data sheet Pic 2 7 Block diagram of CPU MB91F467DA ...

Page 14: ... the CPU The MB86276 has following features CMOS 0 18µm technology Internal and memory frequency 133MHz generated by on chip PLL Base clock for display clocks 400 9MHz generated by on chip PLL Display resolutions typically from 320x240 up to 1280x768 6 layers of overlay display windows Alpha Plane and constant alpha value for each layer Digital Video input various formats including YUV RGB Video S...

Page 15: ...6 textures Bit Blt Unit for transfers up to 4096x4096 areas Alpha Bit Blt and ROP2 functions External 32 bit SDRAM interface for up to 32MB graphic memory Parallel host interface FR SH3 SH4 V850 SparcLite etc New additional serial control interface as host interface I2C based Internal and external DMA support I2C interface and GPIO inputs outputs Supply voltage 3 3V I O 1 8V Internal BGA 256 Packa...

Page 16: ...ed the interrupt 5 P24_5 will be generated If the button SW504 which is labeled with TEST3 will be pressed the interrupt 6 P24_6 will be generated 2 2 6 LEDs Pic 2 10 LEDs The LED D104 which is labeled with RES is on if the reset is active The LED D105 which is labeled with 1 8V is on if the 1 8 V power supply is on independent of the limits The LED D106 which is labeled with 3 3V is on if the 3 3...

Page 17: ...e connector X800 with RS 232 inputs and outputs UART 1 is available at the 9 pin Sub D female connector X801 with RS 232 inputs and outputs As transceiver with enhanced electrostatic discharge ESD protection the MAX3243EIPW U800 U801 are used Following table shows the assignment of pins signals and function from the UART connector X800 Connector X801 is identical For X801 the index 0 has to be cha...

Page 18: ...and PHY large transmit and receive data FIFOs with a high speed host bus interface to accommodate high bandwidth and high latency applications The LAN9218 also supports features which reduce or eliminate packet loss Its internal 16 kByte SRAM can hold over 200 received packets If the receive FIFO gets too full the LAN9218 can automatically generate flow control packets to the remote node or assert...

Page 19: ...JADE with its implemented CAN controllers The RS pin 8 of the SN65HVD234 provides for three modes of operation high speed slope control or low power standby mode The high speed mode of operation is selected by connecting pin 8 directly to ground allowing the driver output transistors to switch on and off as fast as possible with no limitation on the rise and fall slope The rise and fall slope can ...

Page 20: ...r CAN 0 SW701 120 Ohm Termination for CAN 1 Pic 2 14 Switches for termination resistors Following table shows the assignment of pins signals and function from the CAN connector X700 Pin Signal Function 1 VCC33 3 3V switchable via R702 2 EXT_CAN0L CAN 0 Low 3 GND Ground 4 EXT_CAN1L CAN 1 Low 5 GND Ground 6 GND Ground 7 EXT_CAN0H CAN 0 High 8 EXT_CAN1H CAN 1 High 9 VCC50 5V swichable via R701 Table ...

Page 21: ...nector X500 for a colour video baseband signal CVBS and X501 FTSH 106 01 DV from Samtec for digital video inputs with ITU 656 format The analog input signals will be decoded to digital video signals with ITU 656 format from the 9 bit video input processor SAA7113H U500 from Philips Semiconductors The outputs from the SAA7113H are connected to the video capture interface 0 from the JADE The SAA7113...

Page 22: ...s PanelLink Digital technology to support displays ranging from VGA to UXGA resolutions 25 165 Mpps in a single link interface The link interface of U400 is connected to DVI I connector X400 The link interface of U401 is connected to DVI connector X401 The SiI164 transmitter has a highly flexible interface with either a 12 bit mode pixel per clock edge or 24 bit mode 1 pixel clock input for true c...

Page 23: ...n Signal Function 1 GND Ground 2 GND Ground 3 VO0_B0 Digital RGB output 0 Data blue 4 VO0_B1 Digital RGB output 1 Data blue 5 VO0_B2 Digital RGB output 2 Data blue 6 VO0_B3 Digital RGB output 3 Data blue 7 VO0_B4 Digital RGB output 4 Data blue 8 VO0_B5 Digital RGB output 5 Data blue 9 VO0_B6 Digital RGB output 6 Data blue 10 VO0_B7 Digital RGB output 7 Data blue 11 VO0_G0 Digital RGB output 0 Data...

Page 24: ...output 6 Data red 30 VO0_R7 Digital RGB output 7 Data red 31 VO0_HSYNC Video output interface horizontal sync output 32 VO0_VSYNC Video output interface vertical sync output 33 VO0_DE DE CSYNC 34 VO0_CSYNC DE CSYNC 35 VO0_GV 36 VO0_CLK_RGBD Video output interface dot clock output 37 I2C_SCL I2C interface 0 SCL 38 I2C_SDA I2C interface 0 SDA 39 GND Ground 40 GND Ground Table 2 7 Pin assignment X402...

Page 25: ...CPU are available at connected X900 FTSH 110 01 L DV K A P from Samtec Following table shows the assignment of pins signals and function from the connector X900 Pin Signal Function 1 VCC33 3 3 V 2 GPIO0 P14_0 3 GPIO1 P14_1 4 GPIO2 P16_4 5 GPIO3 P16_5 6 GPIO4 P16_6 7 GPIO5 P16_7 8 GPIO6 P27_0 9 GPIO7 P27_1 10 GPIO8 P27_2 11 GPIO9 P27_3 12 GPIO10 P27_4 13 GPIO11 P27_5 14 GPIO12 P27_6 ...

Page 26: ...repared Document Number Manfred Ortmann Approved Checked Date Revision Storage 2008 05 23 PA 6 2 Mycable01 Pin Signal Function 15 GPIO13 P27_7 16 GPIO14 P26_0 17 GPIO15 P26_1 18 GPIO16 P26_2 19 GPIO17 P26_3 20 GND Ground ...

Page 27: ...liminary 27 30 Prepared Document Number Manfred Ortmann Approved Checked Date Revision Storage 2008 05 23 PA 6 2 Mycable01 2 3 Hardware Variants Up to now only PCB version PA6 without variants is available ...

Page 28: ...Preliminary 28 30 Prepared Document Number Manfred Ortmann Approved Checked Date Revision Storage 2008 05 23 PA 6 2 Mycable01 2 4 Placement of Components ...

Page 29: ...Preliminary 29 30 Prepared Document Number Manfred Ortmann Approved Checked Date Revision Storage 2008 05 23 PA 6 2 Mycable01 ...

Page 30: ...y 30 30 Prepared Document Number Manfred Ortmann Approved Checked Date Revision Storage 2008 05 23 PA 6 2 Mycable01 2 5 Mechanical Dimensions The MB 91F467 MB 86276 Evaluation board has a size of 160 0 x 100 0 mm ...

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