Preliminary
11(30)
Prepared
Document Number
Manfred Ortmann
Approved
Checked
Date
Revision
Storage
2008-05-23
PA 6.2
Mycable01
2.2.2 Reset
The triple processor supervisor TPS3307-33DGN from Texas Instruments ( U102 ) generates
a power-on reset and monitors the 1.8 V, 3.3 V and 5.0 V power supplies.
Also if the reset button SW100 will be pressed the supervisor circuit generates a reset.
2.2.3 CPU MB91F467DA
Pic. 2-6: CPU MB91F467DA
The CPU MB91F467DA from Fujitsu ( U500 ) is used. External 2x 1 Gbit Flash Memory ( U580,
U581 ), 2x 128Mx16 SDRAM ( U590, U591 ) and 512kx16 SRAM ( U592 ) are connected.
The mode pins of the CPU MD_2 and MD_1 are set fixed to logical '0'.
The logical level of mode pin MD_0 can be set with switch SW500.
If the switch is open the MD_0 pin is logical '1'. If the switch is closed the MD_0 pin is logical
'0'.
MD[2:0] = '000' : Internal ROM Vector mode, Reset vector access: internal Flash.
This is the standard setting where the internal Flash memory of the device is available.
( see Hardware Manual MB91460 Serie Chapter 9 Reset 4.3 MD: Mode Pins )
MD[2:0] = '001' : External ROM Vector mode, Reset vector access: external.
