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Fujitsu MAW3073 SERIES, Specifications

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1-54 

C141-C011 

 

The SCSI ID bit is a single bit on the DATA BUS that corresponds to the SCSI device's unique 
SCSI address. All other DATA BUS bits shall be released by the SCSI device. The DB(P_CRCA) 
and DB(P1) are not valid during the QAS phase. During the QAS phase, DB(P_CRCA), and 
DB(P1) may be released or asserted, but shall not be actively driven false. 

 

Figure 1.27  QAS phase 

 

1.6.3 SELECTION 

phase 

 

An INIT selects a TARG (a single SCSI unit) in the SELECTION phase. 

 Note: 

 

I/O signal is false during a SELECTION phase.  (The I/O signal identifies the phase as 
SELECTION or RESELECTION). 

 
(1) 

Start sequence without ARBITRATION phase 

 

In systems with the ARBITRATION phase not implemented, the INIT starts the SELECTION 
phase in the following sequence (see Figure 1.28). 

1)  The INIT shall wait for at least Bus Clear Delay after BUS FREE phase detection. 
 
2)  Then the INIT asserts SCSI IDs of desired TARG and INIT itself on the DATA BUS. 

 

Summary of Contents for MAW3073 SERIES

Page 1: ...C141 C011 01EN MAW3073 MAW3147 MAW3300 NP NC SERIES MAX3036 MAX3073 MAX3147 NP NC SERIES DISK DRIVES SCSI PHYSICAL INTERFACE SPECIFICATIONS ...

Page 2: ...damage or other loss hereinafter High Safety Required Use including without limitation nuclear power core control airplane control air traffic control mass transport operation control life support weapon launching control You shall not use this Product without securing the sufficient safety required for the High Safety Required Use If you wish to use this Product for High Safety Required Use pleas...

Page 3: ... Use this product only after thoroughly reading and understanding especially the section Important Alert Items in this manual Keep this manual handy and keep it carefully FUJITSU makes every effort to prevent users and bystanders from being injured or from suffering damage to their property Use the product according to this manual Proceed to the Copyright Page ...

Page 4: ...f products covered by this manual comply with the following standards Standard Text No Name Enacting Organization T10 1365D Rev 10 Working Draft American National Standard Information Technology SCSI Parallel Interface 4 American National Standards Institute ANSI ...

Page 5: ...C141 C011 iii REVISION RECORD Edition Date published Revised contents 01 July 2005 Initial release Specification No C141 C011 ...

Page 6: ...This page is intentionally left blank ...

Page 7: ...uration and Contents This manual consists of the following three chapters and the terminologies and abbreviations sections Chapter 1 SCSI Bus This chapter describes the configuration physical and electrical requirements interface protocol and other operations of the Small Computer System Interface SCSI which connects the MAW3073 MAW3147 MAW3300 MAX3036 MAX3073 MAX3147 NP NC series intelligent disk...

Page 8: ...RG on the SCSI bus The IDD is called TARG in this chapter except when clear identification is required Notations A decimal value is indicated as it is in this manual A hexadecimal value is indicated in the X 17B9 or 17B9h or 17B9H notation A binary value is indicated in the notation similar to 010 The disk drive model name has a different suffix depending on its SCSI electrical characteristics cap...

Page 9: ...m Note 2 Typical model name Type model name Model name MAW3300 MAW3300NP MAW3300NC MAW3147 MAW3147NP MAW3147NC MAW3073 MAW3073NP MAW3073NC MAX3147 MAX3147NP MAX3147NC MAX3073 MAX3073NP MAX3073NC MAX3036 MAX3036NP MAX3036NC Requesting for User s Comments Please use the User s Comment Form attached to the end of this manual to identify user comments including error inaccurate and misleading informat...

Page 10: ...stallation Diagnostics and Maintenance Error Analysis Principle of Operation SCSI Physical Interface Specifications SCSI Bus SCSI Message Error Recovery SCSI Logical Interface Specifications Command Processing Data Buffer Management Command Specifications Parameter Data Formats Sense Data and Error Recovery Methods Disk Media Management ...

Page 11: ...ions 1 26 1 5 Timing Rule 1 28 1 5 1 Timing value 1 28 1 5 2 Measurement point 1 42 1 6 Bus Phases 1 47 1 6 1 BUS FREE phase 1 48 1 6 2 ARBITRATION phase 1 49 1 6 2 1 Normal ARBITRATION 1 49 1 6 2 2 QAS ARBITRATION 1 52 1 6 3 SELECTION phase 1 54 1 6 4 RESELECTION phase 1 58 1 6 5 INFORMATION TRANSFER phases 1 61 1 6 5 1 Asynchronous transfer mode 1 62 1 6 5 2 Synchronous mode 1 65 1 6 5 3 Paced t...

Page 12: ... information unit 1 113 1 9 3 2 SPI L_Q information unit 1 116 1 9 3 3 SPI data information unit 1 119 1 9 3 4 SPI data stream information unit 1 119 1 9 3 5 SPI status information unit 1 121 1 10 SCAM 1 124 1 10 1 SCAM operations 1 124 1 11 Ultra SCSI 1 129 1 11 1 Outline 1 129 1 11 2 Device connection 1 129 1 11 3 Electrical characteristics of SCSI parallel interface 1 130 1 12 Low Voltage Diffe...

Page 13: ... message X 0A T I 2 11 2 3 11 TARGET RESET message X 0C I T 2 11 2 3 12 ABORT TASK message X 0D I T 2 11 2 3 13 CLEAR TASK SET message X 0E I T 2 11 2 3 14 CONTINUE TASK message X 12 I T 2 12 2 3 15 TARGET TRANSFER DISABLE message X 13 I T 2 12 2 3 16 LOGICAL UNIT RESET message X 1C I T 2 13 2 3 17 Task attribute messages 2 13 2 3 18 IGNORE WIDE RESIDUE message X 23 T I 2 14 2 3 19 IDENTIFY messag...

Page 14: ... Ended SCSI termination circuit 2 1 18 Figure 1 14 LVD SCSI termination circuit 1 20 Figure 1 15 Circuit for mated indications 1 23 Figure 1 16 16 bit SCSI not SCA2 terminating resistor circuit 1 24 Figure 1 17 Receiver de skew parameters 1 38 Figure 1 18 Transmitter skew 1 40 Figure 1 19 Transmitter time asymmetry 1 41 Figure 1 20 Fast 5 10 Measurement Point 1 42 Figure 1 21 Fast 20 Measurement P...

Page 15: ...ith information unit transfers enabled 1 105 Figure 1 46 Phase sequences for selection with attention condition with information unit transfers enabled 1 106 Figure 1 47 SPI information unit sequence during initial connection 1 109 Figure 1 48 SPI information unit sequence during data type transfers 1 110 Figure 1 49 SPI information unit sequence during data stream type transfers 1 111 Figure 1 50...

Page 16: ...hod 1 26 Table 1 14 Bus phases and signal sources 1 27 Table 1 15 SCSI bus control timing values 1 28 Table 1 16 SCSI bus data information phase ST timing values 1 29 Table 1 17 Miscellaneous SCSI bus data information phase DT timing values 1 29 Table 1 18 SCSI bus data information phase DT timing values 1 30 Table 1 19 Receive SCSI bus data information phase DT timing values 1 31 Table 1 20 Param...

Page 17: ...ode setup request from INIT to IDD 2 21 Table 2 6 Transfer mode setup request from IDD to INIT 2 23 Table 2 7 Data bus width defined by message exchange 2 25 Table 2 8 Wide mode setting request from the INIT to the IDD 2 27 Table 2 9 Wide mode setting request from the IDD to the INIT 2 28 Table 2 10 TRANSFER PERIOD FACTOR field 2 29 Table 2 11 Valid protocol options bit combinations 2 31 Table 2 1...

Page 18: ...This page is intentionally left blank ...

Page 19: ...is required 1 1 System Configuration Up to 16 bit SCSI series models can be connected to the system via the SCSI bus Figure 1 1 gives an example of multi host system configuration Each SCSI device operates as an initiator INIT or a target TARG Only a single INIT and a single TARG selected by this INIT can operate simultaneously on the SCSI bus The system configuration allows any combination of a S...

Page 20: ... 0 The SCSI ID can be 0 to 15 Note The maximum number of SCSI devices and the maximum cable length are limited depending on the selected SCSI data transfer mode and the SCSI transceiver type Appropriate SCSI devices and cable length must be determined for each system Figure 1 1 Example of SCSI configuration ...

Page 21: ...The 27 signal lines consist of data buses 2 bytes plus two odd parity bits and 9 control signal lines The SCSI bus can be a single ended or low voltage differential LVD interface depending on the model used Their physical and electrical characteristics are detailed in Sections 1 3 and 1 4 P_CRCA 18 Figure 1 2 Interface signals ...

Page 22: ...In the SELECTION or RESELECTION phase the data bus is used to send a SCSI ID of the INIT and TARG Figure 1 3 shows the relationship between the data buses and SCSI IDs DB15 DB14 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 SCSI ID 15 SCSI ID 14 SCSI ID 9 SCSI ID 8 SCSI ID 7 SCSI ID 6 SCSI ID 5 SCSI ID 4 SCSI ID 3 SCSI ID 2 SCSI ID 1 SCSI ID 0 Data bus 16 bit SCSI Figure 1 3 DATA BUS and SCSI ID a DB15 ...

Page 23: ...ity check function and can enable or disable the parity check See Section 5 3 2 SCSI Parity of the Product Manual for setup details When valid data is sent to the data bus from the IDD the parity data is always guaranteed except for the ARBITRATION phase g P_CRCA data group transfer enabled A signal sourced by a target during DT DATA phases to control whether a data group field is a pad field pCRC...

Page 24: ... specifies the information transmission direction on the data bus It is also used to identify the SELECTION phase or RESELECTION phase This signal is always driven by the TARG see Table 1 1 6 MSG MESSAGE A signal sourced by a target to indicate the MESSAGE phase or a DT DATA phase depending on whether C D is true or false Asserted indicates MESSAGE or DT DATA see Table 1 1 Table 1 1 INFORMATION TR...

Page 25: ...n 10 RST RESET The RST signal is a Reset signal to clear all SCSI devices on the bus to the RESET condition 1 3 Physical Requirements All SCSI devices are connected to each other in a daisy chain Both ends of the interface cable are terminated with resistor Tables 1 2 and 1 3 define the SCSI bus electrical characteristics for interface signal driver receiver Table 1 2 Single Ended maximum distance...

Page 26: ...6 bit SCSI bus connector is nonshielded 68 pin consisting of two 34 pin rows with adjacent pins 1 27 mm 0 05 inch part Figure 1 4 For the interface cable connector use a nonshielded 68 contact socket consisting of two 34 contact rows points with adjacent contact points 1 27 mm 0 05 inch apart Figure 1 5 Figure 1 6 shows single ended interface connector signal assignment Figure 1 7 shows low voltag...

Page 27: ...C141 C011 1 9 M M 0 61 5 16 0 001 0 396 Figure 1 5 SCSI interface connector cable side 16 bit SCSI ...

Page 28: ... GND DBP7 47 14 GND P_CRCA 48 15 GND GND 49 16 GND GND 50 17 TERMPWR TERMPWR 51 18 TERMPWR TERMPWR 52 19 reserved reserved 53 20 GND GND 54 21 GND ATN 55 22 GND GND 56 23 GND BSY 57 24 GND ACK 58 25 GND RST 59 26 GND MSG 60 27 GND SEL 61 28 GND C D 62 29 GND REQ 63 30 GND I O 64 31 GND DB08 65 32 GND DB09 66 33 GND DB10 67 34 GND DB11 68 Terminating resistor power Figure 1 6 Single ended connector...

Page 29: ...14 P_CRCA P_CRCA 48 15 GROUND GROUND 49 16 DIFFSENS GROUND 50 17 TERMPWR TERMPWR 51 18 TERMPWR TERMPWR 52 19 RESERVED RESERVED 53 20 GROUND GROUND 54 21 ATN ATN 55 22 GROUND GROUND 56 23 BSY BSY 57 24 ACK ACK 58 25 RST RST 59 26 MSG MSG 60 27 SEL SEL 61 28 C D C D 62 29 REQ REQ 63 30 I O I O 64 31 DB 8 DB 8 65 32 DB 9 DB 9 66 33 DB 10 DB 10 67 34 DB 11 DB 11 68 Terminating resistor power Figure 1 ...

Page 30: ...ors of the IDD are 80 pin unshielded connectors each having two rows of 40 parallel pins separated 1 27 mm or 0 05 from each other see Figure 1 8 Figure 1 9 shows the pin assignment of 16 bit SCA 2 type single ended SCSI interface connector Figure 1 8 SCA 2 type 16 bit SCSI interface connector IDD side ...

Page 31: ...K GND 57 18 BSY GND 58 19 ATN GND 59 20 P_CRCA GND 60 21 DB07 GND 61 22 DB06 GND 62 23 DB05 GND 63 24 DB04 GND 64 25 DB03 GND 65 26 DB02 GND 66 27 DB01 GND 67 28 DB00 GND 68 29 DBP1 GND 69 30 DB15 GND 70 31 DB14 GND 71 32 DB13 GND 72 33 DB12 GND 73 34 5V 5V RETURN MATED2 74 35 5V 5V RETURN GND 75 36 5V CHARGE 5V RETURN GND 76 37 Reserved LED 77 38 RMT_START DLYD_START 78 39 SCSI ID0 SCSI ID1 79 40...

Page 32: ... 16 RST RST 56 17 ACK ACK 57 18 BSY BSY 58 19 ATN ATN 59 20 P_CRCA P_CRCA 60 21 DB 7 DB 7 61 22 DB 6 DB 6 62 23 DB 5 DB 5 63 24 DB 4 DB 4 64 25 DB 3 DB 3 65 26 DB 2 DB 2 66 27 DB 1 DB 1 67 28 DB 0 DB 0 68 29 DB P1 DB P1 69 30 DB 15 DB 15 70 31 DB 14 DB 14 71 32 DB 13 DB 13 72 33 DB 12 DB 12 73 34 5V 5V RETURN MATED2 74 35 5V 5V RETURN GND 75 36 5V CHARGE 5V RETURN GND 76 37 Reserved LED 77 38 RMT_...

Page 33: ... AWG stranded multiple loads allowed 0 to 12 0 05092 mm2 30 AWG solid 0 08042 mm2 28 AWG stranded multiple loads allowed 12 to 25 0 05092 mm2 30 AWG solid 0 08042 mm2 28 AWG stranded point to point only A twisted pair cable must consist of pin n and pin n 1 where n is an odd number of the interface connector Use the SCSI bus cables having the same impedance characteristics to minimize the signal r...

Page 34: ...1 16 C141 C011 a Connection to a middle point of the cable b Connection to the end of the cable Figure 1 11 Connection of interface cable ...

Page 35: ...terminator should source current to the signal line whenever its terminal voltage is below 2 5 VDC and this current should not exceed 22 4 mA for any line voltage at or above 0 5 VDC and 25 4 mA for any line voltage between 0 5 VDC and 0 2 VDC even when all other signal lines are driven at 4 0 VDC 3 The voltage on all released signal lines should be at least 2 5 VDC 4 These conditions should be me...

Page 36: ...1 C011 The IDD uses the terminator circuit satisfying conditions b above The INIT terminator circuit is also recommended to meet conditions b above P_CRCA DB Figure 1 13 Single Ended SCSI termination circuit 2 ...

Page 37: ...utput characteristic Driver Type Value Min Max Notes Passive Negation VOL 0 0 0 5 IOL 48mA VOH 2 5 5 25 Active Negation VOL 0 0 0 5 IOL 48mA VOH 2 5 3 7 Table 1 7 Input characteristic Maximum transfer mode Min Max Notes VIL VDC 0 8 VIH VDC 2 0 Fast 5 IIL mA 0 4 0 0 VI 0 5VDC IIH mA 0 0 0 1 VI 2 7VDC Minimum input hysteresis VDC 0 2 VIL VDC 0 8 VIH VDC 2 0 VI 0 5VDC Fast 10 IIL µA 20 20 VI 2 7VDC I...

Page 38: ...38 TI Open collector NAND gate Receiver SN74LS240 or SN74LS19 TI Shumitt trigger input inverter 1 4 2 Low Voltage Differential type 1 Termination circuit All signals except for GROUND and TERMPWR should be terminated at both ends of the bus Each signal should be terminated Figure 1 14 shows the termination circuit P_CRCA P_CRCA Figure 1 14 LVD SCSI termination circuit ...

Page 39: ...r LVD SCSI devices shall incorporate a LVD DIFFSENS receiver that detects the voltage level on the DIFFSENS line for purposes of informing the device of the transmission mode being used by the bus The LVD DIFFSENS receiver shall be capable of detecting SE and LVD SCSI devices Table 1 9 define the receiver input levels for each of the two modes Table 1 9 DIFFSENS receiver operating requirements VIN...

Page 40: ...through optional logic in such a manner that the MATED 1 signal is held to a ground level when the MATED 2 connection is completed The SCSI device shall sink no more than 100 mA to ground through the MATED 2 pin if optional logic is used c MATED 1 Drive Side The MATED 1 signal shall be sensed by the SCSI device When the MATED 1 connection is determined to be at a ground level the SCSI device may a...

Page 41: ...xternal SCSI device or to cut the power of SCSI device having a terminator the terminator power must be supplied to the TERMPWR line from any of SCSI devices of the bus The SCSI device such as a host adapter which always operates as the INIT should supply the power The terminating resistor power shall be supplied to the TERMPWR line through a diode to prevent a reverse current Table 1 10 lists the...

Page 42: ...on the IDD system requirements 23 24 16 bit SCSI P connector setting terminal CN2 23 24pin Supply TERMPWR to SCSI Bus Short Don t supply TERMPWR to SCSI Bus Open Figure 1 16 16 bit SCSI not SCA2 terminating resistor circuit Notes All series have no internal terminator circuit If the terminator circuit is needed you should add the external circuit on your system ...

Page 43: ...et up pin CN2 13 14 When the IDD is used as 16 bit SCSI device leave the set up pin Jumper setting 8 16 open Table 1 11 shows the guide Jumper setting is available only for MP series Table 1 11 Setting set up pin 16 bit wide 8 bit narrow mode Transfer mode Jumper setting 8 16 DB08 to DB15 and DBP1 Short Don t care 8bit narrow Open Should be terminated externally 16bit wide Should be opened Don t c...

Page 44: ...ves a signal The signal becomes false when the terminating resistor circuit is biased A particular SCSI device drives the signal false Otherwise no SCSI device drives the signal True A SCSI device drives the signal true 1 In this manual the signal is said to be false if one of the following conditions is satisfied 1 The signal is actually driven by a SCSI device to become false non OR tied type 2 ...

Page 45: ...T I I N I A A Any SCSI device can drive the signal Also two or more SCSI devices may drive the signal simultaneously I Only the INIT SCSI device drives the signal I T The INIT and TARG SCSI devices drive the signal in the interface operating sequence INIT TARG or both can drive this signal according to the interface sequence I or T The INIT or TARG SCSI device or both devices may drive the signal ...

Page 46: ...ns 6 Cable skew 1 Max 4 ns 7 Data release delay Max 400 ns 8 DIFFSENS voltage filter time Min 100 ms 9 Physical disconnection delay Min 200 µs 10 Power on to selection 2 Max 10 s 11 QAS arbitration delay Min 1000 ns 12 QAS assertion delay Max 200 ns 13 QAS release delay Max 200 ns 14 QAS non DATA phase REQ ACK peiod Min 50 ns 15 Reset delay Min 200 ns 16 Reset hold time Min 25 µs Note 1 Cable Skew...

Page 47: ...ified by the maximum transfer rate for the given range shall apply even if a slower transfer rate within the given range is negotiated Table 1 17 Miscellaneous SCSI bus data information phase DT timing values Timing values ns 7 Timing description Type Fast 10 Fast 20 Fast 40 Fast 80 Fast 160 1 Cable skew 6 Max 4 3 2 5 2 5 2 5 2 REQ ACK period Nominal 200 100 50 25 12 5 3 Residual Skew Error 8 Max ...

Page 48: ...92 46 23 11 5 5 69 10 Transmit REQ ACK period tolerance Max 0 6 0 6 0 6 0 6 0 06 11 Transmit REQ assertion period with P_CRCA transitioning Min 97 5 54 35 5 24 N A 12 Transmit REQ negation period with P_CRCA transitioning Min 97 5 54 35 5 24 N A 13 Transmit setup time 11 Min 38 4 19 2 9 6 4 8 1 48 14 Transmitter skew Max N A N A N A N A 0 75 15 Transmitter time asymmetry Max N A N A N A N A 0 25 F...

Page 49: ...4 74 9 Receive setup time 14 Min 11 6 5 8 2 9 1 45 6 33 10 Receive REQ ACK period tolerance Min 0 7 0 7 0 7 0 7 0 06 11 Receive REQ assertion period with P_CRCA transitioning Min 85 5 48 32 5 21 N A 12 Receive REQ negation period with P_CRCA transitioning Min 85 5 48 32 5 21 N A 13 Receive Skew Compensation Max N A N A N A N A 4 4 14 Receive Internal Hold Time Min N A N A N A N A 0 345 15 Receive ...

Page 50: ...lay b The SEL signal is received from another SCSI device during the ARBITRATION phase c The transition of the RST signal to true For item a above the maximum time for a SCSI device to release all SCSI bus signals is 1200 ns from the BSY and SEL signals first becoming both false If a SCSI device requires more than a bus settle delay to detect BUS FREE phase it shall release all SCSI bus signals wi...

Page 51: ...SENSE commands See SCSI 3 Primary Commands Standard 13 Reset delay The minimum time that the RST signal shall be continuously true before the SCSI device shall initiate a reset 14 Reset hold time The minimum time that the RST signal is asserted There is no maximum time 15 Reset to selection The recommended maximum time from after a reset condition until a SCSI target is able to respond with approp...

Page 52: ...he receiving SCSI device between the transition i e assertion or negation of the REQ or ACK signals and the changing of the DB 15 0 P_CRCA and or P1 signals while using synchronous data transfers 21 Receive negation period The minimum time required at a SCSI device receiving a REQ signal for the signal to be negated while using synchronous data transfers Also the minimum time required at a SCSI de...

Page 53: ...ot transitioning with pCRC protection enabled Also the minimum time that an initiator shall assert the ACK signal while using synchronous data transfers 27 Transmit hold time For ST data transfers the minimum time provided by the transmitting SCSI device between the assertion of the REQ or ACK signal and the changing of the DB 15 0 P_CRCA and or P1 signals while using synchronous data transfers Fo...

Page 54: ...P_CRCA signal while pCRC protection is enabled 34 pCRC Transmit setup time The minimum time provided by the transmitter between the transition of the P_CRCA signal and the transition of the REQ signal while pCRC protection is enabled Specified to provide the increased receive setup time subject to intersymbol interference cable skew and other distortions 35 Receive REQ assertion period with P_CRCA...

Page 55: ...connect 39 QAS arbitration delay The minimum time a SCSI device with QAS enabled see 1 6 2 2 shall wait from the detection of the MSG C D and I O signals being false to start QAS until the DATA BUS is examined to see if QAS has been won see 1 6 2 2 40 QAS assertion delay The maximum time allowed for a SCSI device to assert certain signals during QAS 41 QAS release delay The maximum time allowed fo...

Page 56: ... 45 Skew correction range The minimum skew correction capability of the receiver of a signal on the DATA BUS or DB P1 relative to the ACK or REQ signal as measured at the receiver s connector The skew correction range shall be equal to transmitter chip skew cable skew two times trace skew relative to the corresponding ACK or REQ clock signal for that transition Receiver chip skew is not included a...

Page 57: ... stream information unit Also the minimum time provided by the SCSI TARG port between the negation of the P_CRCA signal and the assertion of the REQ signal corresponding to any valid data transfer of a SPI L_Q information unit Specified to provide the increased P_CRCA receive setup time subject to intersymbol interference cable skew and other distortions 51 Receive internal hold time The minimum t...

Page 58: ...I device as seen at the receiving SCSI device connector 55 Transmitter skew The maximum difference in time allowed between the rising or falling edge of a 1010 pattern on the DATA BUS or DB P1 signal and its clocking signal on the ACK or REQ signal as measured at their zero crossing points see Fig 1 18 Figure 1 18 Transmitter skew ...

Page 59: ...ximum time on DATA BUS DB P1 ACK or REQ signal from any transition edge to the subsequent transition edge during a 1010 pattern as measured at their zero crossing points minus the data transfer period see Fig 1 19 Figure 1 19 Transmitter time asymmetry ...

Page 60: ...141 C011 1 5 2 Measurement point 1 SE Fast 5 10 The measurement point of Fast 5 10 is different from that of Fast 20 The Figure 1 20 is the Fast 5 10 measurement point Figure 1 20 Fast 5 10 Measurement Point ...

Page 61: ...C141 C011 1 43 2 SE Fast 20 Figure 1 21 is the Fast 20 measurement point Figure 1 21 Fast 20 Measurement Point ...

Page 62: ...t Notes 1 VN negated signal 2 VA asserted signal 3 tm 1 25ns minimum 4 VA or VN are required to drive the 100 mV at the leading edge of the transition Those signals shall be at least 100 mV for at least tm before and after the transition 5 Differential voltage signals in all cases 6 taf and tar shall be less than 3 ns 7 Any signal structure may occur at the receiver while in the taf or tar region ...

Page 63: ...ed signal 3 tm 1 25ns minimum 4 VA or VN are required to drive the 100 mV at the leading edge of the transition Those signals shall be at least 100 mV for at least tm before and after the transition 5 Differential voltage signals in all cases 6 taf and tar shall be less than 3 ns 7 Any signal structure may occur at the receiver while in the taf or tar region including slope reversal ...

Page 64: ...1 46 C141 C011 5 LVD Paced Transfer Fig 1 24 is the LVD Paced Transfer measurement point Figure 1 24 LVD mode DT paced transfer easurement point ...

Page 65: ...phase RESELECTION phase COMMAND phase DATA phase STATUS phase MESSAGE phase The SCSI bus can never be in more than one phase at any given time Note In the following bus phase conditions signals are false unless otherwise defined Signals on the timing charts are assumed to be positive logic or active high INFORMATION TRANSFER phase ...

Page 66: ...hin one Bus Clear Delay after BSY and SEL signals become false for Bus Settle Delay If a SCSI device requires more than Bus Settle Delay to detect the BUS FREE phase it shall release all bus signals within the following period t t Bus Clear Delay Period required for BUS FREE phase detection Bus Settle Delay The maximum time allowed for releasing the bus after both SEL and BSY becomes false is Bus ...

Page 67: ... the detailed error condition If the INIT detects a BUS FREE phase when it is not expected it should issue a REQUEST SENSE command to read the sense data 1 6 2 ARBITRATION phase 1 6 2 1 Normal ARBITRATION The ARBITRATION phase allows one SCSI device to gain control of the SCSI bus The SCSI device that gets control of the SCSI bus can start the operation as INIT or TARG This is an optional system b...

Page 68: ...SI ID then may return to step 1 The SCSI device which detects no higher SCSI ID bit on the DATA BUS can obtain the bus control then it shall assert SEL signal Any other SCSI device that is participating in the ARBITRATION phase shall release its signals within Bus Clear Delay after SEL signal becomes true then may return to step 1 5 The SCSI device which wins arbitration shall wait at least Bus Cl...

Page 69: ...C141 C011 1 51 Figure 1 26 ARBITRATION phase ...

Page 70: ...nd other SCSI devices do not it is possible for the SCSI devices that have QAS enabled to prevent SCSI devices that do not have QAS enabled from arbitrating for the bus This occurs when SCSI devices that have QAS enabled never go to a BUS FREE phase A QAS INIT may interrupt a sequence of QAS cycles to force a normal arbitration with the following procedure 1 Perform a QAS arbitration 2 On winning ...

Page 71: ...efore driving any signal 3 Following the delay in step 2 the SCSI device may arbitrate for the SCSI bus by asserting its own SCSI ID within one QAS assertion delay from detection of the MSG C D and I O signals being false If arbitration fairness is enabled the SCSI device shall not arbitrate until its fairness register is cleared 4 After waiting at least one QAS arbitration delay measured from the...

Page 72: ...e 1 27 QAS phase 1 6 3 SELECTION phase An INIT selects a TARG a single SCSI unit in the SELECTION phase Note I O signal is false during a SELECTION phase The I O signal identifies the phase as SELECTION or RESELECTION 1 Start sequence without ARBITRATION phase In systems with the ARBITRATION phase not implemented the INIT starts the SELECTION phase in the following sequence see Figure 1 28 1 The I...

Page 73: ...Selection enabled parity protection and using without using attention condition 1 The INIT sets the DATA BUS to a value that is the OR of INIT s SCSI ID bit the TARG s SCSI ID bit and the appropriate parity bit s i e DB P_CRCA and or P1 2 In the case of selection using attention condition the INIT should create an attention condition indicating that a MESSAGE OUT phase is to follow the SELECTION p...

Page 74: ...se is not a TARGET RESET message or a PPR message the TARG will change to a MESSAGE IN phase and issue a MESSAGE REJECT message then originate WDTR negotiation with the TRANSFER WIDTH EXPONENT field set to 00h 5 Timeout procedure If the INIT cannot detect the response from TARG when the Selection Timeout Delay or longer has passed after starting the SELECTION phase the timeout procedure shall be p...

Page 75: ...C141 C011 1 57 Min System Deskew Delay 2 Min System Deskew Delay 2 Min System Deskew Delay 2 Min System Deskew Delay 2 Figure 1 28 SELECTION phase ...

Page 76: ...f and INIT to the SCSI bus the SCSI device that gets the bus usage right by asserting the I O signal is recognized as a TARG 3 The TARG releases the BSY signal after waiting at least Deskew Delay 2 and the TARG shall then wait the response BSY signal from the INIT after at least Bus Settle Delay passed b Parity Protection Enabled 1 The SCSI device that won arbitration has both the BSY and SEL sign...

Page 77: ...it is enabled on the data bus the INIT shall not respond to the RESELECTION phase When TARG detects the response BSY signal from INIT the TARG asserts BSY signal and waits at least Deskew Delay 2 then the TARG releases SEL signal At this time the TARG may change the I O signal state and value on the SCSI bus The INIT shall release the BSY signal after making sure that the SEL signal becomes false ...

Page 78: ...L and I O signals true and stops sending the SCSI ID to the data bus Subsequently the INIT waits for the response from TARG for at least Selection Abort Time Deskew Delay 2 If no response is detected the INIT releases the SEL and I O signals allowing the SCSI bus to go to the BUS FREE phase If the INIT detects the response from the TARG during this period the INIT considers the SELECTION phase to ...

Page 79: ...mation transfer modes synchronous and asynchronous transfer modes They differ from each other by their REQ signal transmission and ACK signal response methods called the REQ ACK handshaking Also the 16 bit SCSI bus can transfer 16 bit wide data only in the DATA phase The 16 bit SCSI bus can transfer 16 bit wide data only in the DATA phase except alternate error detection for the asynchronous infor...

Page 80: ... each other it is called the interlock control The asynchronous transfer can be used in all types of INFORMATION TRANSFER phase such as COMMAND DATA STATUS and MESSAGE Figure 1 31 shows the timing of asynchronous transfer If the wide mode data transfer is established between the INIT and TARG the two byte data DB15 to DB0 DBP1 DBP_CRCA is transferred on the 16 bit SCSI bus Otherwise single byte da...

Page 81: ...y after sending valid information of the requested type on the data bus The information on the data bus must be maintained until the REQ signal becomes false on the INIT 3 The TARG fetches data from the data bus after the ACK signal becomes true and negates the REQ signal to report the completion of reception 4 When the REQ signal becomes false on the INIT the INIT negates the ACK signal After tha...

Page 82: ...1 64 C141 C011 Figure 1 31 Transfer in asynchronous mode Min Min System Deskew Delay Cable Skew Delay System Deskew Delay Cable Skew Delay ...

Page 83: ...ome possible times when a SCSI device could try to enable protection code checking During the first COMMAND MESSAGE or STATUS phase After a UNIT ATTENTION condition During the MESSAGE phase of a negotiation Protection code errors are handled exactly parity errors during COMMAND MESSAGE or STATUS phases But this parity error outputs will be logically OR d into the existing parity error logic There ...

Page 84: ...ulses before receiving an ACK signal response if these pulses do not exceed the limit specified by the REQ ACK Offset parameter When the difference between the REQ and ACK signal pulses has reached this limit at the TARG the TARG shall not send a REQ pulse until it receives the leading edge of the next ACK pulse The data transfer in DATA phase can complete normally only when the REQ and ACK signal...

Page 85: ... or DB 15 0 P_CRCA P1 signals valid for at least one Transmit Hold Time after the assertion of the ACK signal 6 The INIT asserts the ACK signal for a minimum of one Transmit Assertion Period 7 The INIT may then negate the ACK signal and change or release the DB 7 0 P_CRCA or DB 15 0 P_CRCA P1 signals 8 The TARG reads the value of the DB 7 0 P_CRCA or DB 15 0 P_CRCA P1 signals within one Receive Ho...

Page 86: ... Transmit Hold Time Min Transmit Assertion Period Min Receive Hold Time I O REQ ACK DB Timing rule for INIT to TARG Min Transmit Setup Time Min Transmit Hold Time Min Transmit Assertion Period Min Receive Hold Time I O REQ ACK DB Figure 1 32 ST transfer in synchronous mode ...

Page 87: ...transfer only Either 8 bit or 16 bit transfer is available 3 MSG signal is asserted MSG signal negated 4 P_CRCA P1 signals are used as Data Group Transfer enabled 5 Both edges of the REQ ACK are available in the data transmission Only trailing edge is available Data group contains three fields They are Data field Pad field pCRC field The following description is about each field transfer a Data Gr...

Page 88: ...ad field is required if the I O signal is true the target has completed the data field transfer of the current data group and REQ signal is asserted Pad field required 1 TARG waits at least one pCRC transmit hold time since the last REQ assertion to assert P_CRCA 2 TARG waits at least one transmit hold time since the last REQ assertion to assert the DB 15 0 signals to their desired pad values 3 TA...

Page 89: ...roup 5 TARG waits at least one transmit REQ negation period with P_CRCA transitioning since the last REQ negation 6 TARG asserts the REQ signal and holds the DB 15 0 signals valid for a minimum of one transmit hold time and the REQ signal asserted for a minimum of a transmit assertion period 7 TARG drives the DB 15 0 signals to their desired pCRC values and waits at least one transmit setup time 8...

Page 90: ...d field data and pCRC field data are transferred using the same negotiated values as the data field data The TARG may continue to send REQs up to the negotiated offset for the next data group The TARG shall not transition REQ with P_CRCA asserted until the initiator has responded with all ACK transitions for the previous data group When the INIT detects an assertion of the P_CRCA signal and the RE...

Page 91: ...s ended a data group As a result of a data group always being an even number of transfers the REQ and ACK signals are negated both before and after the transmission of the data group The TARG fetches the value of the DB 15 0 signals within one receive hold time of the transition of the ACK signal The INIT uses the pad bytes if any in the generation of the transmitted pCRC The TARG then uses those ...

Page 92: ...CA transitioning transmit hold pCRC transmit hold transmit setup pCRC transmit setup pCRC transmit hold pCRC value pCRC value data value 100 mV 100 mV 0 V 100 mV 100 mV Pad field required Pad field no required P_CRCA DB15 0 REQ 100 mV 100 mV 100 mV 100 mV 100 mV 100 mV 0 V 0 V pCRC receive hold pCRC receive setup receive setup receive hold ACK 100 mV 100 mV 0 V Figure 1 33 Data Group Pad field and...

Page 93: ...the data invalid state prior to the next assertion of REQ and will not change P1 to enable a data valid state until after the next ACK assertion is received For successful completion of a paced DT DATA IN phase the number of data valid state REQ assertions and ACK assertions shall be equal Each assertion indicates a single 32 bit data transfer For paced DT DATA OUT phases the REQ ACK offset specif...

Page 94: ...system deskew delays 2 asserting the SEL signal a minimum of two system deskew delays and 3 then asserting the REQ signal The TARG begins the section A of its training sequence by transmitting the following training pattern Start of section A 1 if precompensation is enabled then set the drivers to the strong driver state 2 simultaneously assert REQ P1 P_CRCA and DB 15 0 signals 3 wait the equivale...

Page 95: ...he start of the TARGs training pattern if it detects the SEL MSG and I O true and C D false on the first assertion of the REQ signal The INIT shall transmit the following training pattern 1 assert ACK signal within 200 ns of the first REQ assertion 2 if precompensation is enabled then set the drivers to the strong driver state 3 wait the equivalent of 32 transfer periods e g 200 ns at fast 160 4 n...

Page 96: ...gnals 3 wait the equivalent of 32 transfer periods e g 200 ns at fast 160 4 simultaneously negate REQ and P_CRCA signals 5 wait 32 the equivalent of transfer periods e g 200 ns at fast 160 6 set precompensation to negotiated state 7 negate SEL signal 8 simultaneously assert and negate REQ and P_CRCA signals at the negotiated transfer period 32 times e g 2 x 6 25 x 32 400 ns at fast 160 9 negate RE...

Page 97: ...nd DB 15 0 signals negated while continuing to assert and negate ACK at the negotiated transfer period for the equivalent of 8 transfer periods e g 50 ns at fast 160 3 keep the P1 DB 15 0 and ACK signals negated for the equivalent of 8 additional transfer periods 4 simultaneously assert and negate P1 and DB 15 0 signals at twice the negotiated transfer period i e simultaneously repeat a 1100b bit ...

Page 98: ...the phase of P1 by withholding the next transition of P1 at the start of the first two transfer periods that have invalid data Beginning with the third transfer period with invalid data P1 shall be toggled every two transfer periods until valid data is sent The data invalid state shall have at least one transition of P1 before changing states The minimum data invalid time is four transfer periods ...

Page 99: ...ignal The DT DATA IN phase without training starts on the first assertion of REQ if the SEL is not asserted The TARG begins pacing transfers only after meeting all the following a signal restrictions between information transfer phases b the signal restrictions between a RESELECTION phase and a DT DATA IN phase or c the signal restrictions between a SELECTION phase and a DT DATA OUT phase The TARG...

Page 100: ...After the TARG stops asserting and negating REQ it will not assert REQ again until the requirements in 10 12 are met After transmitting the last data word of a DT DATA OUT phase the INIT shall a continue asserting and negating the ACK and P1 signals until it detects a change to the C D I O or MSG signals and b negate the ACK and P1 signals within 200 ns of detecting a change to the C D I O or MSG ...

Page 101: ...r a minimum of one transmit hold time If the I O signal is false i e transfer to the TARG to receive SPI information units the TARG 1 reads the value of the DB 15 0 signals within one receive hold time of the transition of the ACK signal If write flow control is enabled and the current SPI data stream information unit is the last SPI data stream information unit of the stream then 1 The TARG asser...

Page 102: ...ata Invalid Data REQ ACK Data P_CRCA The assertion of the REQ signal corresponding to the last iuCRC transfer Last iuCRC Don t Care Target should negate the P_CRCA signal a minimum of a flow control transmit setup time before the start of the next IU Slowest negation of P_CRCA Target should not assert the P_CRCA signal until a minimum of a flow control transmit hold time after the end of the previ...

Page 103: ...Q SPI status information unit pair to the INIT with a CHECK CONDITION status and a sense key set to ABORTED COMMAND and an additional sense code set to INITIATOR DETECTED ERROR MESSAGE RECEIVED for the task associated with the received INITIATOR DETECTED ERROR message If the information unit that failed was a SPI status information unit and the message received was an INITIATOR DETECTED ERROR mess...

Page 104: ...or the information unit that follows the SPI L_Q information unit After transferring all the bytes the TARG shall change to a DT DATA IN phase and transmit a SPI status information unit with a RSPVALID bit of one and the packetized failure code set to INVALID TYPE CODE RECEIVED IN SPI L_Q INFORMATION UNIT If a TARG receives a SPI L_Q information unit with an illegal data length the TARG shall tran...

Page 105: ...get using DT data transfers The target shall assert the I O and MSG signals and negate the C D signal during the REQ ACK handshake s of this phase 2 DT DATA OUT phase The DT DATA OUT phase allows the target to request that data be sent from the initiator to the target using DT data transfers The target shall assert the MSG signal and negate the C D and I O signals during the REQ ACK handshake s of...

Page 106: ...11 75 ns 2 Maximum 26 66 MB s X 19 100 ns 1 Maximum 20 00 MB s X 1F 120 ns 1 Maximum 16 00 MB s X 25 150 ns 1 Maximum 13 33 MB s X 2B 175 ns 1 Maximum 11 42 MB s X 32 200 ns Maximum 10 00 MB s X 38 225 ns Maximum 8 88 MB s X 3E 250 ns Maximum 8 00 MB s X 44 275 ns Maximum 7 27 MB s X 4B 300 ns Maximum 6 66 MB s X 51 325 ns Maximum 6 15 MB s X 57 350 ns Maximum 5 71 MB s PPR Transfer Period 6 X 5D ...

Page 107: ...uring REQ ACK handshaking in this phase 1 6 9 MESSAGE phase The MESSAGE phase is divided into MESSAGE IN and MESSAGE OUT phases depending on the direction of message information transfer In either phase several messages can be transferred The first byte transferred in a MESSAGE phase must be a single byte message or the first byte of a multiple byte message If the message consists of more than one...

Page 108: ...rmation correctly without detecting a parity error the TARG shall enter the INFORMATION TRANSFER phase other than the MESSAGE OUT phase and execute at least one byte of information transfer in order to request the INIT not to retry message transfer During some message transfer the TARG may report the normal completion of message reception by switching to the BUS FREE phase for example ABORT TASK S...

Page 109: ...T driving to in TARG driving 1 The TARG delays driving the P_CRCA by at least one Data Release Delay plus one Bus Settle Delay after negating the C D signal 2 The INIT releases the P_CRCA signal within one Data Release Delay after the transition of the C D signal to false When switching the P_CRCA signal direction from in TARG driving to out INIT driving 1 The TARG releases the P_CRCA signal withi...

Page 110: ...sponse within a specified period 250 ms the IDD executes the timeout process see Section 1 6 4 and releases the SCSI bus once After that the IDD executes the retry process of the RESELECTION phase see Section 3 1 The user can select the number of retries of the RESELECTION phase by the CHANGE DEFINITION command Table 1 21 Retry count setting for RESELECTION phase RSRTY bit Retry count for RESELECT...

Page 111: ...ignal true before ATN transmit setup time or more from the timing of setting false the ACK signal for the last byte being transferred in the current bus phase or information unit If the ATN sending timing is delayed the TARG may not be informed of the ATTENTION condition until the next bus phase or information unit The INIT may not operate as it should When transferring message information in seve...

Page 112: ...unit transfer other than a SPI data stream information unit the TARG will enter MESSAGE OUT phase at the completion of the current SPI information unit i e after receiving all the ACKs from the INIT for the current SPI information unit When the ATN signal becomes true in the information unit transfer other than a SPI data stream information unit the TARG will enter MESSAGE OUT phase at the complet...

Page 113: ... 41 ATTENTION condition Note The ATTENTION condition generated by the INIT determines the message level to be used in the command execution sequence Details are explained in Section 2 1 3 If the ATTENTION condition is not generated the TARG uses a TASK COMPLETE message only ...

Page 114: ...e disk drive 3 Initializes the operation mode to its initial status just after power on if it has been set by the message or command The current value of the parameter set by the MODE SELECT command is initialized to the saved value previously established If the value is not saved it is initialized to the default value The synchronous transfer parameters defined between the IDD and other SCSI devi...

Page 115: ...enter the BUS FREE phase in order to report an error condition For details see Section 1 6 1 Figure 1 43 shows the allowable bus phase sequence Figure 1 44 provides an example of bus phase sequence during single command execution Note Figure 1 43 shows the bus phase sequence applied to the system which uses the ARBITRATION phase and the system which does not use the phase Also this Figure compares...

Page 116: ...1 98 C141 C011 Figure 1 43 Bus phase sequence 1 of 2 ...

Page 117: ...C141 C011 1 99 Figure 1 43 Bus phase sequence 2 of 2 ...

Page 118: ...1 100 C141 C011 Figure 1 44 Example of bus phase transition at execution of a single command 1 of 5 ...

Page 119: ...C141 C011 1 101 Figure 1 44 Example of bus phase transition at execution of a single command 2 of 5 ...

Page 120: ...1 102 C141 C011 RESELECTION Figure 1 44 Example of bus phase transition at execution of a single command 3 of 5 ...

Page 121: ...C141 C011 1 103 Figure 1 44 Example of bus phase transition at execution of a single command 4 of 5 ...

Page 122: ...1 104 C141 C011 Figure 1 44 Example of bus phase transition at execution of a single command 5 of 5 TASK COMPLETE ...

Page 123: ...1 45 The normal progression for selection without using attention condition see 10 5 3 if QAS is disabled is 1 from BUS FREE to ARBITRATION 2 from ARBITRATION to SELECTION or RESELECTION and 3 from SELECTION or RESELECTION to one or more DT DATA phases and 4 from the final DT DATA phase to BUS FREE Note See Figure 1 47 48 49 50 for the sequencing of SPI information units within the DT DATA phases ...

Page 124: ...all be as shown in Figure 1 46 The normal progression for selection using attention condition see 10 5 2 3 if QAS is disabled is 1 from BUS FREE to ARBITRATION 2 from ARBITRATION to SELECTION 3 from SELECTION to MESSAGE OUT 4 from MESSAGE OUT to MESSAGE IN and 5 from MESSAGE IN to BUS FREE Figure 1 46 Phase sequences for selection with attention condition with information unit transfers enabled ...

Page 125: ...ation i e PPR or WDTR or SDTR that results in IU_REQ being changed the TARG will abort all tasks except the current task for the INIT participating in the negotiation and the INIT shall abort all tasks except the current task for the TARG When an information unit transfer agreement is in effect there is no option equivalent to the physical disconnect without sending a SAVE DATA POINTERS message Th...

Page 126: ...es the I_T_L_Q nexus for that I O process SCSI devices using information unit transfers may receive several commands during an initial connection This occurs when an INIT uses the multiple command option in the SPI L_Q information unit For each SPI L_Q received with a multiple command type or a last command type a logical connection occurs and an I_T_L_Q nexus is formed If there is a phase change ...

Page 127: ...C141 C011 1 109 Figure 1 47 SPI information unit sequence during initial connection ...

Page 128: ...1 110 C141 C011 Figure 1 48 SPI information unit sequence during data type transfers ...

Page 129: ...C141 C011 1 111 Figure 1 49 SPI information unit sequence during data stream type transfers ...

Page 130: ...1 112 C141 C011 Figure 1 50 SPI information unit sequence during status transfers ...

Page 131: ...s may be sent If the TASK MANAGEMENT FUNCTIONS field is a supported value not equal to 00h the TARG performs the selected task management function before processing any further SPI information units regardless of the command type On completion of a supported task management function the TARG goes to a BUS FREE phase No SPI status information unit shall be reported for the task management function ...

Page 132: ...dard 001b Requests that the task be managed according to the rules for a head of queue task attribute See the SCSI Architecture Model 2 standard 010b Requests that the task be managed according to the rules for an ordered attribute See the SCSI Architecture Model 2 standard 011b Reserved 100b Requests that the task be managed according to the rules for an automatic contingent allegiance task attri...

Page 133: ...the task with a GOOD status The packetized failure code shall be set to TASK MANAGEMENT FUNCTION NOT SUPPORTED The ADDITIONAL CDB LENGTH field contains the length in 4 byte words of the ADDITIONAL CDB field The write data WRDATA bit and read data RDDATA bit are not supported The CDB field contains the actual CDB to be interpreted by the addressed logical unit The CDB field and the task attribute f...

Page 134: ...tion units The receipt of an error free i e no iuCRC error SPI L_Q information unit by an INIT shall cause the INIT to restore the data pointers Table 1 25 SPI L_Q information unit Bit Byte 7 6 5 4 3 2 1 0 0 TYPE 1 Reserved 2 MSB 3 TAG LSB 4 MSB 11 LOGICAL UNIT NUMBER LSB 12 Reserved 13 MSB 14 15 DATA LENGTH LSB 16 DIDI DIRECTION Reserved 17 Reserved 18 MSB 19 IUCRC INTERVAL LSB 20 MSB 21 22 23 IU...

Page 135: ...Data Sent by a SCSI target device to indicate a SPI data information unit shall follow this SPI L_Q information unit The DATA LENGTH field shall not be set to zero For a bidirectional command the direction of the SPI data infor mation unit shall be indicated in the BIDI DIRECTION field of the SPI L_Q in formation unit as defined in table 1 27 05h Data Stream Sent by a SCSI target device to indicat...

Page 136: ...The TARG will not set the data length to a value that exceeds the maximum burst size as defined in the disconnect reconnect page The BIDI DIRECTION field determines the data direction if the command is a bidirectional command and the type code is data or data stream The code values for the BIDI DIRECTION field are defined in table 1 27 Table 1 27 BIDI DIRECTION Codes Description 00b A unidirection...

Page 137: ...ation unit see table 1 29 contains data All the SPI data stream information units transferred after a SPI L_Q information unit with a type of data stream shall be the size indicated in the DATA LENGTH field of the SPI L_Q information unit If the data transfer size is not a multiple of the data length the TARG ends the stream at a data length boundary and sends a new SPI L_Q with a smaller data len...

Page 138: ...E phase following a SPI data stream information unit by an INIT shall be equivalent to the INIT receiving a DISCONNECT message The detection of a QAS REQUEST message following a SPI data stream information unit by an INIT shall be equivalent to the INIT receiving a DISCONNECT message To end a sequence of SPI data stream information units an INIT may request a disconnect by establishing an attentio...

Page 139: ...DATA LENGTH field in the SPI L_Q information unit to zero Table 1 30 SPI status information unit Bit Byte 7 6 5 4 3 2 1 0 0 DATA 1 RESERVED 2 RESERVED FOR FCP SNSVALID RSPVALID 3 STATUS 4 MSB 7 SENSE DATA LIST LENGTH n m LSB 8 11 PACKETIZED FAILURES LIST LENGTH m 11 12 M PACKETIZED FAILURES M 1 N SENSE DATA N 1 MSB N 2 N 3 N 4 IUCRC LSB A sense data valid bit SNSVALID of zero indicates the sense d...

Page 140: ...ST LENGTH field contains a length of 4 Other lengths are reserved for future standardization If no packetized failure data is provided RSPVALID will be set to zero The INIT shall ignore the PACKETIZED FAILURES LIST LENGTH field and shall assume a length of zero The STATUS field contains the status of a task that completes See the SCSI Architecture Model 2 standard for a list of status codes The PA...

Page 141: ...N FAILED 06h INVALID TYPE CODE RECEIVED IN SPI L_Q INFORMATION UNIT 07h ILLEGAL REQUEST RECEIVED IN SPI L_Q INFORMATION UNIT 11h Reserved The SENSE DATA field contains the information specified by the SCSI Primary Commands 3 standard for presentation by the REQUEST SENSE command The proper sense data shall be presented when a SCSI status byte of CHECK CONDITION is presented as specified by the SCS...

Page 142: ...minant SCAM initiator when it broadcasts the numerically highest ID character string during separation The SCAM initiator which does not have the highest ID character string is set to a subaudinate SCAM initiator Notes The level 1 SCAM initiator is not always required for execution of the Dominant Initiator Contention function It shall be used to detect the Dominant Initiator Contention function w...

Page 143: ...meters This can eliminate the requirement of SCSI ID classification SCSI ID assignment After all SCSI IDs have been classified the dominant SCAM initiator shall start the SCAM protocol and repeat ID assignment to all SCSI devices The dominant SCAM initiator shall execute the Dominant Initiator Contention function sequence to prove that the initiator is still dominant by itself If the previously do...

Page 144: ...SI selection When the SCAM target detects the start of SCAM protocol it shall enter the ID Assignable status If the SELECTION phase of the current IDs of SCAM target continues to valid during at least the response delay of SCAM unassigned ID selection this SCAM target shall respond to the selection and assert the BSY signal The SCAM target shall implicitly enter the ID Assigned status as if its ID...

Page 145: ...in the response time of SCAM tolerant selection but does not respond or recognize the SCAM selection The SCAM target can enter the Reset Delay status and allow local initialization by the reset status The SCAM target exists this status and enters the SCAM Monitor status within a SCAM reset to SCAM selection delay 3 Level 2 SCAM target Figure 1 52 shows the operations of level 2 SCAM target Its sta...

Page 146: ...tion When the SCAM target is separated and its Assign ID action code is received the specified ID is set to the current and already assigned ID The SCAM target releases all SCSI bus signals and enters the Assigned ID status When the SCAM target receives a Configuration Process Complete function code or the SCAM protocol has ended if the C D signal becomes false the target shall release all SCSI bu...

Page 147: ...ith the higher data speed are included in this Standard 1 11 2 Device connection Connection between an single ended transceiver and device The maximum length of accumulated signal path between terminators shall be 3 0 m if up to four 25 pF capacitance devices are used The maximum length of accumulated signal path between terminators shall be 1 5 m if five to eight devices that have maximum capacit...

Page 148: ... for SCSI devices The end of bus shall be defined at each end point The end point can be inside of an SCSI device Single ended bus signals not defined as RESERVED GROUND or TERMPWR shall be terminated at each bus end securely Each signal termination shall satisfy the following requirements 1 Each terminator shall be powered from the TERMPWR line 2 Each terminator shall feed the current to a signal...

Page 149: ...e or High Impedance state Each signal supplied by the SCSI device shall have the following output characteristics when measured at the connector position of SCSI device 1 VOL Low level output voltage 0 0 to 0 5 VDC if IOL 48 mA Signal assert state 2 VOH High level output voltage 2 5 to 3 7 VDC Signal negate state 3 The output characteristics in signal negate state shall be limited to allow operati...

Page 150: ...Figure 1 54 cannot be used for this measurement Figure 1 53 Comparison of active negate current and voltage All single ended type drivers shall keep the high impedance state between the power on and power off cycles The SCSI device shall satisfy the following specifications if the load capacitor CL is within 15 pF 5 and if the unbalanced test circuit of Figure 1 54 is used for measurement 1 trise ...

Page 151: ... False signal 3 IIL Low level input current 20 µA if VI 0 5 VDC 4 IIH High level input current 20 µA if VI 2 7 VDC 5 Minimum input hysteresis 0 3 VDC The transient leakage current which may be generated during physical insertion of an SCSI device for example at the ESD protection circuit shall be the exponentially decreasing current to be less than the following specifications value 1 IIH HP High ...

Page 152: ...6 5 2 compared ST data transfer mode The act of verifying that the physical layer is able to transfer test data at the negotiated speed and width between the INIT and TARG i e a quick check for physical domain validation For example two wide SCSI devices connected with a narrow cable will discover that the cable does not support wide transfers during this checking These SCSI devices will then re n...

Page 153: ... current from the signal line to ground A negation is produced when positive supply voltage current is sourced from source 1 to the signal line and source 3 sinks the same current from the signal line to ground LVD RECEIVER Figure 1 55 LVD transceiver architecture Balanced transmissions occur when the changes in SIGNAL current and the changes in the SIGNAL current precisely cancel each other The b...

Page 154: ...1 136 C141 C011 Figure 1 56 Connection to the LVD receivers ...

Page 155: ...measurements shall be made with a nominal 1MHz source with the same nominal D C level on the signal and the signal as specified in Table 1 33 The driving source from the instrumentation shall apply an A C signal level less than 100 mV rms Devices containing the enabled bus termination shall have maximum values 1 5 times the maximums listed in Table 1 33 Differential bus termination circuitry that ...

Page 156: ...siganls C1 C2 pF 1 5 REQ ACK and DB 15 0 P_CRCA P1 C1 C2 pF 3 All other signal C1 C1 REQ pF 2 For C1is any capacitance of DB 15 0 P_CRCA P1 C2 C2 REQ pF 2 For C2is any capacitance of DB 15 0 P_CRCA P1 C1 C1 ACK pF 2 For C1is any capacitance of DB 15 0 P_CRCA P1 C2 C2 ACK pF 2 For C2is any capacitance of DB 15 0 P_CRCA P1 1 12 7 System level requirements for LVD SCSI drivers and receivers The requi...

Page 157: ...sed by the addition of device capacitive load 4 This is the difference in voltage signal commons for SCSI devices on the bus 1 13 SCSI bus fairness 1 Fairness Model Implementation of the SCSI bus fairness is optional A SCSI device determines fairness by monitoring prior arbitration attempts by other SCSI devices It shall put off arbitration for itself until all lower priority SCSI devices that los...

Page 158: ...requires that the SCSI IDs of all arbitrating SCSI devices appear on the bus within a Bus Set Delay since BSY was first asserted After this time a SCSI device examines the bus to detect arbitrating situation Since the lower priority SCSI IDs begin to disappear after an Arbitration Delay from the assertion of BSY the data bus shall be sampled after a Bus Set Delay but before an Arbitration Delay 3 ...

Page 159: ... two SCSI devices on the SCSI bus in order to control a series of bus phase sequence during command execution The messages are transferred over the SCSI data bus in the MESSAGE OUT and MESSAGE IN phases 2 1 1 Message format There are three message formats are listed below The first byte of the message is a message code in any format See Figure 2 1 One byte message This consists of a message code o...

Page 160: ...2 2 C141 C011 Figure 2 1 Message format ...

Page 161: ...ARITY ERROR 1 TARG INIT 0A LINKED TASK COMPLETE 1 TARG INIT 0C TARGET RESET 1 TARG INIT 0D ABORT TASK 1 TARG INIT 0E CLEAR TASK SET 1 TARG INIT 12 CONTINUE TASK 1 TARG INIT 13 TARGET TRANSFER DISABLE 1 TARG INIT 1C LOGICAL UNIT RESET 1 TARG INIT 20 SIMPLE 2 TARG INIT 21 HEAD OF QUEUE 2 TARG INIT 22 ORDERED 2 TARG INIT 23 IGNORE WIDE RESIDUE 2 TARG INIT 80 to FF IDENTIFY 1 TARG INIT Note If a signa...

Page 162: ...ION condition If SCSI device supports messages other than TASK COMPLETE message the SCSI device creates ATTENTION condition or responds to the ATTENTION condition To indicate that the TARG can support messages other than TASK COMPLETE message the TARG initiates MESSAGE OUT phase in response to ATTENTION condition Note If the INIT is in the ARBITRATION phase and if it generates an ATTENTION conditi...

Page 163: ...stored implicitly and the Saved pointer value is set to the current pointer value 2 2 SCSI Pointer The SCSI pointer feature is required by the INIT to control the command execution on the SCSI bus It allows multiple TARGs and logical units to process multiple commands concurrently and allows the TARG to retry processing in bus phases 1 Type of pointers The following three types of SCSI pointers ha...

Page 164: ...alue of the command Therefore if the command disconnect is expected during data transfer the TARG shall save the current data pointer values by issuing the SAVE DATA POINTER message before issuing the DISCONNECT message Note As the TARG may set any pointer value before starting disconnect processing or command termination the pointer value of the INIT may or may not point to the byte position of t...

Page 165: ...C141 C011 2 7 Figure 2 2 SCSI pointer configuration ...

Page 166: ...us in MESSAGE OUT or COMMAND phase When the TARG completes normal message transfer it enters the BUS FREE phase The TARG determines that the message transfer has completed normally if the ATN signal is false when the ACK signal becomes false 2 3 2 SAVE DATA POINTER message X 02 T I The SAVE DATA POINTER message requests the INIT to save the current data pointer When receiving this message the INIT...

Page 167: ...rforms the following regardless of the ATN signal status If the LUN has been determined prior to this message the TARG clears all of the currently executing or queued I O operations which have been initiated to the specified logical unit by the source INIT of this message and enters the BUS FREE phase All of the hold data and status information or the sense data of the logical unit and INIT are cl...

Page 168: ...ge after negating the ACK signal associated with the rejected message if it is received in the MESSAGE OUT phase This is required to allow the INIT to identify the rejected message Section 3 1 explains the IDD operation details when the INIT returns this message in response to the message sent by the IDD 2 3 8 NO OPERATION message X 08 I T The NO OPERATION message does not result in any operation ...

Page 169: ...eared No status or end message is sent to the INIT This message does not affect on the held status data and commands of the I O operations which are being executed or queued by another unit Also this message does not abort another I O operation which is queued in the INIT of this message source The system environment and conditions previously established by the MODE SELECT parameter are not change...

Page 170: ...erwise the TARG may treat the connection as an overlapped command The INIT should avoid sending this message to the TARG that have not implemented this message Such the TARG may not respond as described in this section An application client can determine whether a device server implements this message by examining the TRANDIS bit in the standard INQUIRY data The application client shall inform the...

Page 171: ...age by issuing a TARGET TRANSFER DISABLE link control function in the send SCSI command phase The IDD does not support this message 2 3 16 LOGICAL UNIT RESET message X 1C I T When the TARG receives this message normally it enters the BUS FREE phase In case the I_T_L_x nexus has been established with LUN 0 TARG clears all the tasks in the logical unit and generates UNIT ATTENTION condition for all ...

Page 172: ...ed tasks received after this task is executed after this task except for tasks received with a HEAD OF QUEUE message 2 3 18 IGNORE WIDE RESIDUE message X 23 T I Bit Byte 7 6 5 4 3 2 1 0 0 Message Code X 23 1 Number of bytes to IGNORE X 01 This message the number of bytes of invalid data is notified from TARG to INIT when not coming up to the width of the data bus which the number of bytes of data ...

Page 173: ...fy the logical unit number LUN for the device Note The LUN of the IDD is fixed to 0 c Function of message After the SELECTION phase has completed the INIT usually sends the IDENTIFY message to the TARG as the first message this message specifies a logical unit for I O operations Also after the RESELECTION phase has completed the TARG shall send the IDENTIFY message to the INIT as the first message...

Page 174: ...signed to the two SCSI devices The Transfer Period is the minimum repeat cycle of REQ and ACK pulses which are allowed for data reception by SCSI devices It is the minimum time between the leading edge of an REQ pulse and the leading edge of the next REQ pulse or between the leading edge of an ACK pulse and the leading edge of the next ACK pulse The REQ ACK Offset is the maximum number of REQ puls...

Page 175: ...e synchronous data transfer to be set it asserts the ATN signal that is generating an ATTENTION condition for message exchange and requests the TARG to receive the SYNCHRONOUS DATA TRANSFER REQUEST message After the MESSAGE OUT phase has completed normally the TARG shall return the SYNCHRONOUS DATA TRANSFER REQUEST message or the MESSAGE REJECT message to the INIT If the ACK signal is still true a...

Page 176: ...all consider it as the unsuccessful message exchange and the two SCSI devices shall select the asynchronous data transfer mode between them If the TARG enters the MESSAGE IN phase immediately after the INIT has responded with the SYNCHRONOUS DATA TRANSFER REQUEST message and if the TARG first sends the MESSAGE REJECT message to the INIT the INIT shall consider it as the unsuccessful selection of s...

Page 177: ...pecify using the CHANGE DEFINITION command Table 2 4 Synchronous mode data transfer request setting SDTR bit Operation 0 Even if the IDD recognizes that the synchronous mode transfer and wide mode transfer settings are necessary the IDD does not send the SYNCHRONOUS DATA TRANSFER REQUEST message However when the INIT sends the SYNCHRONOUS DATA TRANSFER REQUEST message the IDD responds to the messa...

Page 178: ...the INIT moves to the default transfer mode c Transfer mode when the SCSI ID is not defined for INITs Even if the SCSI ID of the INIT is not posted in the SELECTION phase if a single INIT is used and if it does not use the RESELECTION phase the message can be exchanged and the data transfer mode can be selected between the IDD and the INIT In this case the IDD sets a unique data transfer mode for ...

Page 179: ...fer Period X 11 Synchronous mode 13 3 MB s max 8 bit mode 26 6 MB s max 16 bit mode REQ Period 75 ns ACK Period 75 ns X 13 76 ns X 19 100 ns SDTR Transfer Period Specified value by INIT Synchronous mode 10 0 MB s max 8 bit mode 20 0 MB s max 16 bit mode REQ Period 100 ns ACK Period 100 ns X 1A 104 ns X 1F 124 ns SDTR Transfer Period Specified value by INIT Synchronous mode 8 00 MB s max 8 bit mode...

Page 180: ... the IDD and the data transfer mode set to the IDD and INIT by the response of this message from the INIT If the INIT does not respond as defined on Table 2 6 the IDD assumes that the synchronous data transfer is unavailable and selects the asynchronous data transfer mode between the IDD and the INIT If an ATTENTION condition has occurred in the COMMAND phase and if the IDD has entered the BUS FRE...

Page 181: ... Synchronous mode 13 3 MB s max 8 bit mode 26 6 MB s max 16 bit mode REQ Period 75 ns ACK Period Specified value by INIT X 13 76 ns X 19 100 ns Synchronous mode 10 0 MB s max 8 bit mode 20 0 MB s max 16 bit mode REQ Period 100 ns ACK Period Specified value by INIT X 1A 104 ns X 1F 124 ns Synchronous mode 8 00 MB s max 8 bit mode 16 0 MB s max 16 bit mode REQ Period 125 ns ACK Period Specified valu...

Page 182: ...all exchange the WIDE DATA TRANSFER REQUEST message with another SCSI device before exchanging the SYNCHRONOUS DATA TRANSFER REQUEST message If the SCSI device having the wide mode transfer function receives the WIDE DATA TRANSFER REQUEST message the data transfer mode is reset to the asynchronous transfer mode 1 Wide mode parameters The data bus width between two SCSI devices is determined by exc...

Page 183: ...he error recovery procedure based on the SCSI Bus protocol for the erroneous phase up to 3 times If the retry fails this negotiation is regarded as a failure The mode setting for wide transfer between the INIT and the TARG must be set to the 8 bit data bus width 3 Message exchange started by the TARG If the TARG recognizes the need of message exchange and if the wide data mode transfer request is ...

Page 184: ... IDD sends the WIDE DATA TRANSFER REQUEST message to the INIT by sending the CHANGE DEFINITION command For details on setting refer to Section 3 1 4 in the SCSI Logical Specifications b Data bus width status determination a Default 8 bit mode status The default 8 bit data bus width mode is selected automatically when the power supply is turned on a RESET condition occurs or the TARGET RESET messag...

Page 185: ...ansfer Width Exponent 00 8 bit width Transfer Width Exponent 01 16 bit width X 02 or larger Transfer Width Exponent 01 16 bit width d Wide mode setting from the IDD to the INIT If the WIDE DATA TRANSFER REQUEST message is enabled to send by the CHANGE DEFINITION command and if the default 8 bit data bus width mode has been selected between the IDD and the INIT the IDD executes one of the following...

Page 186: ...04 m X 00 n x y m Transfer Period Factor 4 m ns n REQ ACK OFFSET x Transfer Width Exponent Transfer width 2x bytes y Protocol Options Bit Bit 7 6 5 4 3 2 1 0 Byte7 PCMP_EN RTI RD_STRM WR_FLOW HOLD_MCS QAS_REQ DT_REQ IU_REQ PCMP_EN Precompensation Enable RTI Retain Training Information RD_STRM Read Streaming WR_FLOW Write Flow Control HOLD_MCS Hold Margin Control Settings QAS_REQ Quick Arbitration ...

Page 187: ...equal to 200 ns For ST synchronous data transfer the REQ ACK OFFSET is the maximum number of REQ assertions allowed to be outstanding before a corresponding ACK assertion is received at the TARG The size of a data transfer may be 1or 2 bytes depending on the values in the transfer width exponent field For DT synchronous data transfer the REQ ACK OFFSET is the maximum number of REQ transitions allo...

Page 188: ...o indicate that the TARG should enable read streaming and read flow control In response the TARG shall set RD_STRM to one if it is capable of read streaming and read flow control and zero if it is not The INIT shall set RD_STRM to zero to indicate that the TARG shall disable read streaming and read flow control In response the TARG shall set RD_STRM to zero Read streaming and read flow control onl...

Page 189: ...ons defined in table 2 11 shall be allowed all allowed All other combinations are reserved Table 2 11 Valid protocol options bit combinations PCMP_EN RTI RD_STRM WR_FLOW HOLD_MCS QAS_REQ DT_REQ IU_REQ DESCRIPTION 0 0 0 0 0 1 0 0 0 Use ST DATA IN and ST DATA OUT phases to transfer data 0 0 0 0 0 1 1 0 0 Use ST DATA IN and ST DATA OUT phases to transfer data with asynchronous transfers and participa...

Page 190: ... agreement only applies to ST DATA IN phases ST DATA OUT phases DT DATA IN phases and DT DATA OUT phases All other information transfer phases shall use an eight bit data path and c on the protocol option is to be used The originating SCSI device the SCSI device that sends the first of the pair of PARALLEL PROTOCOL REQUEST messages sets its values according to the rules above to permit it to recei...

Page 191: ...TA OUT phases with information units MESSAGE REJECT message Eight bit asynchronous data transfer with PROTOCOL OPTIONS field set to 0h Parity error on responding message Eight bit asynchronous data transfer with PROTOCOL OPTIONS field set to 0h Unexpected bus free as a result of the responding message Eight bit asynchronous data transfer with PROTOCOL OPTIONS field set to 0h No response Eight bit ...

Page 192: ...TOCOL REQUEST message s values the INIT shall create an attention condition and the first message shall be a MESSAGE REJECT message If during the PARALLEL PROTOCOL REQUEST message the INIT creates an attention condition and the first message of the MESSAGE OUT phase is either a MESSAGE PARITY ERROR or MESSAGE REJECT message the data transfers shall be considered to be negated by both SCSI devices ...

Page 193: ... should issue the REQUEST SENSE command to obtain the error information 3 1 Error Conditions and Retry Procedure 1 MESSAGE OUT phase parity error When the IDD detects a parity error of the SCSI bus during the MESSAGE OUT phase it retries the MESSAGE OUT phase up to 3 times If the IDD fails to recover a parity error it proceeds to the next procedure For details see Section 1 6 9 If the LUN is alrea...

Page 194: ...TED COMMAND B INITIATOR DETECTED ERROR message received 48 00 If the LUN is not identified yet the IDD does not generate the sense data and enters the BUS FREE phase immediately If the STATUS phase has already completed the IDD also enters the BUS FREE phase but does not send the status again 5 Receiving a MESSAGE PARITY ERROR message If the IDD receives a MESSAGE PARITY ERROR message from the INI...

Page 195: ...nd is attempted and the IDD does not report the command completion status and message At this time the IDD creates the sense information with Sense Key Additional Sense Code of ABORTED COMMAND B Message Error 43 00 d LINKED TASK COMPLETE The IDD immediately enters the BUS FREE phase without requesting the next linked command CDB The command link is broken Then the IDD creates the sense information...

Page 196: ...IDD sets the data transfer width to the 8 bit mode and the asynchronous mode and continues command execution k PARALLEL PROTOCOL REQUEST The IDD assumes that the INIT does not support the DT DATA IN OUT transfer mode The IDD sets the data transfer mode to the 8 bit width mode and the asynchronous mode and continues command execution 7 Reselection timeout If the INIT does not respond within the spe...

Page 197: ...IDD considers it as an error in the message protocol and enters the BUS FREE phase immediately IDENTIFY ABORT TASK TARGET REST 9 Internal controller error If a hardware or firmware error inside of the IDD is detected and if the LUN is already identified the IDD abnormally terminates the currently executing command in the CHECK CONDITION status In such case the IDD generates the sense data which in...

Page 198: ...ders that the LUN is not identified and it enters the BUS FREE phase immediately Table 3 1 gives and outline of the retry procedure for handling SCSI bus errors If the IDD performs the error recovery Table 3 1 means the operation after the error recovery fails The symbols used in this table are as follows LUN I An LUN is already identified N An LUN is not yet X Don t care GOOD GOOD status CHECK CH...

Page 199: ... COMMAND MESSAGE REJECT I CHECK ABORTED COMMAND N BUS FREE NO SENSE RESTORE POINTERS I CHECK BASED ON ORIGINAL ERROR SAVE DATA POINTER I Continues the command execution without disconnection SIMPLE I BUS FREE ABORTED COMMAND SYNCHRONOUS DATA TRANSFER REQUEST X Sets data transfer mode to asynchronous mode and continues the command execution WIDE DATA TRANSFER REQUEST X Sets wide transfer mode to 8 ...

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Page 201: ...from the SCSI bus and the initiator temporarily when SCSI bus operation becomes unnecessary during command processing Initiator SCSI device that has initiated an input output operation on the SCSI device This can be abbreviated as INIT Logical unit Simple unit of equipment that can be directed to perform one I O operation on the SCSI bus LUN Logical unit number used to identify a logical unit LUT ...

Page 202: ...d to report the error Sense key Four bit code attached to sense data to identify the class of the detected error Status One byte of information that is transferred from a target to an initiator on termination of each command to indicate the command termination status Target SCSI device which performs I O initiated by an initiator It can be abbreviated as TARG ...

Page 203: ...ier IDD Intelligent Disk Drive INIT INITiator ISO International Standardization Organization L LSB Least Significant Byte LUN Logical Unit Number LVD Low Voltage Differential M MSB Most Significant Byte MSG MeSeaGe O OEM Original Equipment Manufacturer P PPR Parallel Protocol Request R REQ REQuest RST ReSeT S SCSI Small Computer System Interface SDTR Synchronous Data Transfer Request SE Single End...

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Page 205: ... Almagro 40 28010 Madrid SPAIN TEL 34 91 681 8100 FAX 34 91 681 8125 FUJITSU AUSTRALIA LIMITED 2 Julius Avenue Cnr Delhi Road North Ryde N S W 2113 AUSTRALIA TEL 61 2 9776 4555 FAX 61 2 9776 4556 FUJITSU HONG KONG LTD 10 F Lincoln House 979 King s Road Taikoo Place Island East Hong Kong TEL 852 2827 5780 FAX 852 2827 4724 FUJITSU KOREA LTD Coryo Finance Center Bldg 23 6 YoulDo Dong Young DungPo Gu...

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Page 207: ...of this publication What is your occupation Your other comments may be entered here Please be specific and give page paragraph and line number references where applicable Your Name Return Address Sales Operating Installing Maintaining Learning Reference Fair Poor Very Good Good Very Poor Fully covered Well Illustrated Thank you for your interest Please send this sheet to one of the addresses in a ...

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