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APPENDIX A Instruction Lists

Note:

The field "dir" in the TYPE-D instruction format has the following relation to the values "dir8" to
"dir10" in assembly notation.

Table A.2-13 Direct Addressing Instructions (14 Instructions)

Mnemonic

Format

CYC

FLAG

NZVC

Operation

Remarks

DMOV   @dir10, R13
DMOV   R13,    @dir10
DMOV   @dir10, @R13+
DMOV   @R13+, @dir10
DMOV   @dir10, @–R15
DMOV   @R15+, @dir10

D
D
D
D
D
D

08
18

0C
1C
0B
1B

b
a

2a
2a
2a
2a

– – – –
– – – –
– – – –
– – – –
– – – –
– – – –

(dir10)

→

R13

→

(dir10)

→

(R13),R13+=4

(R13)

→

(dir10),R13+=4

R15–=4,(dir10)

→

(R15)

→

(dir10),R15+=4

Word
Word
Word
Word
Word
Word

DMOVH @dir9, R13
DMOVH R13, @dir9
DMOVH @dir9, @R13+
DMOVH @R13+, @dir9

D
D
D
D

09
19

0D
1D

b
a

2a
2a

– – – –
– – – –
– – – –
– – – –

(dir9)

→

R13

→

(dir9)

→

(R13),R13+=2

(R13)

→

(dir9),R13+=2

Half-word
Half-word
Half-word
Half-word

DMOVB @dir8, R13
DMOVB R13, @dir8
DMOVB @dir8, @R13+
DMOVB @R13+, @dir8

D
D
D
D

0A
1A

0E
1E

b
a

2a
2a

– – – –
– – – –
– – – –
– – – –

(dir8)

→

R13

→

(dir8)

→

(R13),R13++

(R13)

→

(dir8),R13++

Byte
Byte
Byte
Byte

•

dir8

→

dir=dir8

•

dir9

→

dir=dir9 >> 1

•

dir10

→

dir=dir10 >> 2

Table A.2-14 Resource Instructions (2 Instructions)

Mnemonic

Format

CYC

FLAG

NZVC

Operation

Remarks

LDRES @Ri+, #u4

– – – –

(Ri)

→

resource u4

Ri + =4

u4: Channel number

STRES #u4, @Ri+

– – – –

Resource u4

→

(Ri)

Ri + =4

u4: Channel number

Table A.2-15 Coprocessor Instructions (4 Instructions)

Mnemonic

Format

CYC

FLAG

NZVC

Operation

Remarks

COPOP   #u4, #CC, CRj, CRi
COPLD    #u4, #CC, Rj,  CRi
COPST   #u4, #CC, CRj, Ri
COPSV   #u4, #CC, CRj, Ri

E
E
E
E

9F-C

9F-D

9F-E

9F-F

2+a

1+2a
1+2a
1+2a

– – – –
– – – –
– – – –
– – – –

Designates operation
Rj

→

CRi

CRj

→

CRj

→

No error trap generated

Summary of Contents for FR Family

Page 1: ...FUJITSU SEMICONDUCTOR CONTROLLER MANUAL FR Family 32 BIT MICROCONTROLLER INSTRUCTION MANUAL CM71 00101 5E ...

Page 2: ......

Page 3: ...FUJITSU LIMITED FR Family 32 BIT MICROCONTROLLER INSTRUCTION MANUAL ...

Page 4: ......

Page 5: ...ith FR family assemblers and describes the various instructions used with FR family Be sure to read the entire manual carefully Note that the use or non use of coprocessors as well as coprocessor specifications depends on the functions of individual FR family products For information about coprocessor specifications users should consult the coprocessor section of the product documentation Also for...

Page 6: ...AND EIT PROCESSING This chapter describes reset and EIT processing in the FR family CPU CHAPTER 5 PRECAUTIONARY INFORMATION FOR THE FR FAMILY CPU This chapter presents precautionary information related to the use of the FR family CPU CHAPTER 6 INSTRUCTION OVERVIEW This chapter presents an overview of the instructions used with the FR family CPU CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS This chapte...

Page 7: ...bed in this document are designed developed and manufactured as contemplated for general use including without limitation ordinary industrial use general office use personal use and household use but are not designed developed and manufactured as contemplated 1 for use accompanying fatal risks or dangers that unless extremely high safety is secured could have a serious effect to the public and cou...

Page 8: ...iv ...

Page 9: ...ted Registers 17 3 3 1 Program Counter PC 18 3 3 2 Program Status PS 19 3 3 3 Table Base Register TBR 23 3 3 4 Return Pointer RP 25 3 3 5 System Stack Pointer SSP User Stack Pointer USP 27 3 3 6 Multiplication Division Register MD 29 CHAPTER 4 RESET AND EIT PROCESSING 31 4 1 Reset Processing 33 4 2 Basic Operations in EIT Processing 34 4 3 Interrupts 37 4 3 1 User Interrupts 38 4 3 2 Non maskable ...

Page 10: ...3 CMP2 Compare Immediate Data and Destination Register 84 7 14 AND And Word Data of Source Register to Destination Register 85 7 15 AND And Word Data of Source Register to Data in Memory 86 7 16 ANDH And Half word Data of Source Register to Data in Memory 88 7 17 ANDB And Byte Data of Source Register to Data in Memory 90 7 18 OR Or Word Data of Source Register to Destination Register 92 7 19 OR Or...

Page 11: ...ster 150 7 57 LD Load Word Data in Memory to Register 151 7 58 LD Load Word Data in Memory to Register 152 7 59 LD Load Word Data in Memory to Register 153 7 60 LD Load Word Data in Memory to Register 154 7 61 LD Load Word Data in Memory to Register 155 7 62 LD Load Word Data in Memory to Program Status Register 157 7 63 LDUH Load Half word Data in Memory to Register 159 7 64 LDUH Load Half word D...

Page 12: ... DMOV Move Word Data from Direct Address to Pre decrement Register Indirect Address 211 7 105 DMOV Move Word Data from Post Increment Register Indirect Address to Direct Address 213 7 106 DMOVH Move Half word Data from Direct Address to Register 215 7 107 DMOVH Move Half word Data from Register to Direct Address 216 7 108 DMOVH Move Half word Data from Direct Address to Post Increment Register Ind...

Page 13: ...XTUH Unsigned Extend from Byte Data to Word Data 245 7 129 LDM0 Load Multiple Registers 246 7 130 LDM1 Load Multiple Registers 248 7 131 STM0 Store Multiple Registers 250 7 132 STM1 Store Multiple Registers 252 7 133 ENTER Enter Function 254 7 134 LEAVE Leave Function 256 7 135 XCHB Exchange Byte Data 258 APPENDIX 261 APPENDIX A Instruction Lists 262 A 1 Symbols Used in Instruction Lists 263 A 2 I...

Page 14: ...x ...

Page 15: ...nd therefore incremented and therefore 20 Figure 3 3 4 ILM Register Functions is changed A line from ILM to COMP is added 23 Figure 3 3 7 Sample of Table Base Register TBR Operation is changed 31 bit31 27 System Stack Pointer SSP User Stack Pointer USP is changed ST R13 R15 ST R13 R15 The title of Figure 3 3 12 Example of Stack Pointer Operation in Execution of Instruction ST R13 R15 when S Flag 0...

Page 16: ... operand 1 and operand 2 with the results stored at operand 2 is changed The position of R2 is changed 72 7 1 ADD Add Word Data of Source Register to Destination Register is changed Instruction bit pattern 1010 0110 0010 0011 is added 75 7 4 ADDC Add Word Data of Source Register and Carry Bit to Destination Register is changed Instruction bit pattern 1010 0111 0010 0011 is added 79 7 8 SUB Subtrac...

Page 17: ...ce Register to Data in Memory is changed Instruction bit pattern 1001 1100 0010 0011 is added 103 7 24 EORH Exclusive Or Half word Data of Source Register to Data in Memory is changed Instruction bit pattern 1001 1101 0010 0011 is added 105 7 25 EORB Exclusive Or Byte Data of Source Register to Data in Memory is changed Instruction bit pattern 1001 1110 0010 0011 is added 121 7 34 MUL Multiply Wor...

Page 18: ...on bit pattern 1100 0010 0001 0011 is added 150 7 56 LD Load Word Data in Memory to Register is changed Instruction bit pattern 0000 0100 0010 0011 is added 151 7 57 LD Load Word Data in Memory to Register is changed Instruction bit pattern 0000 0000 0010 0011 is added 153 7 59 LD Load Word Data in Memory to Register is changed o4 u4 154 7 60 LD Load Word Data in Memory to Register is changed Inst...

Page 19: ...n Register to Memory is changed Instruction bit pattern 0001 0001 0010 0011 is added 175 7 79 STB Store Byte Data in Register to Memory is changed Instruction bit pattern 0001 0110 0010 0011 is added 176 7 80 STB Store Byte Data in Register to Memory is changed Instruction bit pattern 0001 0010 0010 0011 is added 178 7 82 MOV Move Word Data in Source Register to Destination Register is changed Ins...

Page 20: ...upt is changed Instruction bit pattern 0001 1111 0010 0000 is added 191 7 92 INTE Software Interrupt for Emulator is changed Instruction bit pattern 1001 1111 0011 0000 is added 192 7 93 RETI Return from Interrupt is changed D2 D1 S 193 7 93 RETI Return from Interrupt is changed Instruction bit pattern 1001 0111 0011 0000 is added 194 7 94 Bcc Branch Relative if Condition Satisfied is changed exte...

Page 21: ... LDI 8 255 R1 Instruction placed in delay slot label BHI D instruction address 50H 7 99 Bcc D Branch Relative if Condition Satisfied is changed Instruction bit pattern 1111 1111 0010 1000 is changed 227 7 114 LDRES Load Word Data in Memory to Resource is changed Instruction bit pattern 1011 1100 1000 0010 is added 228 7 115 STRES Store Word Data in Resource to Memory is changed Instruction bit pat...

Page 22: ...gn Extend from Byte Data to Word Data is changed Instruction bit pattern 1001 0111 1001 0001 is changed 244 7 127 EXTSH Sign Extend from Byte Data to Word Data is changed Instruction bit pattern 1001 0111 1010 0001 is added 245 7 128 EXTUH Unsigned Extend from Byte Data to Word Data is changed Instruction bit pattern 1001 0111 1011 0001 is added 255 7 133 ENTER Enter Function is changed XXXX XXXX ...

Page 23: ...d Symbols in Mnemonic and Operation Columns is changed Note Data from 0x80000000H to 1 is handled as data from 0x80000000H to 0xFFFFFFFFH is deleted 263 A 1 Symbols Used in Instruction Lists is changed Symbols in Mnemonic and Operation Columns is changed Ri Ri Rj Symbols in Operation Column is changed indicates indirect addressing which values reading or loading from to the memory address where th...

Page 24: ...16 Ri Ri u4 16 Ri Ri u4 16 Ri 272 Table A 2 13 Direct Addressing Instructions 14 Instructions is changed disp8 dir8 disp9 dir9 disp10 dir10 273 Table A 2 16 Other Instructions 16 Instructions is changed i8 u8 276 Table B 2 1 E Format is changed Undefined is added Page Changes For details refer to main body ...

Page 25: ...W This chapter describes the features of the FR FAMILY CPU core and provides sample configurations 1 1 Features of the FR Family CPU Core 1 2 Sample Configuration of an FR Family Device 1 3 Sample Configuration of the FR Family CPU ...

Page 26: ...purpose register architecture Linear space for 32 bit 4 Gbytes addressing 16 bit fixed instruction length excluding immediate data coprocessor instructions 5 stage pipeline configuration for basic instructions one instruction one cycle execution 32 bit by 32 bit computation enables completion of multiplication instructions within five cycles Stepwise division instructions enable 32 bit 32 bit divi...

Page 27: ...an example of the configuration of an FR family device Sample Configuration of an FR Family Device Figure 1 2 1 Sample Configuration of an FR Family Device FR family CPU Low speed peripherals Low speed peripherals Low speed peripherals Low speed peripherals Internal bus interface Integrated bus User bus interface General purpose port Mandatory Standard in all models Option Not included in some mod...

Page 28: ... Figure 1 3 1 shows a sample configuration of an FR family CPU Sample Configuration of the FR Family CPU Figure 1 3 1 Sample Configuration of the FR Family CPU Instruction data Instruction sequencer Instruction decoder Bypass interlock Wait cancel control Exception processing Interrupt NMI Wait bus control Internal bus Internal bus Internal bus Data Data address Instruction address Multiplier 32 x...

Page 29: ... This chapter describes memory space in the FR family CPU Memory architecture includes the allocation of memory space as well as methods used to access memory 2 1 FR Family Memory Space 2 2 Bit Order and Byte Order 2 3 Word Alignment ...

Page 30: ...ace in the FR family For a detailed description of the direct address area see Section 2 1 1 Direct Address Area and for the vector table area see Section 2 1 2 Vector Table Area Figure 2 1 1 FR Family Memory Space Unused Vector Table Area Unused vector table area is available for use as program or data area 0000 0000H 0000 0100H 0000 0200H 0000 0400H 000F FC00H 0010 0000H FFFF FFFFH Byte data Hal...

Page 31: ...se of Operand Information Contained in Instructions The 8 bit address information contained in the instruction has the following significance In byte data Value represents the lower 8 bits of the address In half word data Value is doubled and used as the lower 9 bits of the address In word data Value is multiplied by 4 and used as the lower 10 bits of the address Figure 2 1 2 shows the relationshi...

Page 32: ...r exception processing interrupt processing and trap processing The table base register TBR can be rewritten to allocate this area to any desired location within word alignment limitations Figure 2 1 3 Relation between Table Base Register TBR and Vector Table Addresses 0000 0000H FFFF FFFFH TBR 1 Kbyte Number Offset from TBR EIT source FFH FEH FDH FCH 00H 000H 004H 008H 00CH 3FCH Entry address for...

Page 33: ...le Area Offset from TBR Number hex Model dependent EIT value description Remarks 000H FFH No INT 0FFH 004H FEH No INT 0FEH 2F8H 41H No System reserved Do not use 2FCH 40H No System reserved 33CH 30H No INT 030H 340H 2FH Yes INT 02FH or IR31 Values will increase towards higher limits when using over 32 source extension Refer to User s Manual for each model 344H 2EH Yes INT 02EH or IR30 3BCH 10H Yes...

Page 34: ...eral purpose register is that the larger numbers are placed in the vicinity of the MSB while the smaller numbers are near the LSB Byte order configuration requires the upper data to be placed in the smaller address memory while the lower data are placed in the larger address memory Figure 2 2 1 illustrates the bit order and byte order in the FR family Figure 2 2 1 Bit Order and Byte Order Bit orde...

Page 35: ...address will explicitly be read as 0 Half word data Data must be assigned to addresses that are multiples of 2 Even if the operand value is not a multiple of 2 the lowest bit of the memory address will explicitly be read as 0 Byte data There are no restrictions on addresses The forced setting of some bits to 0 during memory access for word data and half word data is applied after the computation o...

Page 36: ...12 CHAPTER 2 MEMORY ARCHITECTURE ...

Page 37: ...13 CHAPTER 3 REGISTER DESCRIPTIONS This chapter describes the registers used in the FR family CPU 3 1 FR Family Register Configuration 3 2 General purpose Registers 3 3 Dedicated Registers ...

Page 38: ...e 3 1 1 shows the configuration of registers in FR family devices FR Family Register Configuration Figure 3 1 1 FR Family Register Configuration 64 bits 32 bits Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined General purpose registers Dedicated registers MD R0 R1 R2 R3 R12 R13 R14 R15 PC PS TBR RP SSP USP Accumulator AC Frame pointe...

Page 39: ...tion Figure 3 2 1 shows the configuration of a general purpose register Figure 3 2 1 General purpose Register Configuration Special Uses of General purpose Registers In addition to functioning as general purpose registers R13 R14 and R15 have the following special uses with certain types of instructions R13 Accumulator AC Base address register for load store to memory instructions Example LD R13 R...

Page 40: ...Pointer The R15 functions physically as either the system stack pointer SSP or user stack pointer USP for the general purpose registers When the notation R15 is used in an instruction this register will function as the USP if the S flag in the condition code register CCR section of the program status register PS is set to 1 The R15 register will function as the SSP if the S flag is set to 0 Ensure...

Page 41: ...rogram Counter PC through 3 3 6 Multiplication Division Register MD 32 bit Dedicated Registers Program counter PC Program status PS Table base register TBR Return pointer RP System stack pointer SSP User stack pointer USP 64 bit Dedicated Register Multiplication Division Register MD Figure 3 3 1 shows the configuration of the dedicated registers Figure 3 3 1 Dedicated Register Configuration 64 bit...

Page 42: ...gram counter is read as 0 by the internal circuits in the FR family device Even if 1 is written to this bit it will be treated as 0 for addressing purposes A physical cell does exist for this bit however the lowest bit value remains 0 even when the program address value is incremented and therefore the value of this bit is always 0 except following a branching operation Because the internal circui...

Page 43: ...ansion Write values should always be 0 The read value of these bits is always 0 Interrupt Level Mask Register ILM Bit 20 to bit 16 Bit Configuration of the ILM Register Figure 3 3 3 Bit Configuration of the ILM Register ILM Functions The ILM determines the level of interrupt that will be accepted Whenever the I flag in the CCR register is 1 the contents of this register are compared to the level o...

Page 44: ...CR Functions Bits D1 D0 Bits D1 D0 are used for intermediate data in stepwise division calculations This register is used to assure resumption of division calculations when the stepwise division program is interrupted during processing If changes are made to the contents of this register during division processing the results of the division are not assured T bit The T bit is a step trace trap fla...

Page 45: ...ndicates negative Z Flag This flag indicates whether the results of a calculations are zero The value 0 indicates a non zero value and 1 indicates a zero value V Flag This flag indicates that an overflow occurred when the results of a calculation are expressed in two s complement form The value 0 indicates no overflow and 1 indicates an overflow C Flag This flag indicates whether a carry or borrow...

Page 46: ...step execution is implemented or c a break occurs in a data event or emulator menu due to a command just before DIV0U DIV0S commands the following operation may be implemented 1 D0 and D1 flags are changed first 2 EIT process routine user interrupt NMI or emulator is executed 3 Returning from EIT DIV0U DIV0S commands are executed and D0 and D1 flags are set to the same value in 1 When a user inter...

Page 47: ...ned by the sum of the contents of this register and the vector offset corresponding to the EIT operation Figure 3 3 7 shows an example of the operation of the table base register Figure 3 3 7 Sample of Table Base Register TBR Operation Vector correspondence table Vector no Vector offset Timer interrupt 11H 3B8H bit31 0 EAddr0 EAddr1 EAddr2 EAddr3 EAddr0 EAddr1 EAddr2 EAddr3 PC TBR 87654123H Adder ...

Page 48: ...r access is in word units the lower two bits of the resulting address value are explicitly read as 0 Vector Table Layout Vector table layout can be realized in word 32 bits units Initial Values in Table Base Register After a reset the initial value is 000FFC00H Precautions Related to the Table Base Register The TBR should not be assigned values greater than FFFFFC00H If values higher than this are...

Page 49: ...ed from the RP pointer to the PC counter by execution of a RET instruction Figure 3 3 9 shows a sample operation of the RP pointer in the execution of a CALL instruction with no delay slot and Figure 3 3 10 shows a sample operation of the RP pointer in the execution of a RET instruction Figure 3 3 9 Sample Operation of RP in Execution of a CALL Instruction with No Delay Slot Figure 3 3 10 Sample O...

Page 50: ...re 3 3 11 Return Pointer Bit Configuration Return Pointer Functions Return Pointer in Multiple CALL Instructions Because the RP does not have a stack configuration it is necessary to first execute a save when calling one subroutine from another subroutine Initial Value of Return Pointer The initial value is undefined Bit no RP 31 00 ...

Page 51: ...egister multi transfer instructions R15 is used as an indirect register by the SSP when the S flag in the condition code register CCR is 0 and the USP when the S flag is 1 Also when an EIT event occurs the program counter PC and program status PS values are saved to the stack area designated by the SSP regardless of the value of the S flag at that time Figure 3 3 12 shows an example of stack point...

Page 52: ...nt post increment counting Stack Pointer Initial Value The SSP has the initial value 00000000H The USP initial value is undefined Recovery from EIT handler When RETI instruction is used for recovery from an EIT handler it is necessary to set the S flag to 0 and select the system stack For further details see Recovery from EIT handler of 4 2 Basic Operations in EIT Processing Memory space Before ex...

Page 53: ...rations the dividend must first be placed in the lower 32 bits of the MD beforehand Then as the division process is executed the remainder is placed in the higher 32 bits of the MD and the quotient in the lower 32 bits Figure 3 3 15 shows an example of the use of the MD in multiplication and Figure 3 3 16 shows an example of division Figure 3 3 15 Sample Operation of MD in Multiplication Figure 3 ...

Page 54: ...ns of the MD Storing Results of Multiplication and Division The results of multiplication operations are stored in the MDH higher 32 bits and MDL lower 32 bits registers The results of division are stored as follows quotients in the 32 bit MDL register and remainders in the 32 bit MDH register Initial Value of the MD The initial value is undefined Bit no MDH MDL 31 00 ...

Page 55: ...rn to the prior program by use of the RETI instruction EIT processing operates in essentially the same manner for exceptions interrupts and traps with the following minor differences Interrupts originate independently of the instruction sequence Processing is designed to resume from the instruction immediately following the acceptance of the interrupt Exceptions are related to the instruction sequ...

Page 56: ...32 CHAPTER 4 RESET AND EIT PROCESSING 4 1 Reset Processing 4 2 Basic Operations in EIT Processing 4 3 Interrupts 4 4 Exception Processing 4 5 Traps 4 6 Priority Levels ...

Page 57: ... the reset is canceled the CPU initializes all internal registers and starts execution beginning with the program indicated by the new value of the program counter PC Initialization of CPU Internal Register Values at Reset When a reset is applied the FR family CPU initializes internal registers to the following values PC Word data stored at address 000FFFFCH ILM 01111B T Flag 0 trace OFF I Flag 0 ...

Page 58: ...nts of the old program counter PC and the old program status PS are saved to the stack area designated by the system stack pointer SSP 3 After the processing flow is completed the presence of new EIT sources is determined Figure 4 2 1 shows the operations in the EIT processing sequence Figure 4 2 1 EIT Processing Sequence Note For a description of pipeline operations see Section 5 1 Pipeline Opera...

Page 59: ...nstruction or data area Figure 4 2 2 shows the structure of the vector table Example of 32 source Figure 4 2 2 Vector Table Configuration TBR 00000000H FFFFFFFFH 1 Kbyte Memory space Offset Vector no Description 000H 004H 008H 33CH 340H 344H 3BCH 3C0H 3C4H 3C8H 3CCH 3D0H 3F8H 3FCH FFH FEH FDH 30H 2FH 2EH 10H 0FH 0EH 0DH 0CH 0BH 01H 00H INT 0FFH INT 0FEH INT 0FDH INT 030H INT 02FH or IR31 INT 02EH ...

Page 60: ...recovery it is required that all the contents of the CPU register are saved Ensure that the PC and PS values in the stack are not overwritten unless necessary because those values saved in the stack at the occurrence of EIT are recovered from the stack during the recovery sequence using the RETI instruction Be sure to set the S flag to 0 when the RETI instruction is executed Memory space Immediate...

Page 61: ...e interrupt will be executed to completion however any instructions loaded in the pipeline after the interrupt will be canceled After completion of interrupt processing therefore execution will return to the next instruction following the generation of the interrupt signal Sources of Interrupts There are two types of interrupt sources User interrupts See Section 4 3 1 User Interrupts Non maskable ...

Page 62: ...cceptance of User Interrupt Requests The CPU accepts user interrupts when the following conditions are met The peripheral circuit is operating and generates an interrupt request The interrupt enable bit in the peripheral circuit s control register is set to enable The value of the interrupt request ICR 1 is lower than the value of the ILM 2 setting The I flag is set to 1 1 ICR Interrupt Control Re...

Page 63: ...sing sequence saves PC values to the system stack representing the addresses of canceled instructions How to Use User Interrupts The following programming steps must be set up to enable the use of user interrupts Figure 4 3 1 illustrates the use of user interrupts Figure 4 3 1 How to Use User Interrupts 1 Enter values in the interrupt vector table defined as data 2 Set up the SSP values 3 Set up t...

Page 64: ...pt Requests The FR family CPU will accept an NMI request when the following conditions are met If NMI Pin Input is Active In normal operation Detection of a negative signal edge In stop mode Detection of an L level signal If the ILM Value is Greater than 15 Operation Following Acceptance of a Non maskable Interrupt When an NMI is accepted the following operations take place 1 The contents of the P...

Page 65: ...ill be canceled and will not be processed after the interrupt The EIT processing sequence saves PC values to the system stack representing the addresses of canceled instructions How to Use Non maskable Interrupts The following programming steps must be set up to enable the use of NMI 1 Enter values in the interrupt vector table defined as data 2 Set up the SSP values 3 Set up TBR values 4 Set up t...

Page 66: ...ons are processed by first saving the necessary information to resume the currently executing instruction and then starting the processing routine corresponding to the type of exception that has occurred Branching to the exception processing routine takes place before execution of the instruction that has caused the exception The address of the instruction in which the exception occurs becomes the...

Page 67: ...C4H is stored in the program counter PC Time to Start of Undefined Instruction Exception Processing The time required to start exception processing is 7 cycles PC Values Saved for Undefined Instruction Exceptions The address saved to the system stack as a PC value represents the instruction itself that caused the undefined instruction exception When a RETI instruction is executed the contents of t...

Page 68: ... processing from the next instruction in the sequence and then starting the processing routine corresponding to the type of trap that has occurred Branching to the exception processing routine takes place after execution of the instruction that has caused the exception The address of the instruction in which the exception occurs becomes the program counter PC value that is saved to the stack Sourc...

Page 69: ...struction is saved to the system stack 3 The value of the system stack pointer SSP is reduced by 8 4 The value 0 is written to the I flag in the condition code register CCR in the PS 5 The value 0 is written to the S flag in the CCR in the PS 6 The value TBR 3FCH 4 u8 is stored in PC Time to Start of Trap Processing for INT Instructions The time required to start trap processing is 6 cycles PC Val...

Page 70: ...stack 3 The value of the system stack pointer SSP is reduced by 8 4 The value 4 is written to the interrupt level mask register ILM in the PS 5 The value 0 is written to the S flag in the CCR in the PS 6 The value TBR 3D8H is stored in PC Time to Start of Trap Processing for INTE Instructions The time required to start trap processing is 6 cycles PC Values Saved for INTE Instruction Execution The ...

Page 71: ...d when the following conditions are met The T flag in the SCR in the PS is set to 1 The currently executing instruction is not a delayed branching instruction The CPU is not processing an INTE instruction or a step trace trap processing routine Step Trace Trap Operation When a step trace trap is generated the following operations take place 1 The contents of the program status PS are saved to the ...

Page 72: ...cessor Not Found Trap Operation When a coprocessor not found trap is generated the following operations take place 1 The contents of the program status PS are saved to the system stack 2 The address of the next instruction is saved to the system stack 3 The value of the system stack pointer SSP is reduced by 8 4 The value 0 is written to the S flag in the condition code register CCR in the PS 5 Th...

Page 73: ...or operation A COPOP COPLD COPST instruction is executed involving the same coprocessor Coprocessor Error Trap Operation When a coprocessor error trap is generated the following operations take place 1 The contents of the program status PS are saved to the system stack 2 The address of the next instruction is saved to the system stack 3 The value of the system stack pointer SSP is reduced by 8 4 T...

Page 74: ...essor errors but acts to clear the internal error Note that the error information is retained in the status information that is saved If the saved status information is returned to the coprocessor at the time of re dispatching to the former task the hidden error condition is cleared and the CPU is notified when the next coprocessor instruction is executed Figure 4 5 1 shows an example in which not...

Page 75: ...ed by the EIT processing handler may not match the priority of the requests Priority of Simultaneous Occurrences The FR family uses a hardware function to determine the priority of acceptance of EIT requests Table 4 6 1 shows the priority levels of EIT requests Table 4 6 1 Priority of EIT Requests Priority Source Masking of other sources 1 Reset Other sources discarded 2 Undefined instruction exce...

Page 76: ...stepwise only the step trace EIT is generated Sources related to the INTE instruction will be ignored Table 4 6 2 Priority of Execution of EIT Handlers Priority Source Masking of other sources 1 Reset Other sources discarded 2 Undefined instruction exception Other sources disabled 3 Step trace trap ILM 4 4 INTE instruction ILM 4 5 NMI ILM 15 6 INT instruction I flag 0 7 User interrupt ILM level of...

Page 77: ...ON FOR THE FR FAMILY CPU This chapter presents precautionary information related to the use of the FR family CPU 5 1 Pipeline Operation 5 2 Pipeline Operation and Interrupt Processing 5 3 Register Hazards 5 4 Delayed Branching Processing ...

Page 78: ...re 5 1 1 This is referred to as five stage pipeline processing IF Load instruction ID Interpret instruction EX Execute instruction MA Memory access WB Write to register Figure 5 1 1 Example of Pipeline Operation in the FR Family CPU Processes occurring in each 1 cycle in the above example 1 Load instruction LD R10 R1 2 Interpret instruction LD R10 R1 Load instruction LD R11 R2 3 Execute instructio...

Page 79: ...upt processing the interrupt request will no longer be effective Note that this type of condition does not occur in exception or trap processing Figure 5 2 1 Example Interrupt Accepted and Deleted Causing Mismatched Pipeline Conditions Conditions that Are Actually Generated The following processing conditions may cause an interrupt to be deleted after acceptance A program that clears interrupt sou...

Page 80: ...1 by the previous instruction As a result the old value at R1 will be read instead of the new value Figure 5 3 1 Example of a Register Hazard Register Bypassing Even when a register hazard does occur it is possible to process instructions without operating delays if the data intended for the register to be accessed can be extricated from the preceding instruction This type of data transfer process...

Page 81: ...e of Interlocking Interlocking Produced by Reference to R15 and General purpose Registers after Changing the S Flag The general purpose register R15 is designed to function as either the system stack pointer SSP or user stack pointer USP For this reason the FR family CPU is designed to automatically generate an interlock whenever a change to the S flag in the condition code register CCR in the pro...

Page 82: ... not satisfied are described in Section 5 4 1 Processing Non delayed Branching Instructions Overview of Branching with Delayed Branching Instructions An instruction immediately following a branching instruction will already be loaded by the CPU by the time the branching instruction is executed This position is called the delay slot A delayed branching instruction is a branching instruction that ex...

Page 83: ...4 Ri MUL Rj Ri MULU Rj Ri MULH Rj Ri MULUH Rj Ri LD R15 PS LDM0 reglist LDM1 reglist STM0 reglist STM1 reglist ENTER u10 XCHB Rj Ri DMOV dir10 R13 DMOV R13 dir10 DMOV dir10 R15 DMOV R15 dir10 DMOVH dir9 R13 DMOVH R13 dir9 DMOVB dir8 R13 DMOVB R13 dir8 Restrictions on Interrupts during Processing of Delayed Branching Instructions EIT processing is not accepted during execution of delayed branching ...

Page 84: ...gure 5 4 2 shows an example of processing a non delayed branching instruction when branching conditions are not satisfied In this example the instruction ST R2 R12 which immediately follows the branching instruction has entered the pipeline operation before the fetching of the branch destination instruction and is executed without being canceled Because instructions are executed without branching ...

Page 85: ...nch destination instruction ST R2 R13 and therefore the apparent order of processing is inverted Figure 5 4 3 Example Processing a Delayed Branching Instruction Branching Condition Satisfied Figure 5 4 4 shows an example of processing a delayed branching instruction when branching conditions are not satisfied In this example the delay slot instruction ST R2 R12 is executed without being canceled A...

Page 86: ...THE FR FAMILY CPU Examples of Programing Delayed Branching Instructions An example of programing a delayed branching instruction is shown below LD R10 R1 LD R11 R2 ADD R1 R3 BNE D TestOK ST R2 R12 ADD 4 R12 not satisfy TestOK satisfied ST R2 R13 ...

Page 87: ...family CPU All FR family CPU instructions are in 16 bit fixed length format except for immediate data transfer instructions which may exceed 16 bits in length This format enables the creation of a compact object code and smoother pipeline processing 6 1 Instruction Formats 6 2 Instruction Notation Formats ...

Page 88: ...elation between general purpose register numbers and field bit pattern values MSB LSB 16bits 8bits 8bits 4bits 4bits 4bits 4bits OP OP Rj Ri 8bits 4bits 4bits OP u4 m4 i4 Ri 8bits 8bits OP u8 rel8 dir rlist 12bits 4bits OP Ri Rs 5bits 11bits OP rel11 Ri i8 o8 TYPE A TYPE B TYPE C TYPE D TYPE F TYPE E Table 6 1 1 General purpose Register Numbers and Field Bit Pattern Values Ri Rj Register Ri Rj Reg...

Page 89: ...Numbers and Field Bit Pattern Values Rs Register Rs Register Rs Register Rs Register 0000 TBR 0100 MDH 1000 reserved 1100 reserved 0001 RP 0101 MDL 1001 reserved 1101 reserved 0010 SSP 0110 reserved 1010 reserved 1110 reserved 0011 USP 0111 reserved 1011 reserved 1111 reserved Note Bit patterns marked reserved are reserved for system use Proper operation is not assured if these patterns are used i...

Page 90: ...nd use operand 1 Operations are designated by a mnemonic Instruction Notation Formats FR family CPU instructions are written in the following 3 notation formats Calculations are designated by a mnemonic placed between operand 1 and operand 2 with the results stored at operand 2 Mnemonic Operand 1 Operand 2 Example ADD R1 R2 R1 R2 R2 Operations are designated by a mnemonic and use operand 1 Mnemoni...

Page 91: ...y Divide Instructions Shift Instructions Immediate Data Transfer Instructions Memory Load Instructions Memory Store Instructions Inter register Transfer Instructions Dedicated Register Transfer Instructions Non delayed Branching Instructions Delayed Branching Instructions Direct Addressing Instructions Resource Instructions Coprocessor Instructions Other Instructions 7 1 ADD Add Word Data of Sourc...

Page 92: ...Or Word Data of Source Register to Data in Memory 7 20 ORH Or Half word Data of Source Register to Data in Memory 7 21 ORB Or Byte Data of Source Register to Data in Memory 7 22 EOR Exclusive Or Word Data of Source Register to Destination Register 7 23 EOR Exclusive Or Word Data of Source Register to Data in Memory 7 24 EORH Exclusive Or Half word Data of Source Register to Data in Memory 7 25 EOR...

Page 93: ...ter 7 56 LD Load Word Data in Memory to Register 7 57 LD Load Word Data in Memory to Register 7 58 LD Load Word Data in Memory to Register 7 59 LD Load Word Data in Memory to Register 7 60 LD Load Word Data in Memory to Register 7 61 LD Load Word Data in Memory to Register 7 62 LD Load Word Data in Memory to Program Status Register 7 63 LDUH Load Half word Data in Memory to Register 7 64 LDUH Load...

Page 94: ...turn from Interrupt 7 94 Bcc Branch Relative if Condition Satisfied 7 95 JMP D Jump 7 96 CALL D Call Subroutine 7 97 CALL D Call Subroutine 7 98 RET D Return from Subroutine 7 99 Bcc D Branch Relative if Condition Satisfied 7 100 DMOV Move Word Data from Direct Address to Register 7 101 DMOV Move Word Data from Register to Direct Address 7 102 DMOV Move Word Data from Direct Address to Post Increm...

Page 95: ...essor Register to Register 7 119 COPSV Save 32 bit Data from Coprocessor Register to Register 7 120 NOP No Operation 7 121 ANDCCR And Condition Code Register and Immediate Data 7 122 ORCCR Or Condition Code Register and Immediate Data 7 123 STILM Set Immediate Data to Interrupt Level Mask Register 7 124 ADDSP Add Stack Pointer and Immediate Data 7 125 EXTSB Sign Extend from Byte Data to Word Data ...

Page 96: ...eared when the MSB is 0 Z Set when the operation result is 0 cleared otherwise V Set when an overflow has occurred as a result of the operation cleared otherwise C Set when a carry has occurred as a result of the operation cleared otherwise Execution cycles 1 cycle Instruction format Example ADD R2 R3 N Z V C C C C C MSB LSB 1 0 1 0 0 1 1 0 Rj Ri R2 R3 1 2 3 4 5 6 7 8 8 7 6 5 4 3 2 1 N Z V C CCR R...

Page 97: ... Set when the MSB of the operation result is 1 cleared when the MSB is 0 Z Set when the operation result is 0 cleared otherwise V Set when an overflow has occurred as a result of the operation cleared otherwise C Set when a carry has occurred as a result of the operation cleared otherwise Execution cycles 1 cycle Instruction format Example ADD 2 R3 N Z V C C C C C MSB LSB 1 0 1 0 0 1 0 0 i4 Ri R3 ...

Page 98: ...sembler format ADD2 i4 Ri Operation Ri extn i4 Ri Flag change N Set when the MSB of the operation result is 1 cleared when the MSB is 0 Z Set when the operation result is 0 cleared otherwise V Set when an overflow has occurred as a result of the operation cleared otherwise C Set when a carry has occurred as a result of the operation cleared otherwise Execution cycles 1 cycle Instruction format Exa...

Page 99: ...he operation result is 1 cleared when the MSB is 0 Z Set when the operation result is 0 cleared otherwise V Set when an overflow has occurred as a result of the operation cleared otherwise C Set when a carry has occurred as a result of the operation cleared otherwise Execution cycles 1 cycle Instruction format Example ADDC R2 R3 N Z V C C C C C MSB LSB 1 0 1 0 0 1 1 1 Rj Ri R2 R3 1 2 3 4 5 6 7 8 8...

Page 100: ...rd Data of Source Register to Destination Register Assembler format ADDN Rj Ri Operation Ri Rj Ri Flag change N Z V and C Unchanged Execution cycles 1 cycle Instruction format Example ADDN R2 R3 N Z V C MSB LSB 1 0 1 0 0 0 1 0 Rj Ri R2 R3 1 2 3 4 5 6 7 8 8 7 6 5 4 3 2 1 N Z V C CCR R2 R3 CCR 0 0 0 0 N Z V C 0 0 0 0 9 9 9 9 9 9 9 9 1 2 3 4 5 6 7 8 Before execution After execution Instruction bit pa...

Page 101: ...o Ri without changing flag settings ADDN Add Immediate Data to Destination Register Assembler format ADDN i4 Ri Operation Ri extu i4 Ri Flag change N Z V and C Unchanged Execution cycles 1 cycle Instruction format Example ADDN 2 R3 N Z V C MSB LSB 1 0 1 0 0 0 0 0 i4 Ri R3 9 9 9 9 9 9 9 7 N Z V C CCR R3 CCR 0 0 0 0 N Z V C 0 0 0 0 9 9 9 9 9 9 9 9 Instruction bit pattern 1010 0000 0010 0011 Before e...

Page 102: ...i without changing flag settings ADDN2 Add Immediate Data to Destination Register Assembler format ADDN2 i4 Ri Operation Ri extn i4 Ri Flag change N Z V and C Unchanged Execution cycles 1 cycle Instruction format Example ADDN2 2 R3 N Z V C MSB LSB 1 0 1 0 0 0 0 1 i4 Ri R3 9 9 9 9 9 9 9 9 N Z V C CCR R3 CCR 0 0 0 0 N Z V C 0 0 0 0 9 9 9 9 9 9 9 7 Instruction bit pattern 1010 0001 1110 0011 Before e...

Page 103: ...result is 1 cleared when the MSB is 0 Z Set when the operation result is 0 cleared otherwise V Set when an overflow has occurred as a result of the operation cleared otherwise C Set when a borrow has occurred as a result of the operation cleared otherwise Execution cycles 1 cycle Instruction format Example SUB R2 R3 N Z V C C C C C MSB LSB 1 0 1 0 1 1 0 0 Rj Ri R2 R3 1 2 3 4 5 6 7 8 9 9 9 9 9 9 9 ...

Page 104: ...the MSB of the operation result is 1 cleared when the MSB is 0 Z Set when the operation result is 0 cleared otherwise V Set when an overflow has occurred as a result of the operation cleared otherwise C Set when a borrow has occurred as a result of the operation cleared otherwise Execution cycles 1 cycle Instruction format Example SUBC R2 R3 N Z V C C C C C MSB LSB 1 0 1 0 1 1 0 1 Rj Ri R2 R3 1 2 ...

Page 105: ...ubtract Word Data in Source Register from Destination Register Assembler format SUBN Rj Ri Operation Ri Rj Ri Flag change N Z V and C Unchanged Execution cycles 1 cycle Instruction format Example SUBN R2 R3 N Z V C MSB LSB 1 0 1 0 1 1 1 0 Rj Ri R2 R3 1 2 3 4 5 6 7 8 9 9 9 9 9 9 9 9 N Z V C CCR R2 R3 CCR 0 0 0 0 N Z V C 0 0 0 0 8 7 6 5 4 3 2 1 1 2 3 4 5 6 7 8 Before execution After execution Instru...

Page 106: ...e operation result is 1 cleared when the MSB is 0 Z Set when the operation result is 0 cleared otherwise V Set when an overflow has occurred as a result of the operation cleared otherwise C Set when a borrow has occurred as a result of the operation cleared otherwise Execution cycles 1 cycle Instruction format Example CMP R2 R3 N Z V C C C C C MSB LSB 1 0 1 0 1 0 1 0 Rj Ri R2 R3 1 2 3 4 5 6 7 8 1 ...

Page 107: ...peration Ri extu i4 Flag change N Set when the MSB of the operation result is 1 cleared when the MSB is 0 Z Set when the operation result is 0 cleared otherwise V Set when an overflow has occurred as a result of the operation cleared otherwise C Set when a carry has occurred as a result of the operation cleared otherwise Execution cycles 1 cycle Instruction format Example CMP 3 R3 N Z V C C C C C ...

Page 108: ... extn i4 Flag change N Set when the MSB of the operation result is 1 cleared when the MSB is 0 Z Set when the operation result is 0 cleared otherwise V Set when an overflow has occurred as a result of the operation cleared otherwise C Set when a carry has occurred as a result of the operation cleared otherwise Execution cycles 1 cycle Instruction format Example CMP2 3 R3 N Z V C C C C C MSB LSB 1 ...

Page 109: ...D Rj Ri Operation Ri and Rj Ri Flag change N Set when the MSB of the operation result is 1 cleared when the MSB is 0 Z Set when the operation result is 0 cleared otherwise V and C Unchanged Execution cycles 1 cycle Instruction format Example AND R2 R3 N Z V C C C MSB LSB 1 0 0 0 0 0 1 0 Rj Ri R2 R3 1 1 1 1 0 0 0 0 1 0 1 0 1 0 1 0 N Z V C CCR R2 R3 CCR 0 0 0 0 N Z V C 0 0 0 0 1 0 1 0 0 0 0 0 1 1 1 ...

Page 110: ...ll not accept hold requests between the memory read operation and the memory write operation of this request AND And Word Data of Source Register to Data in Memory Assembler format AND Rj Ri Operation Ri and Rj Ri Flag change N Set when the MSB of the operation result is 1 cleared when the MSB is 0 Z Set when the operation result is 0 cleared otherwise V and C Unchanged Execution cycles 1 2a cycle...

Page 111: ...345678 1234567C 1 1 1 1 0 0 0 0 1 2 3 4 5 6 7 8 N Z V C CCR R2 R3 R3 CCR 0 0 0 0 1 0 1 0 1 0 1 0 N Z V C 0 0 0 0 1 2 3 4 5 6 7 8 1 1 1 1 0 0 0 0 Memory 12345678 1234567C 1 0 1 0 0 0 0 0 Memory Before execution After execution Instruction bit pattern 1000 0100 0010 0011 ...

Page 112: ...ill not accept hold requests between the memory read operation and the memory write operation of this request ANDH And Half word Data of Source Register to Data in Memory Assembler format ANDH Rj Ri Operation Ri and Rj Ri Flag change N Set when the MSB bit 15 of the operation result is 1 cleared when the MSB is 0 Z Set when the operation result is 0 cleared otherwise V and C Unchanged Execution cy...

Page 113: ... R3 R2 12345678 1234567A 0 0 0 0 1 1 0 0 1 2 3 4 5 6 7 8 N Z V C CCR R2 R3 R3 CCR 0 0 0 0 1 0 1 0 N Z V C 0 0 0 0 1 2 3 4 5 6 7 8 0 0 0 0 1 1 0 0 Memory 12345678 1234567A 1 0 0 0 Memory Before execution After execution Instruction bit pattern 1000 0101 0010 0011 ...

Page 114: ...ot accept hold requests between the memory read operation and the memory write operation of this request ANDB And Byte Data of Source Register to Data in Memory Assembler format ANDB Rj Ri Operation Ri and Rj Ri Flag change N Set when the MSB bit 7 of the operation result is 1 cleared when the MSB is 0 Z Set when the operation result is 0 cleared otherwise V and C Unchanged Execution cycles 1 2a c...

Page 115: ...B R2 R3 R2 12345678 12345679 0 0 0 0 0 0 1 0 1 2 3 4 5 6 7 8 N Z V C CCR R2 R3 R3 CCR 0 0 0 0 1 1 N Z V C 0 0 0 0 1 2 3 4 5 6 7 8 0 0 0 0 0 0 1 0 12345678 12345679 1 0 Before execution After execution Memory Memory Instruction bit pattern 1000 0110 0010 0011 ...

Page 116: ...Rj Ri Operation Ri or Rj Ri Flag change N Set when the MSB of the operation result is 1 cleared when the MSB is 0 Z Set when the operation result is 0 cleared otherwise V and C Unchanged Execution cycles 1 cycle Instruction format Example OR R2 R3 N Z V C C C MSB LSB 1 0 0 1 0 0 1 0 Rj Ri R2 R3 1 1 1 1 0 0 0 0 1 0 1 0 1 0 1 0 N Z V C CCR R2 R3 CCR 0 0 0 0 N Z V C 0 0 0 0 1 1 1 1 1 0 1 0 1 1 1 1 0 ...

Page 117: ...ll not accept hold requests between the memory read operation and the memory write operation of this request OR Or Word Data of Source Register to Data in Memory Assembler format OR Rj Ri Operation Ri or Rj Ri Flag change N Set when the MSB of the operation result is 1 cleared when the MSB is 0 Z Set when the operation result is 0 cleared otherwise V and C Unchanged Execution cycles 1 2a cycles In...

Page 118: ...345678 1234567C 1 1 1 1 0 0 0 0 1 2 3 4 5 6 7 8 N Z V C CCR R2 R3 R3 CCR 0 0 0 0 1 0 1 0 1 0 1 0 N Z V C 0 0 0 0 1 2 3 4 5 6 7 8 1 1 1 1 0 0 0 0 Memory 12345678 1234567C 1 1 1 1 1 0 1 0 Memory Before execution After execution Instruction bit pattern 1001 0100 0010 0011 ...

Page 119: ...ill not accept hold requests between the memory read operation and the memory write operation of this request ORH Or Half word Data of Source Register to Data in Memory Assembler format ORH Rj Ri Operation Ri or Rj Ri Flag change N Set when the MSB bit 15 of the operation result is 1 cleared when the MSB is 0 Z Set when the operation result is 0 cleared otherwise V and C Unchanged Execution cycles...

Page 120: ...R3 R2 12345678 1234567A 0 0 0 0 1 1 0 0 1 2 3 4 5 6 7 8 N Z V C CCR R2 R3 R3 CCR 0 0 0 0 1 0 1 0 N Z V C 0 0 0 0 1 2 3 4 5 6 7 8 0 0 0 0 1 1 0 0 12345678 1234567A 1 1 1 0 Memory Memory Before execution After execution Instruction bit pattern 1001 0101 0010 0011 ...

Page 121: ...not accept hold requests between the memory read operation and the memory write operation of this request ORB Or Byte Data of Source Register to Data in Memory Assembler format ORB Rj Ri Operation Ri or Rj Ri Flag change N Set when the MSB bit 7 of the operation result is 1 cleared when the MSB is 0 Z Set when the operation result is 0 cleared otherwise V and C Unchanged Execution cycles 1 2a cycl...

Page 122: ... R2 R3 R2 12345678 12345679 0 0 0 0 0 0 1 1 1 2 3 4 5 6 7 8 N Z V C CCR R2 R3 R3 CCR 0 0 0 0 1 0 N Z V C 0 0 0 0 1 2 3 4 5 6 7 8 0 0 0 0 0 0 1 1 12345678 12345679 1 1 Memory Memory Before execution After execution Instruction bit pattern 1001 0110 0010 0011 ...

Page 123: ...bler format EOR Rj Ri Operation Ri eor Rj Ri Flag change N Set when the MSB of the operation result is 1 cleared when the MSB is 0 Z Set when the operation result is 0 cleared otherwise V and C Unchanged Execution cycles 1 cycle Instruction format Example EOR R2 R3 N Z V C C C MSB LSB 1 0 0 1 1 0 1 0 Rj Ri R2 R3 1 1 1 1 0 0 0 0 1 0 1 0 1 0 1 0 N Z V C CCR R2 R3 CCR 0 0 0 0 N Z V C 0 0 0 0 0 1 0 1 ...

Page 124: ...PU will not accept hold requests between the memory read operation and the memory write operation of this request EOR Exclusive Or Word Data of Source Register to Data in Memory Assembler format EOR Rj Ri Operation Ri eor Rj Ri Flag change N Set when the MSB of the operation result is 1 cleared when the MSB is 0 Z Set when the operation result is 0 cleared otherwise V and C Unchanged Execution cyc...

Page 125: ...2345678 1234567C 1 1 1 1 0 0 0 0 1 2 3 4 5 6 7 8 N Z V C CCR R2 R3 R3 CCR 0 0 0 0 1 0 1 0 1 0 1 0 N Z V C 0 0 0 0 1 2 3 4 5 6 7 8 1 1 1 1 0 0 0 0 Memory 12345678 1234567C 0 1 0 1 1 0 1 0 Memory Before execution After execution Instruction bit pattern 1001 1100 0010 0011 ...

Page 126: ...CPU will not accept hold requests between the memory read operation and the memory write operation of this request EORH Exclusive Or Half word Data of Source Register to Data in Memory Assembler format EORH Rj Ri Operation Ri eor Rj Ri Flag change N Set when the MSB bit 15 of the operation result is 1 cleared when the MSB is 0 Z Set when the operation result is 0 cleared otherwise V and C Unchange...

Page 127: ... R3 R2 12345678 1234567A 0 0 0 0 1 1 0 0 1 2 3 4 5 6 7 8 N Z V C CCR R2 R3 R3 CCR 0 0 0 0 1 0 1 0 N Z V C 0 0 0 0 1 2 3 4 5 6 7 8 0 0 0 0 1 1 0 0 12345678 1234567A 0 1 1 0 Memory Memory Before execution After execution Instruction bit pattern 1001 1101 0010 0011 ...

Page 128: ...ill not accept hold requests between the memory read operation and the memory write operation of this request EORB Exclusive Or Byte Data of Source Register to Data in Memory Assembler format EORB Rj Ri Operation Ri eor Rj Ri Flag change N Set when the MSB bit 7 of the operation result is 1 cleared when the MSB is 0 Z Set when the operation result is 0 cleared otherwise V and C Unchanged Execution...

Page 129: ...B R2 R3 R2 12345678 12345679 0 0 0 0 0 0 1 1 1 2 3 4 5 6 7 8 N Z V C CCR R2 R3 R3 CCR 0 0 0 0 1 0 N Z V C 0 0 0 0 1 2 3 4 5 6 7 8 0 0 0 0 0 0 1 1 12345678 12345679 0 1 Memory Memory Before execution After execution Instruction bit pattern 1001 1110 0010 0011 ...

Page 130: ...to the memory address corresponding to Ri The CPU will not accept hold requests between the memory read operation and the memory write operation of this request BANDL And 4 bit Immediate Data to Lower 4 Bits of Byte Data in Memory Assembler format BANDL u4 Ri Operation F0H u4 and Ri Ri Operation uses lower 4 bits only Flag change N Z V and C Unchanged Execution cycles 1 2a cycles Instruction forma...

Page 131: ...UCTIONS Example BANDL 0 R3 12345678 12345679 1 2 3 4 5 6 7 8 N Z V C CCR R3 R3 CCR 0 0 0 0 1 1 N Z V C 0 0 0 0 1 2 3 4 5 6 7 8 Memory 12345678 12345679 1 0 Memory Instruction bit pattern 1000 0000 0000 0011 Before execution After execution ...

Page 132: ...o the memory address corresponding to Ri The CPU will not accept hold requests between the memory read operation and the memory write operation of this request BANDH And 4 bit Immediate Data to Higher 4 Bits of Byte Data in Memory Assembler format BANDH u4 Ri Operation u4 4 FH and Ri Ri Operation uses higher 4 bits only Flag change N Z V and C Unchanged Execution cycles 1 2a cycles Instruction for...

Page 133: ...UCTIONS Example BANDH 0 R3 12345678 12345679 1 2 3 4 5 6 7 8 N Z V C CCR R3 R3 CCR 0 0 0 0 1 1 N Z V C 0 0 0 0 1 2 3 4 5 6 7 8 Memory 12345678 12345679 0 1 Memory Instruction bit pattern 1000 0001 0000 0011 Before execution After execution ...

Page 134: ...sults to the memory address corresponding to Ri The CPU will not accept hold requests between the memory read operation and the memory write operation of this request BORL Or 4 bit Immediate Data to Lower 4 Bits of Byte Data in Memory Assembler format BORL u4 Ri Operation u4 or Ri Ri Operation uses lower 4 bits only Flag change N Z V and C Unchanged Execution cycles 1 2a cycles Instruction format ...

Page 135: ...RUCTIONS Example BORL 1 R3 12345678 12345679 1 2 3 4 5 6 7 8 N Z V C CCR R3 R3 CCR 0 0 0 0 0 0 N Z V C 0 0 0 0 1 2 3 4 5 6 7 8 12345678 12345679 0 1 Instruction bit pattern 1001 0000 0001 0011 Before execution After execution Memory Memory ...

Page 136: ...ults to the memory address corresponding to Ri The CPU will not accept hold requests between the memory read operation and the memory write operation of this request BORH Or 4 bit Immediate Data to Higher 4 Bits of Byte Data in Memory Assembler format BORH u4 Ri Operation u4 4 or Ri Ri Operation uses higher 4 bits only Flag change N Z V and C Unchanged Execution cycles 1 2a cycles Instruction form...

Page 137: ...RUCTIONS Example BORH 1 R3 12345678 12345679 1 2 3 4 5 6 7 8 N Z V C CCR R3 R3 CCR 0 0 0 0 0 0 N Z V C 0 0 0 0 1 2 3 4 5 6 7 8 12345678 12345679 1 0 Instruction bit pattern 1001 0001 0001 0011 Before execution After execution Memory Memory ...

Page 138: ...e results to the memory address corresponding to Ri The CPU will not accept hold requests between the memory read operation and the memory write operation of this request BEORL Eor 4 bit Immediate Data to Lower 4 Bits of Byte Data in Memory Assembler format BEORL u4 Ri Operation u4 eor Ri Ri Operation uses lower 4 bits only Flag change N Z V and C Unchanged Execution cycles 1 2a cycles Instruction...

Page 139: ...UCTIONS Example BEORL 1 R3 12345678 12345679 1 2 3 4 5 6 7 8 N Z V C CCR R3 R3 CCR 0 0 0 0 0 0 N Z V C 0 0 0 0 1 2 3 4 5 6 7 8 Memory 12345678 12345679 0 1 Memory Instruction bit pattern 1001 1000 0001 0011 Before execution After execution ...

Page 140: ... results to the memory address corresponding to Ri The CPU will not accept hold requests between the memory read operation and the memory write operation of this request BEORH Eor 4 bit Immediate Data to Higher 4 Bits of Byte Data in Memory Assembler format BEORH u4 Ri Operation u4 4 eor Ri Ri Operation uses higher 4 bits only Flag change N Z V and C Unchanged Execution cycles 1 2a cycles Instruct...

Page 141: ...UCTIONS Example BEORH 1 R3 12345678 12345679 1 2 3 4 5 6 7 8 N Z V C CCR R3 R3 CCR 0 0 0 0 0 0 N Z V C 0 0 0 0 1 2 3 4 5 6 7 8 Memory 12345678 12345679 1 0 Memory Instruction bit pattern 1001 1001 0001 0011 Before execution After execution ...

Page 142: ...Memory Assembler format BTSTL u4 Ri Operation u4 and Ri Test uses lower 4 bits only Flag change N Cleared Z Set when the operation result is 0 cleared otherwise V and C Unchanged Execution cycles 2 a cycles Instruction format Example BTSTL 1 R3 N Z V C 0 C MSB LSB 1 0 0 0 1 0 0 0 u4 Ri 12345678 12345679 1 2 3 4 5 6 7 8 N Z V C CCR R3 R3 CCR 0 0 0 0 1 0 N Z V C 0 1 0 0 1 2 3 4 5 6 7 8 12345678 1234...

Page 143: ... Operation u4 4 and Ri Test uses higher 4 bits only Flag change N Set when the MSB bit 7 of the operation result is 1 cleared when the MSB is 0 Z Set when the operation result is 0 cleared otherwise V and C Unchanged Execution cycles 2 a cycles Instruction format Example BTSTH 1 R3 N Z V C C C MSB LSB 1 0 0 0 1 0 0 1 u4 Ri 12345678 12345679 1 2 3 4 5 6 7 8 N Z V C CCR R3 R3 CCR 0 0 0 0 0 1 N Z V C...

Page 144: ...word in the multiplication division register MDL MUL Multiply Word Data Assembler format MUL Rj Ri Operation Rj Ri MDH MDL Flag change N Set when the MSB of the MDL of the operation result is 1 cleared when the MSB is 0 Z Set when the operation result is 0 cleared otherwise V Cleared when the operation result is in the range 2147483648 to 2147483647 set otherwise C Unchanged Execution cycles 5 cyc...

Page 145: ... MDL N Z V C CCR CCR 0 0 0 0 N Z V C 0 0 1 0 R2 R3 0 0 0 0 0 0 0 2 8 0 0 0 0 0 0 1 MDH MDL R2 R3 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 2 8 0 0 0 0 0 0 1 F F F F F F F F x x x x x x x x x x x x x x x x Before execution After execution Instruction bit pattern 1010 1111 0010 0011 ...

Page 146: ... word in the multiplication division register MDL MULU Multiply Unsigned Word Data Assembler format MULU Rj Ri Operation Rj Ri MDH MDL Flag change N Set when the MSB of the MDL of the operation result is 1 cleared when the MSB is 0 Z Set when the MDL of the operation result is 0 cleared otherwise V Cleared when the operation result is in the range 0 to 4294967295 set otherwise C Unchanged Executio...

Page 147: ... MDL N Z V C CCR CCR 0 0 0 0 N Z V C 0 0 1 0 R2 R3 0 0 0 0 0 0 0 2 8 0 0 0 0 0 0 1 MDH MDL R2 R3 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 2 8 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 x x x x x x x x x x x x x x x x Before execution After execution Instruction bit pattern 1010 1011 0010 0011 ...

Page 148: ... in the multiplication division register MDL The multiplication division register MDH is undefined MULH Multiply Half word Data Assembler format MULH Rj Ri Operation Rj Ri MDL Flag change N Set when the MSB of the MDL of the operation result is 1 cleared when the MSB is 0 Z Set when the MDL of the operation result is 0 cleared otherwise V Unchanged C Unchanged Execution cycles 3 cycles Instruction...

Page 149: ... MDL N Z V C CCR CCR 0 0 0 0 N Z V C 1 0 0 0 R2 R3 F E D C B A 9 8 0 1 2 3 4 5 6 7 MDH MDL R2 R3 F E D C B A 9 8 E D 2 F 0 B 2 8 0 1 2 3 4 5 6 7 x x x x x x x x x x x x x x x x x x x x x x x x Before execution After execution Instruction bit pattern 1011 1111 0010 0011 ...

Page 150: ...a in the multiplication division register MDL The multiplication division register MDH is undefined MULUH Multiply Unsigned Half word Data Assembler format MULUH Rj Ri Operation Rj Ri MDL Flag change N Set when the MSB of the MDL of the operation result is 1 cleared when the MSB is 0 Z Set when the MDL of the operation result is 0 cleared otherwise V Unchanged C Unchanged Execution cycles 3 cycles...

Page 151: ...H MDL N Z V C CCR CCR 0 0 0 0 N Z V C 0 0 0 0 R2 R3 F E D C B A 9 8 0 1 2 3 4 5 6 7 MDH MDL R2 R3 F E D C B A 9 8 3 2 9 6 0 B 2 8 0 1 2 3 4 5 6 7 x x x x x x x x x x x x x x x x x x x x x x x x Before execution After execution Instruction bit pattern 1011 1011 0010 0011 ...

Page 152: ...condition code register SCR D0 Set when the dividend is negative cleared when positive D1 Set when the divisor and dividend signs are different cleared when equal The word data in the MDL is extended to 64 bits with the higher word in the MDH and the lower word in the MDL To execute signed division the following instructions are used in combination DIV0S DIV1 32 DIV2 DIV3 DIV4S DIV0S Initial Setti...

Page 153: ... F F F F F 0 F F F F F F F F F F F F F F F 0 0 0 0 0 0 0 0 0 0 F F F F F F F Before execution After execution Instruction bit pattern 1001 0111 0100 0010 DIV0S R2 DIV1 R2 32 DIV1s are arranged DIV1 R2 DIV1 R2 DIV2 R2 DIV3 DIV4S MDH MDL D1 D0 T SCR SCR x x 0 D1 D0 T 1 1 0 R2 0 1 2 3 4 5 6 7 MDH MDL R2 F F F F F F F F F F F F F F F F F E D C B A 9 8 x x x x x x x x 0 1 2 3 4 5 6 7 Before execution A...

Page 154: ...t stored in the MDL register and the remainder in the multiplication division register MDH The MDH and bits D1 and D0 are cleared to 0 To execute unsigned division the instructions are used in combinations such as DIV0U and DIV1 x 32 DIV0U Initial Setting Up for Unsigned Division Assembler format DIV0U Ri Operation 0 D0 0 D1 0 MDH Flag change N Z V and C Unchanged Execution cycles 1 cycle Instruct...

Page 155: ...MDL R2 0 F F F F F F 0 0 0 0 0 0 0 0 0 0 F F F F F F 0 0 0 0 0 0 0 0 0 0 0 F F F F F F Before execution After execution Instruction bit pattern 1001 0111 0101 0010 DIV0U R2 DIV1 R2 32 DIV1s are arranged DIV1 R2 DIV1 R2 MDH MDL D1 D0 T SCR SCR x x 0 D1 D0 T 0 0 0 R2 0 1 2 3 4 5 6 7 MDH MDL R2 0 0 0 0 0 0 E 0 0 0 0 0 0 0 7 8 F E D C B A 9 8 x x x x x x x x 0 1 2 3 4 5 6 7 Before execution After exec...

Page 156: ... N and V Unchanged Z Set when the result of step division is 0 cleared otherwise Set according to remainder of division results not according to quotient C Set when the operation result of step division involves a carry operation cleared otherwise Execution cycles d cycle s Normally executed within one cycle However a 2 cycle interlock is applied if the instruction immediately after is one of the ...

Page 157: ... MDL D1 D0 T SCR SCR D1 D0 T 0 0 0 0 0 0 R2 0 0 F F F F F F MDH MDL R2 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F F F F F F 0 0 F F F F F F N Z V C CCR CCR N Z V C 0 0 0 0 0 0 0 0 Before execution After execution Instruction bit pattern 1001 0111 0110 0010 ...

Page 158: ...embler format DIV2 Ri Operation if D1 1 MDH Ri temp else MDH Ri temp if Z 1 0 MDH Flag change N and V Unchanged Z Set when the operation result of stepwise division is 0 cleared otherwise Set according to remainder of division results not according to quotient C Set when the result of stepwise division involves a carry or borrow operation cleared otherwise Execution cycles 1 cycle Instruction form...

Page 159: ... MDL D1 D0 T SCR SCR D1 D0 T 0 0 0 0 0 0 R2 0 0 F F F F F F MDH MDL R2 0 0 0 0 0 0 0 F 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F 0 0 F F F F F F 0 0 F F F F F F N Z V C CCR CCR N Z V C 0 1 0 0 0 0 0 0 Before execution After execution Instruction bit pattern 1001 0111 0111 0010 ...

Page 160: ...ler format DIV3 Operation if Z 1 MDL 1 MDL Flag change N Z V and C Unchanged Execution cycles 1 cycle Instruction format Example DIV3 N Z V C MSB LSB 1 0 0 1 1 1 1 1 0 1 1 0 0 0 0 0 MDH MDL D1 D0 T SCR SCR D1 D0 T 0 0 0 0 0 0 R2 0 0 F F F F F F MDH MDL R2 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F 0 0 0 0 0 0 0 0 0 0 F F F F F F N Z V C CCR CCR N Z V C 0 1 0 0 0 1 0 0 Before execution After e...

Page 161: ... Assembler format DIV4S Operation if D1 1 0 MDL MDL Flag change N Z V and C Unchanged Execution cycles 1 cycle Instruction format Example DIV4S N Z V C MSB LSB 1 0 0 1 1 1 1 1 0 1 1 1 0 0 0 0 MDH MDL D1 D0 T SCR SCR D1 D0 T 1 1 0 1 1 0 R2 0 0 F F F F F F MDH MDL R2 F F F F F F F 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F 0 0 0 0 0 0 0 0 0 0 F F F F F F N Z V C CCR CCR N Z V C 0 0 0 0 0 0 0 0 Before executi...

Page 162: ...SL Rj Ri Operation Ri Rj Ri Flag change N Set when the MSB of the operation result is 1 cleared when the MSB is 0 Z Set when the operation result is 0 cleared otherwise V Unchanged C Holds the bit value shifted last Cleared when the shift amount is 0 Execution cycles 1 cycle Instruction format Example LSL R2 R3 N Z V C C C C MSB LSB 1 0 1 1 0 1 1 0 Rj Ri R2 R3 R2 R3 F F F F F F 0 0 0 0 0 0 0 0 0 8...

Page 163: ...ge N Set when the MSB of the operation result is 1 cleared when the MSB is 0 Z Set when the operation result is 0 cleared otherwise V Unchanged C Holds the bit value shifted last Cleared when the shift amount is 0 Execution cycles 1 cycle Instruction format Example LSL 8 R3 N Z V C C C C MSB LSB 1 0 1 1 0 1 0 0 u4 Ri R3 R3 F F F F F F 0 0 F F F F F F F F N Z V C CCR CCR N Z V C 1 0 0 1 0 0 0 0 Ins...

Page 164: ... Ri u4 16 Ri Flag change N Set when the MSB of the operation result is 1 cleared when the MSB is 0 Z Set when the operation result is 0 cleared otherwise V Unchanged C Holds the bit value shifted last Execution cycles 1 cycle Instruction format Example LSL2 8 R3 N Z V C C C C MSB LSB 1 0 1 1 0 1 0 1 u4 Ri R3 R3 F F 0 0 0 0 0 0 F F F F F F F F N Z V C CCR CCR N Z V C 1 0 0 1 0 0 0 0 Instruction bit...

Page 165: ...LSR Rj Ri Operation Ri Rj Ri Flag change N Set when the MSB of the operation result is 1 cleared when the MSB is 0 Z Set when the operation result is 0 cleared otherwise V Unchanged C Holds the bit value shifted last Cleared when the shift amount is 0 Execution cycles 1 cycle Instruction format Example LSR R2 R3 N Z V C C C C MSB LSB 1 0 1 1 0 0 1 0 Rj Ri R2 R3 R2 R3 0 0 F F F F F F 0 0 0 0 0 0 0 ...

Page 166: ...nge N Set when the MSB of the operation result is 1 cleared when the MSB is 0 Z Set when the operation result is 0 cleared otherwise V Unchanged C Holds the bit value shifted last Cleared when the shift amount is 0 Execution cycles 1 cycle Instruction format Example LSR 8 R3 N Z V C C C C MSB LSB 1 0 1 1 0 0 0 0 u4 Ri R3 R3 0 0 F F F F F F F F F F F F F F N Z V C CCR CCR N Z V C 0 0 0 1 0 0 0 0 In...

Page 167: ...mbler format LSR2 u4 Ri Operation Ri u4 16 Ri Flag change N Cleared Z Set when the operation result is 0 cleared otherwise V Unchanged C Holds the bit value shifted last Execution cycles 1 cycle Instruction format Example LSR2 8 R3 N Z V C 0 C C MSB LSB 1 0 1 1 0 0 0 1 u4 Ri R3 R3 0 0 0 0 0 0 F F F F F F F F F F N Z V C CCR CCR N Z V C 0 0 0 1 0 0 0 0 Instruction bit pattern 1011 0001 1000 0011 Be...

Page 168: ...rmat ASR Rj Ri Operation Ri Rj Ri Flag change N Set when the MSB of the operation result is 1 cleared when the MSB is 0 Z Set when the operation result is 0 cleared otherwise V Unchanged C Holds the bit value shifted last Cleared when the shift amount is 0 Execution cycles 1 cycle Instruction format Example ASR R2 R3 N Z V C C C C MSB LSB 1 0 1 1 1 0 1 0 Rj Ri R2 R3 R2 R3 F F F F 0 F F F 0 0 0 0 0...

Page 169: ...g change N Set when the MSB of the operation result is 1 cleared when the MSB is 0 Z Set when the operation result is 0 cleared otherwise V Unchanged C Holds the bit value shifted last Cleared when the shift amount is 0 Execution cycles 1 cycle Instruction format Example ASR 8 R3 N Z V C C C C MSB LSB 1 0 1 1 1 0 0 0 u4 Ri R3 R3 F F F F 0 F F F F F 0 F F F F F N Z V C CCR CCR N Z V C 1 0 0 1 0 0 0...

Page 170: ...ration Ri u4 16 Ri Flag change N Set when the MSB of the operation result is 1 cleared when the MSB is 0 Z Set when the operation result is 0 cleared otherwise V Unchanged C Holds the bit value shifted last Execution cycles 1 cycle Instruction format Example ASR2 8 R3 N Z V C C C C MSB LSB 1 0 1 1 1 0 0 1 u4 Ri R3 R3 F F F F F F F 0 F 0 F F F F F F N Z V C CCR CCR N Z V C 1 0 0 1 0 0 0 0 Instructi...

Page 171: ... Register Assembler format LDI 32 i32 Ri Operation i32 Ri Flag change N Z V and C Unchanged Execution cycles 3 cycles Instruction format Example LDI 32 87654321H R3 N Z V C MSB LSB 1 0 0 1 1 1 1 1 1 0 0 0 Ri n 0 i32 higher i32 lower n 2 n 4 R3 R3 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 Before execution After execution Instruction bit pattern 1001 1111 1000 0011 1000 0111 0110 0101 0100 0011 0010 0001 ...

Page 172: ...Immediate 20 bit Data to Destination Register Assembler format LDI 20 i20 Ri Operation extu i20 Ri Flag change N Z V and C Unchanged Execution cycles 2 cycles Instruction format Example LDI 20 54321H R3 N Z V C MSB LSB 1 0 0 1 1 0 1 1 Ri n 0 i20 lower i20 higher n 2 R3 R3 0 0 0 5 4 3 2 1 0 0 0 0 0 0 0 0 Before execution After execution Instruction bit pattern 1001 1011 0101 0011 0100 0011 0010 000...

Page 173: ...r bits loads to Ri LDI 8 Load Immediate 8 bit Data to Destination Register Assembler format LDI 8 i8 Ri Operation extu i8 Ri Flag change N Z V and C Unchanged Execution cycles 1 cycle Instruction format Example LDI 8 21H R3 N Z V C MSB LSB 1 1 0 0 Ri i8 R3 R3 0 0 0 0 0 0 2 1 0 0 0 0 0 0 0 0 Before execution After execution Instruction bit pattern 1100 0010 0001 0011 ...

Page 174: ...er format LD Rj Ri Operation Rj Ri Flag change N Z V and C Unchanged Execution cycles b cycle s Instruction format Example LD R2 R3 N Z V C MSB LSB 0 0 0 0 0 1 0 0 Rj Ri R2 12345678 1 2 3 4 5 6 7 8 0 0 0 0 0 0 0 0 R2 R3 R3 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 1 2 3 4 5 6 7 8 Memory 12345678 8 7 6 5 4 3 2 1 Memory Before execution After execution Instruction bit pattern 0000 0100 0010 0011 ...

Page 175: ...R13 Rj Ri Flag change N Z V and C Unchanged Execution cycles b cycle s Instruction format Example LD R13 R2 R3 N Z V C MSB LSB 0 0 0 0 0 0 0 0 Rj Ri R2 12345678 1234567C 0 0 0 0 0 0 0 4 x x x x x x x x 1 2 3 4 5 6 7 8 R2 R3 R3 R13 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 4 12345678 1234567C 8 7 6 5 4 3 2 1 1 2 3 4 5 6 7 8 R13 Memory Memory Before execution After execution Instruction bit patt...

Page 176: ...Assembler format LD R14 disp10 Ri Operation R14 o8 4 Ri Flag change N Z V and C Unchanged Execution cycles b cycle s Instruction format Example LD R14 4 R3 N Z V C MSB LSB 0 0 1 0 Ri o8 12345678 1234567C x x x x x x x x 1 2 3 4 5 6 7 8 R3 R14 8 7 6 5 4 3 2 1 12345678 1234567C 8 7 6 5 4 3 2 1 R3 1 2 3 4 5 6 7 8 8 7 6 5 4 3 2 1 R14 Instruction bit pattern 0010 0000 0001 0011 Memory Memory Before exe...

Page 177: ...sembler format LD R15 udisp6 Ri Operation R15 u4 4 Ri Flag change N Z V and C Unchanged Execution cycles b cycle s Instruction format Example LD R15 4 R3 N Z V C MSB LSB 0 0 0 0 0 0 1 1 u4 Ri 12345678 1234567C 1 2 3 4 5 6 7 8 R3 R15 8 7 6 5 4 3 2 1 12345678 1234567C 8 7 6 5 4 3 2 1 R3 1 2 3 4 5 6 7 8 8 7 6 5 4 3 2 1 R15 Instruction bit pattern 0000 0011 0001 0011 x x x x x x x x Memory Memory Befo...

Page 178: ... LD Load Word Data in Memory to Register Assembler format LD R15 Ri Operation R15 Ri R15 4 R15 Flag change N Z V and C Unchanged Execution cycles b cycle s Instruction format Example LD R15 R3 N Z V C MSB LSB 0 0 0 0 0 1 1 1 0 0 0 0 Ri 12345678 1234567C 1 2 3 4 5 6 7 8 R3 R15 8 7 6 5 4 3 2 1 12345678 1234567C 8 7 6 5 4 3 2 1 R3 1 2 3 4 5 6 7 C 8 7 6 5 4 3 2 1 R15 x x x x x x x x Memory Memory Befo...

Page 179: ...is designated as the system stack pointer SSP or user stack pointer USP and that pointer is indicating R15 the S flag in the condition code register CCR is set to 0 to indicate the SSP and to 1 to indicate the USP the last value remaining in R15 will be the value read from memory LD Load Word Data in Memory to Register Assembler format LD R15 Rs Operation R15 Rs R15 4 R15 Flag change N Z V and C U...

Page 180: ...le LD R15 MDH 12345670 12345674 1 2 3 4 5 6 7 4 R15 MDH 8 7 6 5 4 3 2 1 12345670 12345674 8 7 6 5 4 3 2 1 R15 1 2 3 4 5 6 7 8 8 7 6 5 4 3 2 1 MDH x x x x x x x x Memory Memory Before execution After execution Instruction bit pattern 0000 0111 1000 0100 ...

Page 181: ...o that data before being transferred to the ILM If the original ILM value is in the range 0 to 15 then any value from 0 to 31 can be transferred to the ILM LD Load Word Data in Memory to Program Status Register Assembler format LD R15 PS Operation R15 PS R15 4 R15 Flag change N Z V and C Data is transferred from R15 Execution cycles 1 a c cycles The value of c is normally 1 cycle However if the ne...

Page 182: ...mple LD R15 PS 12345670 12345674 1 2 3 4 5 6 7 4 F F F F F 8 D 5 PS R15 F F F 8 F 8 C 0 12345670 12345674 F F F 8 F 8 C 0 PS 1 2 3 4 5 6 7 8 F F F 8 F 8 C 0 R15 Memory Memory Before execution After execution Instruction bit pattern 0000 0111 1001 0000 ...

Page 183: ...ory to Register Assembler format LDUH Rj Ri Operation extu Rj Ri Flag change N Z V and C Unchanged Execution cycles b cycle s Instruction format Example LDUH R2 R3 N Z V C MSB LSB 0 0 0 0 0 1 0 1 Rj Ri R2 12345678 1 2 3 4 5 6 7 8 x x x x x x x x R2 R3 R3 4 3 2 1 0 0 0 0 4 3 2 1 1 2 3 4 5 6 7 8 Memory 12345678 4 3 2 1 Memory Before execution After execution Instruction bit pattern 0000 0101 0010 00...

Page 184: ...LDUH R13 Rj Ri Operation extu R13 Rj Ri Flag change N Z V and C Unchanged Execution cycles b cycle s Instruction format Example LDUH R13 R2 R3 N Z V C MSB LSB 0 0 0 0 0 0 0 1 Rj Ri R2 12345678 0 0 0 0 0 0 0 4 x x x x x x x x R2 R3 R3 4 3 2 1 0 0 0 0 4 3 2 1 0 0 0 0 0 0 0 4 12345678 1234567C 1234567C 4 3 2 1 1 2 3 4 5 6 7 8 R13 R13 1 2 3 4 5 6 7 8 Memory Memory Before execution After execution Inst...

Page 185: ... in Memory to Register Assembler format LDUH R14 disp9 Ri Operation extu R14 o8 2 Ri Flag change N Z V and C Unchanged Execution cycles b cycle s Instruction format Example LDUH R14 2 R3 N Z V C MSB LSB 0 1 0 0 Ri o8 12345678 R3 R3 4 3 2 1 0 0 0 0 4 3 2 1 12345678 1234567A 1234567A 4 3 2 1 1 2 3 4 5 6 7 8 R14 1 2 3 4 5 6 7 8 R14 Instruction bit pattern 0100 0000 0001 0011 Memory Memory Before exec...

Page 186: ...to Register Assembler format LDUB Rj Ri Operation extu Rj Ri Flag change N Z V and C Unchanged Execution cycles b cycle s Instruction format Example LDUB R2 R3 N Z V C MSB LSB 0 0 0 0 0 1 1 0 Rj Ri R2 12345678 1 2 3 4 5 6 7 8 x x x x x x x x R2 R3 R3 2 1 0 0 0 0 0 0 2 1 1 2 3 4 5 6 7 8 12345678 2 1 Memory Memory Before execution After execution Instruction bit pattern 0000 0110 0010 0011 ...

Page 187: ... R13 Rj Ri Operation extu R13 Rj Ri Flag change N Z V and C Unchanged Execution cycles b cycle s Instruction format Example LDUB R13 R2 R3 N Z V C MSB LSB 0 0 0 0 0 0 1 0 Rj Ri R2 12345678 0 0 0 0 0 0 0 4 x x x x x x x x R2 R3 R3 2 1 0 0 0 0 0 0 2 1 0 0 0 0 0 0 0 4 12345678 1234567C 1234567C 2 1 1 2 3 4 5 6 7 8 R13 R13 1 2 3 4 5 6 7 8 Memory Memory Before execution After execution Instruction bit ...

Page 188: ... Memory to Register Assembler format LDUB R14 disp8 Ri Operation extu R14 o8 Ri Flag change N Z V and C Unchanged Execution cycles b cycle s Instruction format Example LDUB R14 1 R3 N Z V C MSB LSB 0 1 1 0 Ri o8 12345678 x x x x x x x x R3 R3 2 1 0 0 0 0 0 0 2 1 12345678 12345679 12345679 2 1 1 2 3 4 5 6 7 8 R14 1 2 3 4 5 6 7 8 R14 Instruction bit pattern 0110 0000 0001 0011 Memory Memory Before e...

Page 189: ...ler format ST Ri Rj Operation Ri Rj Flag change N Z V and C Unchanged Execution cycles a cycle s Instruction format Example ST R3 R2 N Z V C MSB LSB 0 0 0 1 0 1 0 0 Rj Ri R2 12345678 1 2 3 4 5 6 7 8 8 7 6 5 4 3 2 1 R2 R3 R3 x x x x x x x x 8 7 6 5 4 3 2 1 1 2 3 4 5 6 7 8 12345678 8 7 6 5 4 3 2 1 Memory Memory Before execution After execution Instruction bit pattern 0001 0100 0010 0011 ...

Page 190: ... Ri R13 Rj Flag change N Z V and C Unchanged Execution cycles a cycle s Instruction format Example ST R3 R13 R2 N Z V C MSB LSB 0 0 0 1 0 0 0 0 Rj Ri R2 12345678 0 0 0 0 0 0 0 4 8 7 6 5 4 3 2 1 R2 R3 R3 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 4 12345678 1234567C 1234567C 1 2 3 4 5 6 7 8 R13 R13 1 2 3 4 5 6 7 8 x x x x x x x x Memory Memory Before execution After execution Instruction bit pat...

Page 191: ... Assembler format ST Ri R14 disp10 Operation Ri R14 o8 4 Flag change N Z V and C Unchanged Execution cycles a cycle s Instruction format Example ST R3 R14 4 N Z V C MSB LSB 0 0 1 1 Ri o8 12345678 R3 R3 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 12345678 1234567C 1234567C 1 2 3 4 5 6 7 8 8 7 6 5 4 3 2 1 R14 1 2 3 4 5 6 7 8 R14 Instruction bit pattern 0011 0000 0001 0011 x x x x x x x x Memory Memory Before ex...

Page 192: ...ssembler format ST Ri R15 udisp6 Operation Ri R15 u4 4 Flag change N Z V and C Unchanged Execution cycles a cycle s Instruction format Example ST R3 R15 4 N Z V C MSB LSB 0 0 0 1 0 0 1 1 u4 Ri 12345678 R3 R3 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 12345678 1234567C 1234567C 1 2 3 4 5 6 7 8 8 7 6 5 4 3 2 1 R15 1 2 3 4 5 6 7 8 R15 Instruction bit pattern 0001 0011 0001 0011 x x x x x x x x Memory Memory Bef...

Page 193: ...before subtraction ST Store Word Data in Register to Memory Assembler format ST Ri R15 Operation R15 4 R15 Ri R15 Flag change N Z V and C Unchanged Execution cycles a cycle s Instruction format Example ST R3 R15 N Z V C MSB LSB 0 0 0 1 0 1 1 1 0 0 0 0 Ri 12345674 R3 R3 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 12345674 12345678 12345678 1 2 3 4 5 6 7 8 8 7 6 5 4 3 2 1 R15 1 2 3 4 5 6 7 4 R15 x x x x x x x x...

Page 194: ... will be transferred ST Store Word Data in Register to Memory Assembler format ST Rs R15 Operation R15 4 R15 Rs R15 Flag change N Z V and C Unchanged Execution cycles a cycle s Instruction format Example ST MDH R15 N Z V C MSB LSB 0 0 0 1 0 1 1 1 1 0 0 0 Rs 12345670 R15 R15 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 12345670 12345674 12345674 1 2 3 4 5 6 7 8 8 7 6 5 4 3 2 1 MDH 1 2 3 4 5 6 7 4 MDH x x x x x ...

Page 195: ...ogram Status Register to Memory Assembler format ST PS R15 Operation R15 4 R15 PS R15 Flag change N Z V and C Unchanged Execution cycles a cycle s Instruction format Example ST PS R15 N Z V C MSB LSB 0 0 0 1 0 1 1 1 1 0 0 1 0 0 0 0 12345670 R15 R15 F F F 8 F 8 C 0 F F F 8 F 8 C 0 12345670 12345674 12345674 1 2 3 4 5 6 7 8 F F F 8 F 8 C 0 PS 1 2 3 4 5 6 7 4 PS x x x x x x x x Memory Memory Before e...

Page 196: ...to Memory Assembler format STH Ri Rj Operation Ri Rj Flag change N Z V and C Unchanged Execution cycles a cycle s Instruction format Example STH R3 R2 N Z V C MSB LSB 0 0 0 1 0 1 0 1 Rj Ri R2 12345678 1 2 3 4 5 6 7 8 0 0 0 0 4 3 2 1 R2 R3 R3 0 0 0 0 4 3 2 1 1 2 3 4 5 6 7 8 12345678 4 3 2 1 x x x x Memory Memory Before execution After execution Instruction bit pattern 0001 0101 0010 0011 ...

Page 197: ... R13 Rj Operation Ri R13 Rj Flag change N Z V and C Unchanged Execution cycles a cycle s Instruction format Example STH R3 R13 R2 N Z V C MSB LSB 0 0 0 1 0 0 0 1 Rj Ri R2 1234567A 0 0 0 0 0 0 0 4 0 0 0 0 4 3 2 1 R2 R3 R3 0 0 0 0 4 3 2 1 4 3 2 1 0 0 0 0 0 0 0 4 1234567A 1234567C 1234567C 1 2 3 4 5 6 7 8 R13 R13 1 2 3 4 5 6 7 8 x x x x Memory Memory Before execution After execution Instruction bit p...

Page 198: ...egister to Memory Assembler format STH Ri R14 disp9 Operation Ri R14 o8 2 Flag change N Z V and C Unchanged Execution cycles a cycle s Instruction format Example STH R3 R14 2 N Z V C MSB LSB 0 1 0 1 Ri o8 12345678 R3 R3 0 0 0 0 4 3 2 1 4 3 2 1 12345678 1234567A 1234567A 1 2 3 4 5 6 7 8 0 0 0 0 4 3 2 1 R14 1 2 3 4 5 6 7 8 R14 Instruction bit pattern 0101 0000 0001 0011 x x x x Memory Memory Before ...

Page 199: ...Memory Assembler format STB Ri Rj Operation Ri Rj Flag change N Z V and C Unchanged Execution cycles a cycle s Instruction format Example STB R3 R2 N Z V C MSB LSB 0 0 0 1 0 1 1 0 Rj Ri R2 12345678 1 2 3 4 5 6 7 8 0 0 0 0 0 0 2 1 R2 R3 R3 0 0 0 0 0 0 2 1 1 2 3 4 5 6 7 8 12345678 2 1 x x Memory Memory Before execution After execution Instruction bit pattern 0001 0110 0010 0011 ...

Page 200: ...3 Rj Operation Ri R13 Rj Flag change N Z V and C Unchanged Execution cycles a cycle s Instruction format Example STB R3 R13 R2 N Z V C MSB LSB 0 0 0 1 0 0 1 0 Rj Ri R2 1234567B 0 0 0 0 0 0 0 4 0 0 0 0 0 0 2 1 R2 R3 R3 0 0 0 0 0 0 2 1 2 1 0 0 0 0 0 0 0 4 1234567B 1234567C 1234567C 1 2 3 4 5 6 7 8 R13 R13 1 2 3 4 5 6 7 8 x x Memory Memory Before execution After execution Instruction bit pattern 0001...

Page 201: ...ter to Memory Assembler format STB Ri R14 disp8 Operation Ri R14 o8 Flag change N Z V and C Unchanged Execution cycles a cycle s Instruction format Example STB R3 R14 1 N Z V C MSB LSB 0 1 1 1 Ri o8 12345678 R3 R3 0 0 0 0 0 0 2 1 2 1 12345678 12345679 12345679 1 2 3 4 5 6 7 8 0 0 0 0 0 0 2 1 R14 1 2 3 4 5 6 7 8 R14 Instruction bit pattern 0111 0000 0001 0011 x x Memory Memory Before execution Afte...

Page 202: ...Source Register to Destination Register Assembler format MOV Rj Ri Operation Rj Ri Flag change N Z V and C Unchanged Execution cycles 1 cycle Instruction format Example MOV R2 R3 N Z V C MSB LSB 1 0 0 0 1 0 1 1 Rj Ri R2 8 7 6 5 4 3 2 1 x x x x x x x x R2 R3 R3 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 Before execution After execution Instruction bit pattern 1000 1011 0010 0011 ...

Page 203: ...s given as Rs undefined data will be transferred MOV Move Word Data in Source Register to Destination Register Assembler format MOV Rs Ri Operation Rs Ri Flag change N Z V and C Unchanged Execution cycles 1 cycle Instruction format Example MOV MDL R3 N Z V C MSB LSB 1 0 1 1 0 1 1 1 Rs Ri R3 R3 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 MDL 8 7 6 5 4 3 2 1 MDL x x x x x x x x Before execution After execution ...

Page 204: ... Move Word Data in Program Status Register to Destination Register Assembler format MOV PS Ri Operation PS Ri Flag change N Z V and C Unchanged Execution cycles 1 cycle Instruction format Example MOV PS R3 N Z V C MSB LSB 0 0 0 1 0 1 1 1 0 0 0 1 Ri R3 R3 F F F 8 F 8 C 0 F F F 8 F 8 C 0 PS F F F 8 F 8 C 0 PS x x x x Before execution After execution x x x x Instruction bit pattern 0001 0111 0001 001...

Page 205: ... parameter Rs the read value Ri will be ignored MOV Move Word Data in Source Register to Destination Register Assembler format MOV Ri Rs Operation Ri Rs Flag change N Z V and C Unchanged Execution cycles 1 cycle Instruction format Example MOV R3 MDL N Z V C MSB LSB 1 0 1 1 0 0 1 1 Rs Ri R3 R3 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 x x x x x x x x MDL MDL Before execution After execution I...

Page 206: ...ore being transferred to the ILM If the original ILM value is in the range 0 to 15 then any value from 0 to 31 can be transferred to the ILM MOV Move Word Data in Source Register to Program Status Register Assembler format MOV Ri PS Operation Ri PS Flag change N Z V and C Data is transferred from Ri Execution cycles c cycle s The number of execution cycles is normally 1 However if the instruction ...

Page 207: ...PTER 7 DETAILED EXECUTION INSTRUCTIONS Example MOV R3 PS R3 R3 F F F 3 F 8 D 5 F F F 3 F 8 D 5 F F F 3 F 8 D 5 PS PS x x x x x x x x Before execution After execution Instruction bit pattern 0000 0111 0001 0011 ...

Page 208: ... by Ri JMP Jump Assembler format JMP Ri Operation Ri PC Flag change N Z V and C Unchanged Execution cycles 2 cycles Instruction format Example JMP R1 N Z V C MSB LSB 1 0 0 1 0 1 1 1 0 0 0 0 Ri R1 R1 C 0 0 0 8 0 0 0 F F 8 0 0 0 0 0 0 0 0 0 0 0 F F C 0 0 0 8 0 0 0 PC PC Before execution After execution Instruction bit pattern 1001 0111 0000 0001 ...

Page 209: ...PC When calculating the address double the value of rel11 as a signed extension CALL Call Subroutine Assembler format CALL label12 Operation PC 2 RP PC 2 exts rel11 2 PC Flag change N Z V and C Unchanged Execution cycles 2 cycles Instruction format Example CALL label label CALL instruction address 122H N Z V C MSB LSB 1 1 0 1 0 rel11 PC PC F F 8 0 0 0 0 0 F F 8 0 0 1 2 2 F F 8 0 0 0 0 4 x x x x x ...

Page 210: ... indicated by Ri occurs CALL Call Subroutine Assembler format CALL Ri Operation PC 2 RP Ri PC Flag change N Z V and C Unchanged Execution cycles 2 cycles Instruction format Example CALL R1 N Z V C MSB LSB 1 0 0 1 0 1 1 1 0 0 0 1 Ri R1 F F F F F 8 0 0 8 0 0 0 F F F E F F F F F 8 0 0 F F F F F 8 0 0 PC 8 0 0 1 0 0 0 0 RP R1 PC RP x x x x Before execution After execution x x x x Instruction bit patte...

Page 211: ...eturn pointer RP RET Return from Subroutine Assembler format RET Operation RP PC Flag change N Z V and C Unchanged Execution cycles 2 cycles Instruction format Example RET N Z V C MSB LSB 1 0 0 1 0 1 1 1 0 0 1 0 0 0 0 0 PC PC F F F 0 8 8 2 0 8 0 0 0 A E 8 6 8 0 0 0 A E 8 6 8 0 0 0 A E 8 6 RP RP Before execution After execution Instruction bit pattern 1001 0111 0010 0000 ...

Page 212: ...nterrupts Reads the vector table for the interrupt vector number u8 to determine the branch destination address and branches This instruction has no delay slot Vector numbers 9 to 13 64 and 65 are used by emulators for debugging interrupts and therefore the corresponding numbers INT 9 to INT 13 INT 64 INT 65 should not be used in user programs INT Software Interrupt Assembler format INT u8 Operati...

Page 213: ... 0 0 0 0 0 0 4 0 0 0 0 0 0 0 SSP TBR 4 0 0 0 0 0 0 0 0 0 0 F F C 0 0 USP PC F F F F F 8 F 0 8 0 8 8 8 0 8 6 PS 1 1 0 0 0 0 S I N Z V C CCR R15 7 F F F F F F 8 7 F F F F F F 8 SSP TBR 4 0 0 0 0 0 0 0 0 0 0 F F C 0 0 USP PC F F F F F 8 C 0 6 8 0 9 6 8 0 0 PS 0 0 0 0 0 0 S I N Z V C CCR Memory Memory Before execution After execution x x x x x x x x x x x x x x x x x x x x x x x x Instruction bit patt...

Page 214: ...ng interrupt vector number 9 from the vector table then branches There is no change to the I flag in the condition code register CCR The interrupt level mask register ILM in the program status PS is set to level 4 This instruction is the software interrupt instruction for debugging In step execution no EIT events are generated by the INTE instruction This instruction has no delay slot INTE Softwar...

Page 215: ... 0 0 0 0 0 0 SSP TBR 4 0 0 0 0 0 0 0 0 0 0 F F C 0 0 USP PC F F F 5 F 8 F 0 8 0 8 8 8 0 8 6 PS 1 0 1 0 1 ILM 0 0 1 0 0 ILM 1 1 0 0 0 0 S I N Z V C CCR R15 7 F F F F F F 8 7 F F F F F F 8 SSP TBR 4 0 0 0 0 0 0 0 0 0 0 F F C 0 0 USP PC F F E 4 F 8 D 0 6 8 0 9 6 8 0 0 PS 0 1 0 0 0 0 S I N Z V C CCR Memory Memory Before execution After execution x x x x x x x x x x x x x x x x x x x x x x x x Instruct...

Page 216: ... executed if the value of the interrupt level mask register ILM is in the range 16 to 31 only new ILM settings between 16 and 31 can be entered If data in the range 0 to 15 is loaded in memory the value 16 will be added to that data before being transferred to the ILM If the original ILM value is in the range 0 to 15 then any value between 0 and 31 can be transferred to the ILM RETI Return from In...

Page 217: ...0000000 8 0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 SSP 4 0 0 0 0 0 0 0 USP PC F F F 3 F 8 F 1 8 0 8 8 8 0 8 8 PS 1 0 0 1 1 ILM 1 0 0 0 0 ILM 1 1 0 0 0 1 S I N Z V C CCR R15 7 F F F F F F 8 7 F F F F F F 8 SSP 4 0 0 0 0 0 0 0 USP PC F F F 0 F 8 D 4 F F 0 0 9 0 B C PS 0 1 0 1 0 0 S I N Z V C CCR Memory Memory Before execution After execution x x x x x x x x Instruction bit pattern 1001 0111 0011 0000 ...

Page 218: ...7 94 1 Bcc Branch Relative if Condition Satisfied Assembler format BRA label9 BV label9 BNO label9 BNV label9 BEQ label9 BLT label9 BNE label9 BGE label9 BC label9 BLE label9 BNC label9 BGT label9 BN label9 BLS label9 BP label9 BHI label9 Operation if conditions satisfied PC 2 exts rel8 2 PC Flag change N Z V and C Unchanged Table 7 94 1 Branching Conditions Mnemonic cc Conditions Mnemonic cc Cond...

Page 219: ...h 1 cycle Instruction format Example BHI label label BHI instruction address 50H MSB LSB 1 1 1 0 cc rel8 PC PC F F 8 0 0 0 5 2 F F 8 0 0 0 0 0 N Z V C CCR CCR N Z V C 1 0 1 0 1 0 1 0 Z or C 0 conditions satisfied Before execution After execution Instruction bit pattern 1110 1111 0010 1000 ...

Page 220: ...D R1 LDI 8 0FFH R1 Instruction placed in delay slot The instruction placed in the delay slot will be executed before execution of the branch destination instruction The value R1 above will vary according to the specifications of the LDI 8 instruction placed in the delay slot N Z V C MSB LSB 1 0 0 1 1 1 1 1 0 0 0 0 Ri R1 R1 0 0 0 0 0 0 F F F F 8 0 0 0 0 0 C 0 0 0 8 0 0 0 PC C 0 0 0 8 0 0 0 PC Befor...

Page 221: ...y slot to the RP branch to the address indicated by label12 relative to the value of the program counter PC When calculating the address double the value of rel11 as a signed extension CALL D Call Subroutine Assembler format CALL D label12 Operation PC 4 RP PC 2 exts rel11 2 PC Flag change N Z V and C Unchanged Execution cycles 1 cycle Instruction format N Z V C MSB LSB 1 1 0 1 1 rel11 ...

Page 222: ...ill be executed before execution of the branch destination instruction The value R2 above will vary according to the specifications of the LDI 8 instruction placed in the delay slot PC F F 8 0 0 1 2 2 F F 8 0 0 0 0 0 RP F F 8 0 0 0 0 4 R2 PC RP R2 0 0 0 0 0 0 0 0 x x x x x x x x x x x x x x x x Before execution of CALL instruction After branching Instruction bit pattern 1101 1000 1001 0000 ...

Page 223: ...lot After saving the address of the next instruction after the delay slot to the RP it branches to the address indicated by Ri CALL D Call Subroutine Assembler format CALL D Ri Operation PC 4 RP Ri PC Flag change N Z V and C Unchanged Execution cycles 1 cycle Instruction format N Z V C MSB LSB 1 0 0 1 1 1 1 1 0 0 0 1 Ri ...

Page 224: ...re execution of the branch destination instruction The value R1 above will vary according to the specifications of the LDI 8 instruction placed in the delay slot PC F F F F F 8 0 0 8 0 0 0 F F F E F F F F F 8 0 0 RP 8 0 0 1 0 0 0 2 R1 PC RP R1 0 0 0 0 0 0 0 1 x x x x x x x x Before execution of CALL instruction After branching Instruction bit pattern 1001 1111 0001 0001 ...

Page 225: ...s is a branching instruction with a delay slot Branches to the address indicated by the RP RET D Return from Subroutine Assembler format RET D Operation RP PC Flag change N Z V and C Unchanged Execution cycles 1 cycle Instruction format N Z V C MSB LSB 1 0 0 1 1 1 1 1 0 0 1 0 0 0 0 0 ...

Page 226: ...branch destination instruction The value R1 above will vary according to the specifications of the MOV instruction placed in the delay slot PC 8 0 0 0 A E 8 6 F F F 0 x x x x x x x x 8 8 2 0 8 0 0 0 A E 8 6 RP 8 0 0 0 A E 8 6 PC RP 0 0 1 1 2 2 3 3 R0 R0 0 0 1 1 2 2 3 3 R1 R1 0 0 1 1 2 2 3 3 Before execution of RET instruction After branching Instruction bit pattern 1001 1111 0010 0000 ...

Page 227: ...ion Satisfied Assembler format BRA D label9 BV D label9 BNO D label9 BNV D label9 BEQ D label9 BLT D label9 BNE D label9 BGE D label9 BC D label9 BLE D label9 BNC D label9 BGT D label9 BN D label9 BLS D label9 BP D label9 BHI D label9 Operation if conditions satisfied PC 2 exts rel8 2 PC Flag change N Z V and C Unchanged Table 7 99 1 Branching Conditions Mnemonic cc Conditions Mnemonic cc Conditio...

Page 228: ...ot will be executed before execution of the branch destination instruction The value R1 above will vary according to the specifications of the LDI 8 instruction placed in the delay slot MSB LSB 1 1 1 1 cc rel8 PC PC F F 8 0 0 0 5 2 F F 8 0 0 0 0 0 R1 R1 0 0 0 0 0 0 F F 8 9 4 7 9 7 A F N Z V C CCR CCR N Z V C 1 0 1 0 1 0 1 0 Z or C 0 conditions satisfied Before execution After execution Instruction...

Page 229: ...ister Assembler format DMOV dir10 R13 Operation dir8 4 R13 Flag change N Z V and C Unchanged Execution cycles b cycle s Instruction format Example DMOV 88H R13 N Z V C MSB LSB 0 0 0 0 1 0 0 0 dir8 0 1 2 3 4 5 6 7 R13 Memory x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 84H 88H 8CH 84H 88H 8CH 0 1 2 3 4 5 6 7 R13 Memory 0 1 2 3 4 5 6 7 Instruction bit pattern 0000 ...

Page 230: ...dress Assembler format DMOV R13 dir10 Operation R13 dir8 4 Flag change N Z V and C Unchanged Execution cycles a cycle s Instruction format Example DMOV R13 54H N Z V C MSB LSB 0 0 0 1 1 0 0 0 dir8 R13 Memory x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 50H 54H 58H 50H 54H 58H 8 9 A B C D E F R13 Memory Instruction bit pattern 0001 1000 0001 0101 Before execution ...

Page 231: ...onding to 4 times the value of dir8 to the address indicated in R13 After the data transfer it increments the value of R13 by 4 DMOV Move Word Data from Direct Address to Post Increment Register Indirect Address Assembler format DMOV dir10 R13 Operation dir8 4 R13 R13 4 R13 Flag change N Z V and C Unchanged Execution cycles 2a cycles Instruction format N Z V C MSB LSB 0 0 0 0 1 1 0 0 dir8 ...

Page 232: ...4 2 1 3 5 1 4 1 4 2 1 3 5 1 4 1 4 2 1 3 5 R13 Memory 00000088 FFFF1248 FFFF124C FFFF1248 FFFF124C 00000088 F F F F 1 2 4 8 R13 Memory F F F F 1 2 4 C Instruction bit pattern 0000 1100 0010 0010 x x x x x x x x x x x x x x x x x x x x x x x x Before execution After execution ...

Page 233: ...R13 to the direct address corresponding to 4 times the value dir8 After the data transfer it increments the value of R13 by 4 DMOV Move Word Data from Post Increment Register Indirect Address to Direct Address Assembler format DMOV R13 dir10 Operation R13 dir8 4 R13 4 R13 Flag change N Z V and C Unchanged Execution cycles 2a cycles Instruction format N Z V C MSB LSB 0 0 0 1 1 1 0 0 dir8 ...

Page 234: ...7 9 1 A F 8 9 4 7 9 1 A F 8 9 4 7 9 1 A F R13 00000054 FFFF1248 FFFF124C FFFF1248 FFFF124C 00000054 F F F F 1 2 4 8 R13 F F F F 1 2 4 C Instruction bit pattern 0001 1100 0001 0101 Memory Memory x x x x Before execution After execution x x x x x x x x x x x x x x x x x x x x ...

Page 235: ...ansfers word data at the direct address corresponding to 4 times the value of dir8 to the address indicated in R15 DMOV Move Word Data from Direct Address to Pre decrement Register Indirect Address Assembler format DMOV dir10 R15 Operation R15 4 R15 dir8 4 R15 Flag change N Z V and C Unchanged Execution cycles 2a cycles Instruction format N Z V C MSB LSB 0 0 0 0 1 0 1 1 dir8 ...

Page 236: ...2 8 2 A 9 8 2 A 2 8 2 A 9 8 2 A 2 8 2 A 9 R15 Memory 0000002C 7FFFFF84 7FFFFF88 0000002C 7 F F F F F 8 8 R15 Memory 7 F F F F F 8 4 Instruction bit pattern 0000 1011 0000 1011 7FFFFF84 7FFFFF88 x x x x x x x x x x x x x x x x x x x x x x x x Before execution After execution ...

Page 237: ...R15 to the direct address corresponding to 4 times the value dir8 After the data transfer it increments the value of R15 by 4 DMOV Move Word Data from Post Increment Register Indirect Address to Direct Address Assembler format DMOV R15 dir10 Operation R15 dir8 4 R15 4 R15 Flag change N Z V and C Unchanged Execution cycles 2a cycles Instruction format N Z V C MSB LSB 0 0 0 1 1 0 1 1 dir8 ...

Page 238: ...3 8 3 4 A 8 3 4 3 8 3 4 A 8 3 4 3 8 3 4 A R15 Memory 00000038 7FFEEE80 7FFEEE84 00000038 7 F F E E E 8 0 R15 Memory 7 F F E E E 8 4 Instruction bit pattern 0001 1011 0000 1110 7FFEEE80 7FFEEE84 x x x x Before execution After execution x x x x x x x x x x x x x x x x x x x x ...

Page 239: ... data DMOVH Move Half word Data from Direct Address to Register Assembler format DMOVH dir9 R13 Operation dir8 2 R13 Flag change N Z V and C Unchanged Execution cycles b cycle s Instruction format Example DMOVH 88H R13 N Z V C MSB LSB 0 0 0 0 1 0 0 1 dir8 R13 86 88 8A 86 88 8A x x x x x x x x x x x x x x x x x x x x x x x x R13 B 2 B 6 B 2 B 6 0 0 0 0 B 2 B 6 Instruction bit pattern 0000 1001 0100...

Page 240: ...ord Data from Register to Direct Address Assembler format DMOVH R13 dir9 Operation R13 dir8 2 Flag change N Z V and C Unchanged Execution cycles a cycle s Instruction format Example DMOVH R13 52H N Z V C MSB LSB 0 0 0 1 1 0 0 1 dir8 R13 50 52 54 50 52 54 x x x x x x x x x x x x x x x x x x x x R13 A E 8 6 F F F F A E 8 6 F F F F A E 8 6 Instruction bit pattern 0001 1001 0010 1001 Before execution ...

Page 241: ...responding to 2 times the value dir8 to the address indicated by R13 After the data transfer it increments the value of R13 by 2 DMOVH Move Half word Data from Direct Address to Post Increment Register Indirect Address Assembler format DMOVH dir9 R13 Operation dir8 2 R13 R13 2 R13 Flag change N Z V and C Unchanged Execution cycles 2a cycles Instruction format N Z V C MSB LSB 0 0 0 0 1 1 0 1 dir8 ...

Page 242: ...mple DMOVH 88H R13 1 3 7 4 R13 00000088 FF000052 FF000054 F F 0 0 0 0 5 2 R13 F F 0 0 0 0 5 4 Instruction bit pattern 0000 1101 0100 0100 1 3 7 4 1 3 7 4 00000088 FF000052 FF000054 Before execution After execution x x x x x x x x x x x x Memory Memory ...

Page 243: ...by R13 to the direct address corresponding to 2 times the value dir8 After the data transfer it increments the value of R13 by 2 DMOVH Move Half word Data from Post Increment Register Indirect Address to Direct Address Assembler format DMOVH R13 dir9 Operation R13 dir8 2 R13 2 R13 Flag change N Z V and C Unchanged Execution cycles 2a cycles Instruction format N Z V C MSB LSB 0 0 0 1 1 1 0 1 dir8 ...

Page 244: ...mple DMOVH R13 52H 8 9 3 3 R13 00000052 FF801220 FF801222 FF801220 FF801222 F F 8 0 1 2 2 0 R13 F F 8 0 1 2 2 2 Instruction bit pattern 0001 1101 0010 1001 8 9 3 3 8 9 3 3 00000052 x x x x x x x x x x x x Memory Memory Before execution After execution ...

Page 245: ...f data DMOVB Move Byte Data from Direct Address to Register Assembler format DMOVB dir8 R13 Operation dir8 R13 Flag change N Z V and C Unchanged Execution cycles b cycle s Instruction format Example DMOVB 91H R13 N Z V C MSB LSB 0 0 0 0 1 0 1 0 dir8 R13 Memory 90 91 92 90 91 92 x x x x x x x x x x x x x x x x R13 3 2 3 2 Memory 0 0 0 0 0 0 3 2 Instruction bit pattern 0000 1010 1001 0001 Before exe...

Page 246: ...te Data from Register to Direct Address Assembler format DMOVB R13 dir8 Operation R13 dir8 Flag change N Z V and C Unchanged Execution cycles a cycle s Instruction format Example DMOVB R13 53H N Z V C MSB LSB 0 0 0 1 1 0 1 0 dir8 R13 Memory 52 53 54 52 53 54 x x x x x x x x x x R13 F E Memory F F F F F F F E F F F F F F F E Instruction bit pattern 0001 1010 0101 0011 Before execution After executi...

Page 247: ...ndicated by the value dir8 to the address indicated by R13 After the data transfer it increments the value of R13 by 1 DMOVB Move Byte Data from Direct Address to Post Increment Register Indirect Address Assembler format DMOVB dir8 R13 Operation dir8 R13 R13 1 R13 Flag change N Z V and C Unchanged Execution cycles 2a cycles Instruction format N Z V C MSB LSB 0 0 0 0 1 1 1 0 dir8 ...

Page 248: ...RUCTIONS Example DMOVB 71H R13 9 9 R13 Memory 00000071 x x x x x x 88001234 88001235 8 8 0 0 1 2 3 4 R13 8 8 0 0 1 2 3 5 Instruction bit pattern 0000 1110 0111 0001 00000071 88001234 88001235 9 9 9 9 Memory Before execution After execution ...

Page 249: ...ted by R13 to the direct address indicated by the value dir8 After the data transfer it increments the value of R13 by 1 DMOVB Move Byte Data from Post Increment Register Indirect Address to Direct Address Assembler format DMOVB R13 dir8 Operation R13 dir8 R13 1 R13 Flag change N Z V and C Unchanged Execution cycles 2a cycles Instruction format N Z V C MSB LSB 0 0 0 1 1 1 1 0 dir8 ...

Page 250: ...RUCTIONS Example DMOVB R13 57H 5 5 5 5 5 5 R13 Memory 00000057 x x x x x x FF801220 FF801221 F F 8 0 1 2 2 0 R13 F F 8 0 1 2 2 1 Instruction bit pattern 0001 1110 0101 0111 00000057 FF801220 FF801221 Memory Before execution After execution ...

Page 251: ...bler format LDRES Ri u4 Operation Ri Resource on channel u4 Ri 4 Ri Flag change N Z V and C Unchanged Execution cycles a cycle s Instruction format Example LDRES R2 8 N Z V C MSB LSB 1 0 1 1 1 1 0 0 u4 Ri 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 R2 ch 8 Resource ch 8 Resource x x x x x x x x 12345678 1234567C 12345678 1234567C 1 2 3 4 5 6 7 8 R2 1 2 3 4 5 6 7 C Memory Memory Before executio...

Page 252: ...mbler format STRES u4 Ri Operation Resource on channel u4 Ri Ri 4 Ri Flag change N Z V and C Unchanged Execution cycles a cycle s Instruction format Example STRES 8 R2 N Z V C MSB LSB 1 0 1 1 1 1 0 1 u4 Ri 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 R2 ch 8 Resource ch 8 Resource x x x x x x x x 12345678 1234567C 12345678 1234567C 1 2 3 4 5 6 7 8 R2 1 2 3 4 5 6 7 C Memory Memory Before executi...

Page 253: ...e fields CC CRj and CRi is done by the coprocessor so that the detailed operation is determined by the specifications of the coprocessor If the coprocessor designated by the value u4 is not mounted a coprocessor not found trap is generated If the coprocessor designated by the value u4 has generated an error in a previous operation a coprocessor error trap is generated COPOP Coprocessor Operation A...

Page 254: ...CC set as shown in Table 7 116 1 will have the following effect on coprocessor operation Table 7 116 1 Conditions for Coprocessor Command CC COPOP CC Calculation 00 Addition CRi CRj CRi 01 Subtraction CRi CRj CRi 02 Multiplication CRi CRj CRi 03 Division CRi CRj CRi Other No operation MSB LSB 0 0 0 0 0 0 0 1 0 0 1 1 0 1 0 0 CR3 C 0 0 0 0 0 0 0 1 x 20 CR3 C 0 0 0 0 0 0 0 CR4 4 0 8 0 0 0 0 0 2 x 20 ...

Page 255: ...ote that the actual interpretation of the fields CC Rj CRi is done by the coprocessor so that the detailed actual operation is determined by the specifications of the coprocessor If the coprocessor designated by the value u4 is not mounted a coprocessor not found trap is generated If the coprocessor designated by the value u4 has generated an error in a previous operation a coprocessor error trap ...

Page 256: ...ecimal calculation unit the coprocessor command CC set as shown in Table 7 117 1 will have the following effect on coprocessor operation Table 7 117 1 Conditions for Coprocessor Command CC COPLD CC Calculation 00 Addition CRi CRj CRi 01 Subtraction CRi CRj CRi 02 Multiplication CRi CRj CRi 03 Division CRi CRj CRi Other No calculation MSB LSB 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 R8 3 F 8 0 0 0 0 0 CPU r...

Page 257: ...Note that the actual interpretation of the fields CC CRj Ri is done by the coprocessor so that the detailed actual operation is determined by the specifications of the coprocessor If the coprocessor designated by the value u4 is not mounted a coprocessor not found trap is generated If the coprocessor designated by the value u4 has generated an error in a previous operation a coprocessor error trap...

Page 258: ...l calculation unit the coprocessor command CC set as shown in Table 7 118 1 will have the following effect on coprocessor operation Table 7 118 1 Conditions for Coprocessor Command CC COPST CC Calculation 00 Addition CRi CRj CRi 01 Subtraction CRi CRj CRi 02 Multiplication CRi CRj CRi 03 Division CRi CRj CRi Other No calculation MSB LSB 0 0 0 0 0 1 0 0 0 0 1 0 0 1 0 0 R4 B F 8 0 0 0 0 0 R4 B F 8 0...

Page 259: ...processor so that the detailed actual operation is determined by the specifications of the coprocessor If the coprocessor designated by the value u4 is not mounted a coprocessor not found trap is generated However no coprocessor error trap will be generated even if the coprocessor designated by the value u4 has generated an error in a previous operation The operation of this instruction is basical...

Page 260: ...oprocessor indicated by channel 15 is a single precision floating decimal calculation unit the coprocessor command CC set as shown in Table 7 119 1 will have the following effect on coprocessor operation Table 7 119 1 Conditions for Coprocessor Command CC COPSV CC Calculation 00 Addition CRi CRj CRi 01 Subtraction CRi CRj CRi 02 Multiplication CRi CRj CRi 03 Division CRi CRj CRi Other No calculati...

Page 261: ...n Assembler format NOP Operation This instruction performs no operation Flag change N Z V and C Unchanged Execution cycles 1 cycle Instruction format Example NOP N Z V C MSB LSB 1 0 0 1 1 1 1 1 1 0 1 0 0 0 0 0 PC PC 8 3 4 3 8 3 4 C 8 3 4 3 8 3 4 A Before execution After execution Instruction bit pattern 1001 1111 1010 0000 ...

Page 262: ... Z V and C Varies according to results of calculation Execution cycles c cycle s The number of execution cycles is normally 1 However if the instruction immediately after involves read or write access to memory address R15 the system stack pointer SSP or the user stack pointer USP then an interlock is applied and the value becomes 2 cycles Instruction format Example ANDCCR 0FEH S I N Z V C C C C C...

Page 263: ... V and C Varies according to results of calculation Execution cycles c cycle s The number of execution cycles is normally 1 However if the instruction immediately after involves read or write access to memory address R15 the system stack pointer SSP or the user stack pointer USP then an interlock is applied and the value becomes 2 cycles Instruction format Example ORCCR 10H S I N Z V C C C C C C C...

Page 264: ...settings between 16 and 31 can be entered If the value u8 is in the range 0 to 15 the value 16 will be added to that data before being transferred to the ILM If the original ILM value is in the range 0 to 15 then any value between 0 and 31 can be transferred to the ILM STILM Set Immediate Data to Interrupt Level Mask Register Assembler format STILM u8 Operation u8 ILM Flag change N Z V and C Uncha...

Page 265: ...he value in R15 ADDSP Add Stack Pointer and Immediate Data Assembler format ADDSP s10 Operation R15 exts s8 4 R15 Flag change N Z V and C Unchanged Execution cycles 1 cycle Instruction format Example ADDSP 4 N Z V C MSB LSB 1 0 1 0 0 0 1 1 s8 R15 8 0 0 0 0 0 0 0 R15 7 F F F F F F C Instruction bit pattern 1010 0011 1111 1111 Before execution After execution ...

Page 266: ...ary value EXTSB Sign Extend from Byte Data to Word Data Assembler format EXTSB Ri Operation exts Ri Ri byte word Flag change N Z V and C Unchanged Execution cycles 1 cycle Instruction format Example EXTSB R1 N Z V C MSB LSB 1 0 0 1 0 1 1 1 1 0 0 0 Ri R1 0 0 0 0 0 0 A B R1 F F F F F F A B Before execution After execution Instruction bit pattern 1001 0111 1000 0001 ...

Page 267: ...inary value EXTUB Unsign Extend from Byte Data to Word Data Assembler format EXTUB Ri Operation extu Ri Ri byte word Flag change N Z V and C Unchanged Execution cycles 1 cycle Instruction format Example EXTUB R1 N Z V C MSB LSB 1 0 0 1 0 1 1 1 1 0 0 1 Ri R1 F F F F F F F F R1 0 0 0 0 0 0 F F Before execution After execution Instruction bit pattern 1001 0111 1001 0001 ...

Page 268: ...ary value EXTSH Sign Extend from Byte Data to Word Data Assembler format EXTSH Ri Operation exts Ri Ri half word word Flag change N Z V and C Unchanged Execution cycles 1 cycle Instruction format Example EXTSH R1 N Z V C MSB LSB 1 0 0 1 0 1 1 1 1 0 1 0 Ri R1 0 0 0 0 A B C D R1 F F F F A B C D Before execution After execution Instruction bit pattern 1001 0111 1010 0001 ...

Page 269: ...inary value EXTUH Unsigned Extend from Byte Data to Word Data Assembler format EXTUH Ri Operation extu Ri Ri half word word Flag change N Z V and C Unchanged Execution cycles 1 cycle Instruction format Example EXTUH R1 N Z V C MSB LSB 1 0 0 1 0 1 1 1 1 0 1 1 Ri R1 F F F F F F F F R1 0 0 0 0 F F F F Before execution After execution Instruction bit pattern 1001 0111 1011 0001 ...

Page 270: ...llowing operations are repeated according to the number of registers specified in the parameter reglist R15 Ri R15 4 R15 Flag change N Z V and C Unchanged Execution cycles If n is the number of registers specified in the parameter reglist the execution cycles required are as follows If n 0 1 cycle For other values of n a n 1 b 1 cycles Instruction format N Z V C Table 7 129 1 Bit Values and Regist...

Page 271: ... x 7FFFFFC0 7FFFFFC4 7FFFFFC8 R15 7 F F F F F C 0 R4 R3 Instruction bit pattern 1000 1100 0001 1000 9 0 B C 9 3 6 3 8 3 4 3 8 3 4 A 7FFFFFC0 7FFFFFC4 7FFFFFC8 R15 7 F F F F F C 8 8 3 4 3 8 3 4 A 9 0 B C 9 3 6 3 R4 R3 Memory Memory Before execution After execution x x x x x x x x x x x x x x x x x x x x x x x x ...

Page 272: ...tents of R15 will be read from memory LDM1 Load Multiple Registers Assembler format LDM1 reglist Operation The following operations are repeated according to the number of registers specified in the parameter reglist R15 Ri R15 4 R15 Flag change N Z V and C Unchanged Execution cycles If n is the number of registers specified in the parameter reglist the execution cycles required are as follows If ...

Page 273: ... 7 8 8 E 4 x x x x x x x x 7FFFFFC4 7FFFFFC8 7FFFFFCC R15 7 F F F F F C 0 R12 R10 Instruction bit pattern 1000 1101 0001 1100 9 0 B C 9 3 6 3 8 D F 7 8 8 E 4 7FFFFFC4 8 F E 3 9 E 8 A 7FFFFFC0 8 F E 3 9 E 8 A 7FFFFFC0 7FFFFFC8 7FFFFFCC R15 7 F F F F F C C 8 D F 7 8 8 E 4 8 F E 3 9 E 8 A R12 R10 R11 9 0 B C 9 3 6 3 R11 Memory Memory Before execution After execution x x x x x x x x x x x x x x x x x ...

Page 274: ...eglist Operation The following operations are repeated according to the number of registers specified in the parameter reglist R15 4 R15 Ri R15 Flag change N Z V and C Unchanged Execution cycles If n is the number of registers specified in the parameter reglist the execution cycles required are as follows a n 1 cycle Instruction format N Z V C Table 7 131 1 Bit Values and Register Numbers for regl...

Page 275: ... x 7FFFFFC0 7FFFFFC4 7FFFFFC8 R15 7 F F F F F C 8 R3 R2 Instruction bit pattern 1000 1110 0011 0000 9 0 B C 9 3 6 3 8 3 4 3 8 3 4 A 7FFFFFC0 7FFFFFC4 7FFFFFC8 R15 7 F F F F F C 0 8 3 4 3 8 3 4 A 9 0 B C 9 3 6 3 R3 R2 Memory Memory Before execution After execution x x x x x x x x x x x x x x x x x x x x x x x x ...

Page 276: ... to memory STM1 Store Multiple Registers Assembler format STM1 reglist Operation The following operations are repeated according to the number of registers specified in the parameter reglist R15 4 R15 Ri R15 Flag change N Z V and C Unchanged Execution cycles If n is the number of registers specified in the parameter reglist the execution cycles required are as follows a n 1 cycles Instruction form...

Page 277: ...F C C R12 R10 Instruction bit pattern 1000 1111 0011 1000 9 0 B C 9 3 6 3 8 D F 7 8 8 E 4 7FFFFFC4 8 F E 3 9 E 8 A 7FFFFFC0 8 F E 3 9 E 8 A 7FFFFFC0 7FFFFFC8 7FFFFFCC R15 7 F F F F F C 0 8 D F 7 8 8 E 4 8 F E 3 9 E 8 A R12 R10 R11 9 0 B C 9 3 6 3 R11 Memory Memory Before execution After execution x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x ...

Page 278: ...rame generation processing for high level languages The value u8 is calculated as an unsigned value ENTER Enter Function Assembler format ENTER u10 Operation R14 R15 4 R15 4 R14 R15 extu u8 4 R15 Flag change N Z V and C Unchanged Execution cycles 1 a cycles Instruction format N Z V C MSB LSB 0 0 0 0 1 1 1 1 u8 ...

Page 279: ... 0 0 7FFFFFF4 7FFFFFF0 7FFFFFEC 8 0 0 0 0 0 0 0 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 7 F F F F F F 4 R14 R15 7 F F F F F E C R15 7FFFFFF8 7FFFFFFC 80000000 7FFFFFF4 7FFFFFF0 7FFFFFEC Memory Memory Before execution After execution ...

Page 280: ...nstruction is used for stack frame release processing for high level languages LEAVE Leave Function Assembler format LEAVE Operation R14 4 R15 R15 4 R14 Flag change N Z V and C Unchanged Execution cycles b cycle s Instruction format N Z V C MSB LSB 1 0 0 1 1 1 1 1 1 0 0 1 0 0 0 0 ...

Page 281: ...0 8 0 0 0 0 0 0 0 x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x 8 0 0 0 0 0 0 0 R14 R15 7 F F F F F F 8 R15 7FFFFFF8 7FFFFFFC 80000000 7FFFFFF4 7FFFFFF0 7FFFFFEC Memory Memory Before execution After execution Instruction bit pattern 1001 1111 1001 0000 ...

Page 282: ...e address indicated by Rj and the data originally at Rj is extended with zeros and transferred to Ri The CPU will not accept hold requests between the memory read operation and the memory write operation of this instruction XCHB Exchange Byte Data Assembler format XCHB Rj Ri Operation Ri TEMP extu Rj Ri TEMP Rj Flag change N Z V and C Unchanged Execution cycles 2a cycles Instruction format N Z V C...

Page 283: ...XCHB R1 R0 R1 80000001 80000002 80000003 80000001 80000002 80000003 x x x x x x x x F D R1 7 8 8 0 0 0 0 0 0 2 8 0 0 0 0 0 0 2 R0 R0 0 0 0 0 0 0 F D 0 0 0 0 0 0 7 8 Memory Memory Before execution After execution Instruction bit pattern 1000 1010 0001 0000 ...

Page 284: ...260 CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS ...

Page 285: ...261 APPENDIX The appendix section includes lists of CPU instructions used in the FR family as well as instruction map diagrams APPENDIX A Instruction Lists APPENDIX B Instruction Maps ...

Page 286: ...DIX A Instruction Lists APPENDIX A Instruction Lists Appendix A includes a description of symbols used in instruction lists plus the instruction lists A 1 Symbols Used in Instruction Lists A 2 Instruction Lists ...

Page 287: ...0x1FC multiples of 4 dir8 unsigned 8 bit address values range 0 to 0xFF dir9 unsigned 9 bit address values range 0 to 0x1FE multiples of 2 dir10 unsigned 10 bit address values range 0 to 0x3FC multiples of 4 label9 signed 9 bit branch address range 0x100 to 0xFE multiples of 2 for the value of PC label12 signed 12 bit branch address range 0x800 to 0x7FE multiples of 2 for the value of PC Ri Rj ind...

Page 288: ... by Ready function b Memory access cycles may be increased by Ready function Note that if the next instruction references a register involved in a LD operation an interlock will be applied increasing the number of execution cycles from 1 cycle to 2 cycles c If the instruction immediately after is a read or write operation involving register R15 or the SSP or USP pointers or the instruction format ...

Page 289: ...dicated Register Transfer Instructions 5 Instructions Non delayed Branching Instructions 23 Instructions Delayed Branching Instructions 20 Instructions Direct Addressing Instructions 14 Instructions Resource Instructions 2 Instructions Coprocessor Instructions 4 Instructions Other Instructions 16 Instructions Instruction Lists Table A 2 1 Add Subtract Instructions 10 Instructions Mnemonic Format O...

Page 290: ...i Rj Ri Rj Ri Rj Ri Rj Word Word Half word Byte EOR Rj Ri EOR Rj Ri EORH Rj Ri EORB Rj Ri A A A A 9A 9C 9D 9E 1 1 2a 1 2a 1 2a CC CC CC CC Ri Rj Ri Rj Ri Rj Ri Rj Word Word Half word Byte Table A 2 4 Bit Operation Instructions 8 Instructions Mnemonic Format OP CYC FLAG NZVC Operation RMW Remarks BANDL u4 Ri u4 0 to 0FH BANDH u4 Ri u4 0 to 0FH C C 80 81 1 2a 1 2a Ri F0H u4 Lower 4 bit operation Hig...

Page 291: ...ons Mnemonic Format OP CYC FLAG NZVC Operation Remarks LSL Rj Ri LSL u4 Ri LSL2 u4 Ri A C C B6 B4 B5 1 1 1 CC C CC C CC C Ri Rj Ri Ri u4 Ri Ri u4 16 Ri Logical shift LSR Rj Ri LSR u4 Ri LSR2 u4 Ri A C C B2 B0 B1 1 1 1 CC C CC C CC C Ri Rj Ri Ri u4 Ri Ri u4 16 Ri Logical shift ASR Rj Ri ASR u4 Ri ASR2 u4 Ri A C C BA B8 B9 1 1 1 CC C CC C CC C Ri Rj Ri Ri u4 Ri Ri u4 16 Ri Arithmetic shift Table A 2...

Page 292: ...isp6 Ri LD R15 Ri LD R15 Rs LD R15 PS A A B C E E E 04 00 20 03 07 0 07 8 07 9 b b b b b b 1 a b CCCC Rj Ri R13 Rj Ri R14 disp10 Ri R15 udisp6 Ri R15 Ri R15 4 R15 Rs R15 4 R15 PS R15 4 Rs dedicated register LDUH Rj Ri LDUH R13 Rj Ri LDUH R14 disp9 Ri A A B 05 01 40 b b b Rj Ri R13 Rj Ri R14 disp9 Rj Zero extension Zero extension Zero extension LDUB Rj Ri LDUB R13 Rj Ri LDUB R14 disp8 Ri A A B 06 0...

Page 293: ...5 R15 4 PS R15 Word Word Word Rs dedicated register STH Ri Rj STH Ri R13 Rj STH Ri R14 disp9 A A B 15 11 50 a a a Ri Rj Ri R13 Rj Ri R14 disp9 Half word Half word Half word STB Ri Rj STB Ri R13 Rj STB Ri R14 disp8 A A B 16 12 70 a a a Ri Rj Ri R13 Rj Ri R14 disp8 Byte Byte Byte disp8 o8 disp8 disp9 o8 disp9 1 disp10 o8 disp10 2 udisp6 u4 udisp6 2 Table A 2 10 Inter register Transfer Instructions D...

Page 294: ... 4 PS SSP SSP 4 PC 2 SSP 0 I flag 0 S flag TBR 3FC u8 4 PC INTE E 9F 3 3 3a SSP 4 PS SSP SSP 4 PC 2 SSP 0 S flag 4 ILM TBR 3D8 u8 4 PC RETI E 97 3 2 2a CCCC R15 PC R15 4 R15 PS R15 4 BNO label9 BRA label9 BEQ label9 BNE label9 BC label9 BNC label9 BN label9 BP label9 BV label9 BNV label9 BLT label9 BGE label9 BLE label9 BGT label9 BLS label9 BHI label9 D D D D D D D D D D D D D D D D E1 E0 E2 E3 E...

Page 295: ... Delayed Branching Instructions 20 Instructions Mnemonic Format OP CYC FLAG NZVC Operation Remarks JMP D Ri E 9F 0 1 Ri PC CALL D label12 CALL D Ri F E D8 9F 1 1 1 PC 4 RP PC 2 rel11 2 PC PC 4 RP Ri PC RET D E 9F 2 1 RP PC Return BNO D label9 BRA D label9 BEQ D label9 BNE D label9 BC D label9 BNC D label9 BN D label9 BP D label9 BV D label9 BNV D label9 BLT D label9 BGE D label9 BLE D label9 BGT D...

Page 296: ...a 2a 2a dir9 R13 R13 dir9 dir9 R13 R13 2 R13 dir9 R13 2 Half word Half word Half word Half word DMOVB dir8 R13 DMOVB R13 dir8 DMOVB dir8 R13 DMOVB R13 dir8 D D D D 0A 1A 0E 1E b a 2a 2a dir8 R13 R13 dir8 dir8 R13 R13 R13 dir8 R13 Byte Byte Byte Byte dir8 dir dir8 dir9 dir dir9 1 dir10 dir dir10 2 Table A 2 14 Resource Instructions 2 Instructions Mnemonic Format OP CYC FLAG NZVC Operation Remarks L...

Page 297: ... FLAG NZVC Operation RMW Remarks NOP E 9F A 1 No change ANDCCR u8 ORCCR u8 D D 83 93 c c CCCC CCCC CCR and u8 CCR CCR or u8 CCR STILM u8 D 87 1 u8 ILM Sets ILM immediate value ADDSP s10 D A3 1 R15 s10 ADD SP instruction EXTSB Ri EXTUB Ri EXTSH Ri EXTUH Ri E E E E 97 8 97 9 97 A 97 B 1 1 1 1 Sign extension 8 32bit Zero extension 8 32bit Sign extension 16 32bit Zero extension 16 32bit LDM0 reglist L...

Page 298: ...274 APPENDIX B Instruction Maps APPENDIX B Instruction Maps This appendix presents FR family instruction map and E format B 1 Instruction Map B 2 E Format ...

Page 299: ...Rj ANDH Rj Ri ORH Rj Ri ADD2 i4 Ri LSL2 u4 Ri BNC label9 BNC D label9 6 LDUB Rj Ri STB Ri Rj ANDB Rj Ri ORB Rj Ri ADD Rj Ri LSL Rj Ri BN label9 BN D label9 7 E format E format STILM u8 E format ADDC Rj Ri MOV Rs Ri BP label9 BP D label9 8 DMOV d10 R13 DMOV R13 d10 BTSTL u4 Ri BEORL u4 Ri CMP i4 Ri ASR u4 Ri CALL D label12 BV label9 BV D label9 9 DMOVH R13 DMOVH R13 d9 BTSTH u4 Ri BEORH u4 Ri CMP2 ...

Page 300: ...ower 4 bits 0 LD R15 Ri ST Ri R15 JMP Ri JMP D Ri 1 MOV Ri PS MOV PS Ri CALL Ri CALL D Ri 2 RET RET D 3 RETI INTE 4 DIV0S Ri 5 DIV0U Ri 6 DIV1 Ri DIV3 7 DIV2 Ri DIV4S 8 LD R15 Rs ST Rs R15 EXTSB Ri LDI 32 i32 Ri 9 LD R15 PS ST PS R15 EXTUB Ri LEAVE A EXTSH Ri NOP B EXTUH Ri C COPOP u4 CC CRj CRi D COPLD u4 CC Rj CRi E COPST u4 CC CRj Ri F COPSV u4 CC CRj Ri ...

Page 301: ...277 INDEX INDEX The index follows on the next page This is listed in alphabetical order ...

Page 302: ...to Data in Memory 90 And Condition Code ANDCCR And Condition Code Register and Immediate Data 238 And Half word Data ANDH And Half word Data of Source Register to Data in Memory 88 And Word Data AND And Word Data of Source Register to Data in Memory 86 AND And Word Data of Source Register to Destination Register 85 ANDB ANDB And Byte Data of Source Register to Data in Memory 90 ANDCCR ANDCCR And C...

Page 303: ...t 07 to bit 00 21 COPLD COPLD Load 32 bit Data from Register to Coprocessor Register 231 COPOP COPOP Coprocessor Operation 229 Coprocessor PC Values Saved for Coprocessor Error Traps 49 PC Values Saved for Coprocessor Not Present Traps 48 Conditions for Generation of Coprocessor Error Traps 49 Conditions for Generation of Coprocessor Not Found Traps 48 COPLD Load 32 bit Data from Register to Copro...

Page 304: ...dress Area 7 DMOV Move Word Data from Direct Address to Post Increment Register Indirect Address 207 DMOV Move Word Data from Direct Address to Pre decrement Register Indirect Address 211 DMOV Move Word Data from Direct Address to Register 205 DMOV Move Word Data from Register to Direct Address 206 DMOVB Move Byte Data from Direct Address to Post Increment Register Indirect Address 223 DMOVB Move ...

Page 305: ...ed Instruction Exceptions 43 Factors Causing Exception Processing 42 How to Use Undefined Instruction Exceptions 43 Operations of Undefined Instruction Exceptions 43 Overview of Exception Processing 42 Overview of Undefined Instruction Exceptions 43 Time to Start of Undefined Instruction Exception Processing 43 Exchange Byte Data XCHB Exchange Byte Data 258 Exclusive Or Byte Data EORB Exclusive Or...

Page 306: ...ation 46 PC Values Saved for INT Instruction Execution 45 PC Values Saved for INTE Instruction Execution 46 PC Values Saved for Undefined Instruction Exceptions 43 Examples of Processing Delayed Branching Instructions 61 Examples of Processing Non delayed Branching Instructions 60 Examples of Programing Delayed Branching Instructions 62 General purpose Registers during Execution of COPST COPSV Ins...

Page 307: ... on Interrupts during Processing of Delayed Branching Instructions 59 RETI Return from Interrupt 192 Sources of Interrupts 37 Time to Start of Interrupt Processing 39 Time to Start of Non maskable Interrupt Processing 40 Interrupt Level Mask Register Interrupt Level Mask Register ILM Bit 20 to bit 16 19 STILM Set Immediate Data to Interrupt Level Mask Register 240 J JMP JMP Jump 184 JMP D Jump 196...

Page 308: ...om Direct Address to Post Increment Register Indirect Address 217 DMOVH Move Half word Data from Direct Address to Register 215 DMOVH Move Half word Data from Post Increment Register Indirect Address to Direct Address 219 DMOVH Move Half word Data from Register to Direct Address 216 Move Word Data DMOV Move Word Data from Direct Address to Post Increment Register Indirect Address 207 DMOV Move Wor...

Page 309: ...yte Data of Source Register to Data in Memory 97 ORCCR ORCCR Or Condition Code Register and Immediate Data 239 ORH ORH Or Half word Data of Source Register to Data in Memory 95 P PC PC Values Saved for INT Instruction Execution 45 PC Values Saved for INTE Instruction Execution 46 PC Values Saved for Coprocessor Error Traps 49 PC Values Saved for Coprocessor Not Present Traps 48 PC Values Saved for...

Page 310: ... Direction 141 142 LSR2 Logical Shift to the Right Direction 143 S Sample Sample Configuration of an FR Family Device 3 Sample Configuration of the FR Family CPU 4 Save COPSV Save 32 bit Data from Coprocessor Register to Register 235 Saving Saving and Restoring Coprocessor Error Information 50 SCR System Condition Code Register SCR Bit 10 to bit 08 20 Set Immediate Data STILM Set Immediate Data to...

Page 311: ... to NMI and External Interrupts 47 Step Trace Trap Operation 47 Stepwise Division Programs Interrupts during Execution of Stepwise Division Programs 37 STH STH Store Half word Data in Register to Memory 172 173 174 STILM STILM Set Immediate Data to Interrupt Level Mask Register 240 STM STM0 Store Multiple Registers 250 STM1 Store Multiple Registers 252 Store COPST Store 32 bit Data from Coprocesso...

Page 312: ...Operation 47 Time to Start of Trap Processing for INT Instructions 45 Time to Start of Trap Processing for INTE Instructions 46 U Undefined Instruction Exception PC Values Saved for Undefined Instruction Exceptions 43 How to Use Undefined Instruction Exceptions 43 Operations of Undefined Instruction Exceptions 43 Overview of Undefined Instruction Exceptions 43 Time to Start of Undefined Instructio...

Page 313: ...E FUJITSU SEMICONDUCTOR CONTROLLER MANUAL FR Family 32 BIT MICROCONTROLLER INSTRUCTION MANUAL December 2007 the fifth edition Published FUJITSU LIMITED Electronic Devices Edited Strategic Business Development Dept ...

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