D1271/D1291 CUV-LSV/CUV-LV User’s Manual 57
4. BIOS SETUP
4. BIOS SETUP
SDRAM Active to Precharge Time
To make changes to this field, set the SDRAM Configuration field to
[User Defined].
Read Around Write [Enabled]
Setting this field to [Enabled] allows the memory controller to store write
data in its buffer whenever the CPU issues a write command. The next time
the CPU needs the data, it retrieves the data from the memory buffer without
accessing the SDRAM. Configuration options: [Disabled] [Enabled]
CPU-DRAM Back-Back Transaction [Enabled]
Configuration options: [Enabled] [Disabled]
Delayed Transaction [Disabled]
When set to [Enabled], this feature frees the PCI bus when the CPU is
accessing 8-bit ISA cards. This process normally consumes about 50-60
PCI Clocks without PCI delayed transaction. Set this field to [Disabled]
when using ISA cards that are not PCI 2.1 compliant. Configuration options:
[Enabled] [Disabled]
PCI to DRAM Prefetch [Disabled]
Configuration options: [Disabled] [Enabled]
Byte Merge [Disabled]
To optimize the data transfer on PCI, this feature combines a sequence of
individual memory writes (bytes or words) into a single 32-bit block of
data. However, byte merging may only be done when the bytes within a
data phase are in a prefetchable address range. Configuration options:
[Disabled] [Enabled]
DRAM Read Latch Delay [1 ns]
Configuration options: [0.0 ns] [0.5 ns] [1.0 ns] [1.5 ns]
AGP Capability [4X Mode]
This motherboard supports the AGP 4x interface that transfers video data at
1066MB/s. AGP 4x is backward-compatible, so you may leave the default
[4X Mode] on even if you are using an AGP 1x or 2x video card. When set
to [1X Mode], the AGP interface only provides a peak data throughput of
266MB/s even if you are using an AGP 2x/4x card. When set to [2X Mode],
the AGP interface only provides a peak data throughput of 533MB/s even if
you are using an AGP 4x card. Configuration options: [1X Mode] [2X Mode]
[4X Mode]
Chip Configuration
Summary of Contents for D1271
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