FTDI Vinculum-II VNC2-32L1B Manual Download Page 27

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Datasheet

Vinculum-II Embedded Dual USB Host Controller

Version 1.6

Document No.: FT_000138 Clearance No.: FTDI# 143

Figure 5.3 expands upon Figure 5.2 by moving the UART, SPI slave0 and SPI master signals to differing
IOBUS positions. The purpose of this diagram to highlight peripherals connected to differing IOBUS
positions.

IOBUS0

IOBUS1

IOBUS2

IOBUS3

IOBUS4

IOBUS5

IOBUS6

IOBUS7

IOBUS8

IOBUS9

IOBUS10

IOBUS11

IOBUS12

IOBUS13

IOBUS14

IOBUS15

IOBUS16

IOBUS17

IOBUS18

IOBUS19

IOBUS20

IOBUS21

IOBUS22

IOBUS23

IOBUS24

IOBUS25

IOBUS26

IOBUS27

IOBUS28

IOBUS29

IOBUS30

IOBUS31

IOBUS43

uart_txd

uart_rxd

uart_rts#

uart_cts#

uart_dtr#

uart_dsr#

uart_dcd#

uart_ri#

uart_tx_active

spi_s0_clk

spi_s0_mosi

spi_s0_miso

spi_s0_ss#

spi_s1_clk

spi_s1_mosi

spi_s1_miso

spi_s1_ss#

spi_m_clk

spi_m_mosi

spi_m_miso

spi_m_ss_0#

spi_m_ss_1#

Peripheral Pin

IOBUS Pin

gpio[A0]

gpio[A1]

gpio[A2]

gpio[A3]

gpio[A4]

gpio[A5]

gpio[A6]

gpio[A7]

gpio[E7]

Figure 5.3 IOBUS to UART, SPI slave0 and SPI master second example

Summary of Contents for Vinculum-II VNC2-32L1B

Page 1: ...RAM 4k x 32 bits Programmable UART up to 6Mbaud Two SPI Serial Peripheral slave interfaces and one SPI master interface Reduced power modes capability Variable instruction length Native support for 8...

Page 2: ...one to USB Flash drive GPS to mobile phone interface Instrumentation USB Flash drive Data logger USB Flash drive Set Top Box USB device interface GPS tracker with USB Flash disk storage USB webcam Fla...

Page 3: ...FIFO Interface SPI Slave 0 SPI Slave 1 General Purpose Timers GPIOS Input Output Multiplexer USB Host Device Controller Peripheral Bus DMA 3 DMA 2 Data Memory Bus 16K Bytes Data Ram 4K x 32 Embedded...

Page 4: ...mbol 48 Pin 14 3 9 VNC2 Schematic symbol 64 Pin 15 3 10 Pin Configuration USB and Power 16 3 11 Miscellaneous Signals 17 3 12 Pin Configuration Input Output 18 4 Function Description 21 4 1 Key Featur...

Page 5: ...3 6 VNC1L Legacy Interface 48 6 4 Serial Peripheral Interface SPI Master 53 6 4 1 SPI Master Signal Descriptions 53 6 5 Debugger Interface 56 6 5 1 Debugger Interface Signal description 56 6 6 Paralle...

Page 6: ...Package Dimensions 74 11 3 VNC2 QFN 32 Package Dimensions 75 11 4 VNC2 LQFP 48 Package Dimensions 76 11 5 VNC2 QFN 48 Package Dimensions 77 11 6 VNC2 LQFP 64 Package Dimensions 78 11 7 VNC2 QFN 64 Pac...

Page 7: ...pin QFN Figure 3 3 shows how the VNC2 pins map to the VNC1L pins VNC2 pins labelled in bold text 3 1 Pin Out 32 pin LQFP FTDI XXXXXXXXXX VNC2 32L1A YYWW GND Core USB1DP USB1DM USB2DP USB2DM VCCIO 3 3...

Page 8: ...VREG OUT 1 8V VCC PLL IN XTIN XTOUT GND PLL 3 3V VREG IN NC 25 26 27 28 29 30 31 32 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 17 18 19 20 21 22 23 24 GND Core IO BUS6 IO BUS7 IO BUS8 IO BUS11 IO BUS10 I...

Page 9: ...BDBUS3 VCCIO BDBUS6 BDBUS7 BCBUS0 BCBUS1 BCBUS2 BCBUS3 GND IO IO BUS2 IO BUS5 IO BUS4 IO BUS3 VCCIO 3 3V IO BUS6 IO BUS7 IO BUS8 IO BUS9 IO BUS10 IO BUS11 GND VCC AVCC XTIN XTOUT AGND PLLFLTR TEST RE...

Page 10: ...BUS1 2 1 4 3 5 7 6 8 9 11 10 12 FTDI XXXXXXXXXX VNC2 48Q1A YYWW IOBUS2 IOBUS3 IOBUS4 IOBUS5 VCCIO 3 3 V IOBUS6 IOBUS7 IOBUS8 IOBUS9 IOBUS10 IOBUS11 GND IO 13 14 15 16 17 18 19 20 21 22 23 24 USB1DM US...

Page 11: ...IO BUS36 IO BUS35 VCCIO 3 3V GND Core 3 3V VREG IN 1 8V VCC PLL IN XTIN XTOUT GND PLL 1 8V VREG OUT NC RESET PROG IO BUS0 IO BUS1 GND IO IO BUS5 IO BUS2 IO BUS3 IO BUS4 IO BUS11 IO BUS12 IO BUS13 IO B...

Page 12: ...O 3 3V IOBUS10 GND IO 19 20 21 22 23 24 25 26 27 28 29 30 17 18 31 32 IOBUS6 IOBUS7 IOBUS11 IOBUS12 IOBUS13 IOBUS14 IOBUS15 IOBUS16 IOBUS17 IOBUS18 IOBUS19 43 44 41 42 40 38 39 37 36 34 35 33 47 48 45...

Page 13: ...ic symbol 32 Pin V C C I O V C C I O V C C I O V R E G I N 18 17 8 USB1DP USB1DM RESET PROG VREG OUT NC USB2DP USB2DM 4 5 XTIN XTOUT VNC2 32 Pin 7 10 9 21 20 28 22 13 3 N G N D G N D G D G N D 27 19 1...

Page 14: ...NC USB2DP USB2DM 4 5 XTIN XTOUT VNC2 48 Pin 7 10 9 29 28 40 30 17 2 3 N G N D G N D G D G N D 39 27 24 6 11 12 13 14 IOBUS0 IOBUS1 IOBUS2 IOBUS3 15 16 18 19 IOBUS7 IOBUS6 IOBUS5 IOBUS4 20 21 22 23 IO...

Page 15: ...G N D 53 35 30 6 11 12 13 14 IOBUS0 IOBUS1 IOBUS2 IOBUS3 15 16 17 18 IOBUS7 IOBUS6 IOBUS5 IOBUS4 19 20 22 23 IOBUS8 IOBUS9 IOBUS10 IOBUS11 24 25 26 27 IOBUS15 IOBUS14 IOBUS13 IOBUS12 28 29 31 32 IOBU...

Page 16: ...Name Type Description 64 pin 48 pin 32 pin 1 30 35 53 1 24 27 39 1 16 19 27 GND PWR Device ground supply pins 2 2 2 3 3V VREGIN PWR 3 3V supply to the regulator 3 3 3 1 8V VCC PLL IN PWR 1 8V supply...

Page 17: ...s pins 4 and 5 If driven by an external source reference to 1 8V VCC PLL IN 5 5 5 XTOUT Output Output from 12MHz Oscillator Cell Connect 12MHz crystal across pins 4 and 5 No connect if XTIN is driven...

Page 18: ...only available when the I O Mux is enabled A blank VNC2 chip defaults to all I O pins as inputs Pin No Name VINC1 L 64 Pin Default 48 Pin Default 32 PIN Default Type Description 64 Pin 48 Pin 32 Pin...

Page 19: ...BUS7 Input uart_ri I O GPIO 39 41 IOBUS20 ACBUS0 uart_txd uart_tx_active I O GPIO 40 42 IOBUS21 ACBUS1 uart_rxd gpio A5 I O GPIO 41 43 IOBUS22 ACBUS2 uart_rts gpio A6 I O GPIO 42 44 IOBUS23 ACBUS3 uar...

Page 20: ...Name VINC1 L 64 Pin Default 48 Pin Default 32 PIN Default Type Description 64 Pin 48 Pin 32 Pin 58 IOBUS37 spi_s1_mosi I O GPIO 59 IOBUS38 spi_s1_miso I O GPIO 60 IOBUS39 spi_s1_ss I O GPIO 61 IOBUS4...

Page 21: ...ded microprocessor core and dual USB interfaces large RAM and Flash capacity and the ability to develop and customise firmware using the VNC2 Toolchain VNC2 has an enhanced feature list over and above...

Page 22: ...per package are as follows 32 pin package 12 I O pins 48 pin package 28 I O pins 64 pin package 44 I O pins Table 4 1 lists the peripherals which can be multiplexed to I O and the maximum number of pi...

Page 23: ...eceivers provide USB DATA IN SE0 and USB Reset condition detection These cells also include integrated internal USB pull up or pull down resistors as required for host or slave mode 4 2 9 USB Host Dev...

Page 24: ...peripheral signal is allocated to group 0 then it can connect to IOBUS0 IOBUS4 IOBUS8 IOBUS12 and so on If a peripheral signal is allocated to group 1 then it can connect to IOBUS1 IOBUS5 IOBUS9 IOBUS...

Page 25: ...BUS3 IOBUS4 IOBUS5 IOBUS6 IOBUS7 IOBUS8 IOBUS9 IOBUS10 IOBUS11 IOBUS12 IOBUS13 IOBUS14 IOBUS15 IOBUS16 IOBUS17 IOBUS18 IOBUS19 IOBUS20 IOBUS21 IOBUS43 uart_txd uart_rxd uart_rts uart_cts uart_dtr uart...

Page 26: ...2 IOBUS13 IOBUS14 IOBUS15 IOBUS16 IOBUS17 IOBUS18 IOBUS19 IOBUS20 IOBUS21 IOBUS22 IOBUS23 IOBUS24 IOBUS25 IOBUS26 IOBUS27 IOBUS28 IOBUS29 IOBUS30 IOBUS31 IOBUS43 uart_txd uart_rxd uart_rts uart_cts ua...

Page 27: ...US4 IOBUS5 IOBUS6 IOBUS7 IOBUS8 IOBUS9 IOBUS10 IOBUS11 IOBUS12 IOBUS13 IOBUS14 IOBUS15 IOBUS16 IOBUS17 IOBUS18 IOBUS19 IOBUS20 IOBUS21 IOBUS22 IOBUS23 IOBUS24 IOBUS25 IOBUS26 IOBUS27 IOBUS28 IOBUS29 I...

Page 28: ...ted to 3 GPIO pins Note that GPIO pins A0 and A4 are unused as a sufficient gap wasn t available IOBUS0 IOBUS1 IOBUS2 IOBUS3 IOBUS4 IOBUS5 IOBUS6 IOBUS7 IOBUS8 IOBUS9 IOBUS10 IOBUS11 IOBUS12 IOBUS13 I...

Page 29: ...n be read by strobing RD low then high fifo_wr 0 1 Writes the data byte on the D0 D7 pins into the transmit FIFO buffer when WR goes from high to low fifo_rd 0 1 Enables the current FIFO data byte on...

Page 30: ...lity is shown in figure 5 5 below The IOMux utility user guide is available to download VINCULUM II IO_Mux Configuration Utility User Guide The following tables provide a lookup guide to determine wha...

Page 31: ...B4 gpio C0 gpio C4 gpio D0 gpio D4 gpio E0 gpio E4 debug_if uart_txd uart_dtr uart_tx_active fifo_data 0 fifo_data 4 fifo_rxf pwm 0 pwm 4 spi_m_clk spi_m_ss_1 gpio A0 gpio A4 gpio B0 gpio B4 gpio C0 g...

Page 32: ...io B5 gpio C1 gpio C5 gpio D1 gpio D5 gpio E1 gpio E5 fifo_data 1 fifo_data 5 fifo_txe pwm 1 pwm 5 spi_s0_mosi spi_s1_mosi spi_m_mosi fifo_clkout gpio A1 gpio A5 gpio B1 gpio B5 gpio C1 gpio C5 gpio D...

Page 33: ...pio A6 gpio B2 gpio B6 gpio C2 gpio C6 gpio D2 gpio D6 gpio E2 gpio E6 uart_rts fifo_data 2 fifo_data 6 pwm 2 pwm 6 spi_s0_miso spi_s1_miso gpio A2 gpio A6 gpio B2 gpio B6 gpio C2 gpio C6 gpio D2 gpio...

Page 34: ...s gpio A3 gpio A7 gpio B3 gpio B7 gpio C3 gpio C7 gpio D3 gpio D7 gpio E3 gpio E7 fifo_data 3 fifo_data 7 pwm 3 pwm 7 spi_m_ss_0 gpio A3 gpio A7 gpio B3 gpio B7 gpio C3 gpio C7 gpio D3 gpio D7 gpio E3...

Page 35: ...be used to select where the UART interface can be placed Figure 5 6 shows the four UART signal selected on pins 11 12 13 14 however they could have been selected on any of the other four pins highlig...

Page 36: ...485 The UART can support baud rates from 183 baud to 6 Mbaud The maximum UART speed is determined by the CPU speed 8 The CPU can be run at three frequecies therefore the following maximum rates apply...

Page 37: ...Transmit asynchronous data output 12 16 20 25 29 40 44 48 52 58 62 12 16 21 32 36 42 46 12 24 30 uart_rxd Input Receive asynchronous data input 13 17 22 26 31 41 45 49 55 59 63 13 18 22 33 37 43 47 14...

Page 38: ...15 20 31 35 41 45 11 23 29 uart_tx_active Output Enable transmit data for RS485 designs This signal may be used to signal that a transmit operation is in progress The uart_tx_active signal will be set...

Page 39: ...maximum clock to 12Mhz Lowest power mode 12Mhz would set the SPI maximum clock to 6hMz Module Signal Name Type Description SPI Slave 0 spi_s0_clk Input Clock input slave 0 spi_s0_ss Input Active low c...

Page 40: ...O Multiplexer 6 2 1 SPI Clock Phase Modes SPI interface has 4 unique modes of clock phase CPHA and clock polarity CPOL known as Mode 0 Mode 1 Mode 2 and Mode 3 Table 6 4 summarizes these modes and ava...

Page 41: ...trolled by the internal CPU using internal memory mapped I O registers It operates from the main system clock although sampling of input data and transmission of output data is controlled by the SPI c...

Page 42: ...11 15 20 31 35 41 45 11 23 29 spi_s0_clk spi_s1_clk Input Slave clock input 12 16 20 25 29 40 44 48 52 58 62 12 16 21 32 36 42 46 12 24 30 spi_s0_mosi spi_s1_mosi Input Mater Out Slave In Synchronous...

Page 43: ...an receive more data the master can continue to stream further write bytes Figure 6 5 is an example of this SS MISO MOSI 8 bit CMD W0 W1 W2 STATUS STATUS STATUS STATUS Figure 6 5 Full Duplex Data Mast...

Page 44: ...g used in a multi slave environment This would typically be used in the scenario where a shared data bus is used R W Set to 1 for a read and 0 for a write Z Tri stated TXE Transmit Empty When 1 the Sl...

Page 45: ...llow this up with a byte of write data If the status continues to indicate that more data can be written a whole stream of data can be written following one single command The operation completes when...

Page 46: ...be changed to an output again and data will be sent from Master to Slave Following this data the Slave will send a further status byte if SS remains active If the status indicates that more data can b...

Page 47: ...pi_slave_data_tx register This will then be moved into the transfer shift register to wait for the SPI Master to request it The SPI Master will at some point assert SS and start clocking data on MOSI...

Page 48: ...uctions on whether a read or write is requested and if data or status is to be sent For a data write 8 bits of data are sent on MOSI followed by a status bit being returned on MISO If this bit is 0 it...

Page 49: ...When 1 it means a read contains old data or a write did not work and needs retried Table 6 7 SPI Command and Status Fields 6 3 6 1 SPI Setup Bit Encoding The VNC1L compatible SPI interface differs fro...

Page 50: ...6 16 SPI Slave Mode Timing Table 6 9 SPI Slave Data Timing 6 3 6 2 SPI Master Data Read Transaction in VNC1L legacy mode The SPI master must periodically poll for new data in VNC2 Transmit Buffer It i...

Page 51: ...e is sent by the SPI master to VNC2 see Figure 6 18 This is followed by the SPI master transmitting each bit of the data to be written to VNC2 The VNC2 then responds with a status bit on MISO on the r...

Page 52: ...r This is followed by a status bit generated by VNC2 also on the MISO which will always be zero indicating new data The meaning of the bits within the status byte sent by VNC2 during a Status Read ope...

Page 53: ...tween negative edge of slave select and start of transfer SD Card interface An interface that s compatible with the VLSI VS1033 SCI mode used for VMUSIC capability The SPI Master only clocks in and ou...

Page 54: ...spi_m_ss_1 Output Active low slave select 1 from master to slave 1 Table 6 13 SPI Master Signal Names The main purpose of the SPI Master block is to transfer data between an external SPI interface an...

Page 55: ...FTDI 143 Figure 6 21 Typical SPI Master Timing Table 6 14 SPI Master Timing Time Description Minimum Typical Maximum Unit t1 SCLK period 39 68 41 67 ns t2 SCLK high period 19 84 20 84 21 93 ns t3 SCL...

Page 56: ...tepped and can be halted Detailed internal debug memory read write access The single wire interface has the following features Half Duplex Operation 1Mbps speed 1 start bit 1 stop bit 8 data bits Pull...

Page 57: ...ble 6 16 They can be programmed to a choice of I O pins depending on the package size Further details on the configuration of input and output signals are available in Section 5 I O Multiplexer 64 Pin...

Page 58: ...fifo_data 4 I O FIFO Data Bus Bit 4 12 16 20 25 29 40 44 48 52 58 62 12 16 21 32 36 42 46 12 24 30 fifo_data 5 I O FIFO Data Bus Bit 5 13 17 22 26 31 41 45 49 55 59 63 13 18 22 33 37 43 47 14 25 31 f...

Page 59: ...26 32 fifo_wr Input Writes the data byte on the D0 D7 pins into the transmit FIFO buffer when fifo_wr goes from high to low Table 6 16 Data and Control Bus Signal Mode Options Parallel FIFO Interface...

Page 60: ...ion Minimum Maximum Unit t1 RD inactive to RXF 1 14 ns t2 RXF inactive after RD cycle 100 ns t3 RD to DATA 1 14 ns t4 RD active pulse width 30 ns t5 RD active after RXF 0 ns t6 WR active to TXE inacti...

Page 61: ...e and a clock out The synchronous FIFO mode uses the parallel FIFO interface signals detailed in Table 6 16 and an additional two signals detailed in Table 6 18 This mode is not available on the 32 pi...

Page 62: ...ming In synchronous mode data can be transmitted to and from the FIFO module on each clock edge An external device synchronises to the CLKOUT output and it also has access to the output enable OE inpu...

Page 63: ...Write DATA hold time 0 ns t13 WR setup time 12 ns t14 WR hold time 0 ns Table 6 19 Synchronous FIFO mode Read Write Timing 6 8 General Purpose Timers In VNC2 there are 4 General Purpose Timers availa...

Page 64: ...are connected to Ports A through E These ports are controlled by the VNC2 CPU All ports are configurable to be either inputs or outputs and allow level or edge driven interrupts to be generated To si...

Page 65: ...eed transactions Control transfer Used to transfer specific requests to all types USB devices most commonly used during device configuration VNC2 control transfers are valid for low and full speed tra...

Page 66: ...he basic hardware device driver functionality for a specific purpose For example drivers for standard USB device classes may be created which build upon the USB host hardware driver to implement a BOM...

Page 67: ...tion path from VNC1L designs with VDAP firmware V2DPS firmware USB Host for single Flash Disk and general purpose USB peripherals and USB peripheral emulating a FT232 on a Host computer Offers a migra...

Page 68: ...mperature Power Applied 40 to 85 C Vcc Supply Voltage 0 to 3 63 V VCC_IO 0 to 3 63 V VCC_PLL_IN 0 to 1 98 V DC Input Voltage USBDP and USBDM 0 5 to Vcc 0 5 V DC Input Voltage XTIN 0 5 to 1 8V VCC PLL...

Page 69: ...Operating Supply Voltage 2 97 3 3 3 63 V VCC_PLL VCC_PLL Operating Supply Voltage 1 62 1 8 1 98 V Icc1 Operating Supply Current 48MHz 25 mA Normal Operation Icc2 Operating Supply Current 24MHz 16 mA L...

Page 70: ...0 8 2 5 V UVdif Differential Input Sensitivity 0 2 V UDrvZ Driver Output Impedance 3 6 9 Ohms Table 9 4 USB I O Pin USBDP USBDM Characteristics Parameter Description Minimum Typical Maximum Units Con...

Page 71: ...Embedded Dual USB Host Controller IC Version 1 6 Document No FT_000138 Clearance No FTDI 143 9 3 ESD and Latch up Specifications Description Specification Human Body Mode HBM TBD Machine mode MM TBD C...

Page 72: ...l The 5V0_SW power signal assumes proper switching and over current detection conform to the USB IF specifications for a USB host port The 120uF capacitor should be a low ESR type The value of the fer...

Page 73: ...profile for all packages can be viewed in Section 11 8 11 1 VNC2 Package Markings An example of the markings on each package are shown in Figure 11 1 The FTDI part number is too long for the 32 QFN pa...

Page 74: ...ional Limited Datasheet Vinculum II Embedded Dual USB Host Controller IC Version 1 6 Document No FT_000138 Clearance No FTDI 143 11 2 VNC2 LQFP 32 Package Dimensions FTDl XXXXXXXX YYWW VNC2 32L1A PIN...

Page 75: ...ernational Limited Datasheet Vinculum II Embedded Dual USB Host Controller IC Version 1 6 Document No FT_000138 Clearance No FTDI 143 11 3 VNC2 QFN 32 Package Dimensions 1 XXXXXXXX FTDl 1A YYWW VNC2 3...

Page 76: ...ersion 1 6 Document No FT_000138 Clearance No FTDI 143 11 4 VNC2 LQFP 48 Package Dimensions Pin 1 0 25 1 60 MAX 12 o 1o 1 4 0 05 0 2 Min 0 6 0 15 1 0 0 05 Min 0 15 Max 0 24 0 07 0 22 0 05 0 09 Min 0 2...

Page 77: ...tional Limited Datasheet Vinculum II Embedded Dual USB Host Controller IC Version 1 6 Document No FT_000138 Clearance No FTDI 143 11 5 VNC2 QFN 48 Package Dimensions 48 1 XXXXXXXXXX FTDl YYWW VNC2 48Q...

Page 78: ...Version 1 6 Document No FT_000138 Clearance No FTDI 143 11 6 VNC2 LQFP 64 Package Dimensions 10 10 12 12 0 25 1 60 MAX 12 o 1o 1 4 0 05 0 2 Mi n 0 6 0 15 1 0 0 05 Mi n 0 15 Ma x 0 5 FTDl XXXXXXXX VNC...

Page 79: ...mited Datasheet Vinculum II Embedded Dual USB Host Controller IC Version 1 6 Document No FT_000138 Clearance No FTDI 143 11 7 VNC2 QFN 64 Package Dimensions XXXXXXXXXX FTDl YYWW VNC2 64Q1A Figure 11 7...

Page 80: ...t Future Technology Devices International Limited Datasheet Vinculum II Embedded Dual USB Host Controller IC Version 1 6 Document No FT_000138 Clearance No FTDI 143 Figure 11 8 All packages Reflow Sol...

Page 81: ...onds 100 C 150 C 60 to 120 seconds Time Maintained Above Critical Temperature TL Temperature TL Time tL 217 C 60 to 150 seconds 183 C 60 to 150 seconds Peak Temperature Tp 260 C see Table 11 2 Time wi...

Page 82: ...595 E mail Sales cn sales ftdichip com E mail Support cn support ftdichip com E mail General Enquiries cn admin ftdichip com Web Site http ftdichip com Distributor and Sales Representatives Please vis...

Page 83: ...II IO_Mux Configuration Utility User Guide Application note AN_145 Vinculum II Toolchain Installation Guide Application note AN_151 Vinculum II User Guide VNC2 FTDI Web Page Vinculum II Web Page The...

Page 84: ...ut Output VNC1L Vinculum I VNC2 Vinculum II DMA Direct Memory Access IDE Integrated Development Environment BOMS Bulk Only Mass Storage UART Universal Asynchronous Receiver Transmitter SIE Serial Inte...

Page 85: ...and Status Fields 44 Table 6 7 SPI Command and Status Fields 49 Table 6 8 SPI Setup Bit Encoding 49 Table 6 9 SPI Slave Data Timing 50 Table 6 10 SPI Master Data Read Status Bit 51 Table 6 11 SPI Mast...

Page 86: ...UART Receive Waveform 36 Figure 6 2 UART Transmit Waveform 36 Figure 6 3 SPI CPOL CPHA Function 41 Figure 6 4 SPI Slave block diagram 41 Figure 6 5 Full Duplex Data Master Write 43 Figure 6 6 Full Dup...

Page 87: ...0138 Clearance No FTDI 143 Figure 11 1 Package Markings 73 Figure 11 2 Markings 32 QFN 73 Figure 11 3 LQFP 32 Package Dimensions 74 Figure 11 4 QFN 32 Package Dimensions 75 Figure 11 5 LQFP 48 Package...

Page 88: ...le 2010 09 09 1 2 Revised part numbers to Rev B in section 1 2 added notes to sections 3 12 and 5 default pin assignments 2010 10 07 1 3 Added USB transfer transaction combinations 2011 04 19 1 31 Tab...

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