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P5F111 User’s Manual
3.9 CHIPSET FEATURES SETUP
Selecting “CHIPSET FEATURES SETUP” on the main program screen
displays this menu:
Chipset Features Setup Screen
This screen controls the settings for the board’s chipset. All entries
related to the DRAM timing on the screen are automatically configured.
Do not make any change unless you are familiar with the chipset.
Bank 0/1 2/3 4/5 DRAM Timing.
This item allows you to select the
value in the field, depending on whether the board has paged
SDRAMs or EDO (extended data output) DRAMs. The choice:
SDRAM 10ns, SDRAM 8ns, Normal, Medium, Fast and Turbo.
SDRAM Cycle Length.
You can select CAS latency time in HCLKs
of 2/2 or 3/3. The system board designer should have set the values in
this field, depending on the DRAM installed. Do not change the val-
ues in this field unless you change specifications of the installed
DRAM or the installed CPU.
Chapter 3: BIOS Configuration
Current System Temp.
FAN1 Speed
Vcc3
+ 12V
- 5V
Vccp
+5V
: +
: +
: -
- 12V
: +
: +
: -
:
FAN2 Speed
:
:
Current System Temp.
FAN1 Speed
Vcc3
+ 12V
- 5V
Vccp
+5V
: +
: +
: -
- 12V
: +
: +
: -
:
FAN2 Speed
:
:
ROM PCI/ISA BIOS (2A5LHF2A)
CHIPSET FEATURES SETUP
AWARD SOFTWARE, INC.
Bank 0/1 DRAM Timing
SDRAM Cycle Length
System BIOS Cacheable
Memory Hole
DRAM Read Pipeline
: SDRAM 10ns
: 3
: 8M
: Enabled
Cache R/CPU W Pipeline
(Shift) F2: Color
PU/PD/+/-:Modify
ESC: Quit
F1: Help
F5: Old Values
F7: Load Setup Defaults
:Select Item
Cache Timing
: Fast
Video BIOS Cacheable
: Enabled
AGP Aperture Size
Frame Buffer Size
: Enabled
: Disabled
OnChip USB
: Enabled
USB Keyboard Support
: Disabled
: 64M
Bank 4/5 DRAM Timing
Bank 2/3 DRAM Timing
Sustained 3T Write
Init Display First
: SDRAM 10ns
: SDRAM 10ns
: AGP
: Enabled
: Disabled
OnChip Sound
OnChip Modem
Auto Detect DIMM/PCI Clk
Spread Spectrum
: Enabled
: Disabled
: Enabled
: Disabled
