manualshive.com logo in svg

Freescale Semiconductor TWR-P1025, Hardware User'S Manual, Page: 37 / 41

Share
Download
Freescale Semiconductor TWR-P1025 Hardware User'S Manual Download Page 37

Tower Elevator Connections

TWR-P1025 Hardware User Guide,  Rev. 0

Freescale Semiconductor

5

 

D16

GPIO18

C16

ETH_RXDV

ENET5_RX_DV

D17

GPIO19 / SDHC_D4

C17

GPIO27 / 

SDHC_D6

GPIO_EXPAND8

D18

GPIO20 / SDHC_D5

C18

GPIO28 / 

SDHC_D7

GPIO_EXPAND9

D19

ETH_TXD1

ENET5_TX

D1

C19

ETH_RXD1

ENET5_RXD1 (LWE1_b)

D20

ETH_TXD0

ENET5_TX

D0

C20

ETH_RXD0

ENET5_RXD0

D21

ULPI_NEXT / 

USB_HS_DM

GPIO_EXPA

ND0

C21

ULPI_DATA

0 / 

I2S1_MCLK

D22

ULPI_DIR / 

USB_HS_DP

C22

ULPI_DATA 

1 / 

I2S1_DOUT

_SCK

D23

UPLI_DATA5 / 

USB_HS_VBUS

CE_PB1

C23

ULPI_DATA

2 / 

I2S1_DOUT

_WS

D24

ULPI_DATA6 / 

USB_HS_ID

ENET5_RE

FCLK

C24

ULPI_DATA

3 / 

I2S1_DIN0

D25

ULPI_DATA7

C25

ULPI_DATA

4 / 

I2S1_DOUT

0

D26

GND

Ground

C26

GND

Ground

D27

LCD_HSYNC / 

LCD_P24

C27

AN11

D28

LCD_VSYNC / 

LCD_P25

C28

AN10

D29

AN13

C29

AN9

D30

AN12

C30

AN8

D31

GND

Ground

C31

GND

Ground

D32

LCD_CLK / LCD_P26

C32

GPIO29 / 

UART2_DC

D

SER3_CD

D33

TMR11

C33

TMR9

D34

TMR10

C34

TMR8

Table 6-2. TWR-P1025 Primary Connector Pinout (continued)

Pin#

Side B

Pin#

Side A

Summary of Contents for TWR-P1025

Page 1: ...TWR P1025 Tower Module Hardware User Guide TWR P1025HUG Rev 0 3 2012...

Page 2: ...n systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Freescale Semiconductor product...

Page 3: ...r 2 Power Requirements 2 1 Overview 2 1 Chapter 3 Hardware Description 3 1 P1025 Microprocessor 3 1 3 2 Clocking 3 2 3 3 System Power 3 5 3 4 Debug Interface 3 5 3 5 Accelerometer 3 5 3 6 Pushbutton a...

Page 4: ...ontents Paragraph Number Title Page Number Chapter 5 Input Output Connectors and Pin Usage Table 5 1 LED Usage 5 1 5 2 I O Connectors and Pin Usage Table 5 1 Chapter 6 Tower Elevator Connections 6 1 O...

Page 5: ...Freescale Tower System 1 1 1 2 Callouts on front side of the TWR P1025 1 3 1 3 Callouts on back side of the TWR P1025 1 3 2 1 Power Supply Barrel Connector J2 Polarity 2 1 3 1 TWR P1025 Block Diagram...

Page 6: ...4 3 3 P1025 DDR Clock PLL Ratio 3 4 3 4 CPU Speed Selection 3 5 3 5 eTSEC1 PHY Connectivity 3 6 3 6 eTSEC1 PHY Connectivity 3 7 3 7 I2C1 Connectivity 3 9 3 8 I2C2 Connectivity 3 9 3 9 DDR3 Signals 3...

Page 7: ...the QorIQ P1xxx family of microprocessor MPU devices The TWR P1025 features the QorIQ P1025 dual core processor based on the PowerPC e500 core architecture The TWR P1025 is available as a stand alone...

Page 8: ...n a 561 TEPBGA package operating up to 533 MHz P1025 JTAG CPLD JTAG Three axis accelerometer MMA8451Q Two 2 user controllable LEDs One 1 reset pushbutton switch Ten way DIP Switch for configuration mi...

Page 9: ...TWR P1025 Overview TWR P1025 Hardware User Guide Rev 0 Freescale Semiconductor 3 Figure 1 2 Callouts on front side of the TWR P1025 Figure 1 3 Callouts on back side of the TWR P1025...

Page 10: ...tart Guide or the interactive DVD contained in the TWR P1025 box for recommended get started steps 1 5 Reference Documents For more information on the QorIQ family Tower System and MPU Modules refer f...

Page 11: ...elevators and other TWR peripherals the TWR P1025 provides 5V and 3 3V supplies There are several expansion options on the board that allow external boards to interface to the TWR P1025 such as the m...

Page 12: ...equency of 533MHz It is intended to be used stand alone or in the Freescale Tower System Power is supplied through a 5V barrel connector Figure 3 1 shows a block diagram of the TWR P1025 The following...

Page 13: ...nd device support Enhanced host controller interface EHCI ULPI interface to PHY Enhanced secure digital host controller SD MMC Enhanced serial peripheral interface eSPI Integrated security engine Prot...

Page 14: ...roller complex clock In this case the DDR complex operates asynchronous with respect to the platform clock and runs at a fixed data rate of 667MTps The clocks for the PCI Express and SGMII interfaces...

Page 15: ...0 2 000 4 1 001 5 1 010 6 1 Table 3 2 P1025 e500 Core 0 1 to CCB Clock Ratio Selection Functional Signals Reset Configuration Name Value e500 Core CCB Clock Ratio LBCTL LALE LGPL2 LOE LFRE No Default...

Page 16: ...gh its second I2C interface at address 0x1C and the accelerometers INT1 signal routed to the P1025 IRQ0 3 6 Pushbutton and LEDs The TWR P1025 features one pushbutton switch connected to a reset circui...

Page 17: ...D03 AC22 Output TX data bit TXD3 37 TSEC1_TXD02 AE27 Output TX data bit TXD2 36 TSEC1_TXD01 AB23 Output TX data bit TXD1 35 TSEC1_TXD00 AD25 Output TX data bit TXD0 34 TSEC1_TX_EN AD22 Output TX data...

Page 18: ...TSEC3_TXD03 AE22 Output TX data bit TXD3 37 TSEC3_TXD02 AF24 Output TX data bit TXD2 36 TSEC3_TXD01 AG26 Output TX data bit TXD1 35 TSEC3_TXD00 AF21 Output TX data bit TXD0 34 TSEC3_TX_EN AD27 Output...

Page 19: ...odule to provide code storage for boot and application code Some of the connections are direct between the P1025 s GPCM controlled memory controller and the Flash device However the data bus is multip...

Page 20: ...to control the optional 50 MHz VXCO DNP by default and is also routed to the tower primary elevator 3 14 DDR3 512 MBytes of memory is connected to the P1025 32 bit DDR3 controller The 512 MByte compri...

Page 21: ...AS 47 Ohm to VTT Row Address Strobe Control MCKE0 CKE CKE 47 Ohm to VTT Clock Enable MCKE1 47 Ohm to VTT Clock Enable MCS0 CS CS 47 Ohm to VTT Chip Select MODT0 ODT ODT 47 Ohm to VTT On Die Terminatio...

Page 22: ...TIMING_CFG_1 0x6f6b4846 reg DDR_CONT_GROUP TIMING_CFG_1 0x5c5b6544 TIMING_CFG_2 reg DDR_CONT_GROUP TIMING_CFG_2 0x0fa8c8cf reg DDR_CONT_GROUP TIMING_CFG_2 0x0fa880de TIMING_CFG_3 reg DDR_CONT_GROUP T...

Page 23: ...RVAL 0x09480000 DDR_DATA_INIT reg DDR_CONT_GROUP DDR_DATA_INIT 0xdeadbeef DDR_SDRAM_CLK_CNTL reg DDR_CONT_GROUP DDR_SDRAM_CLK_CNTL 0x03000000 TIMING_CFG_4 reg DDR_CONT_GROUP TIMING_CFG_4 0x00220001 TI...

Page 24: ...ry elevator GPIO5 GPIO_EXPAND2 Primary elevator GPIO7 GPIO_EXPAND3 Primary elevator GPIO8 GPIO_EXPAND4 Primary elevator GPIO9 GPIO_EXPAND5 Primary elevator GPIO14 GPIO_EXPAND6 Primary elevator GPIO15...

Page 25: ...1025 Jumper Table Feature Settings OFF 1 ON 0 Comments S1 1 OFF ON Reserved S1 2 OFF ON PCIE_HOST_AGENT Selection P1025 is Host P1025 is Agent S1 3 OFF ON Reserved S1 4 OFF ON CFG_CPU0_1_BOOT Core0 bo...

Page 26: ...r S1 9 OFF ON ETH_TDM_SEL Ethernet1 clock routed to P1025 through CPLD TDM Clock routed to P1025 through CPLD S1 10 OFF ON PROFIBUS_MODE_SEL normal mode RTS inverted debug mode RTS connected to CTS Ta...

Page 27: ...r Activity Off for no Activity CPLD D2 Green User programmable User programmable CPLD D3 Green User programmable User programmable 3V3 Power D5 Green 3V3 Power ON 3V3 Power OFF P1025 ASLEEP D7 Green A...

Page 28: ...etect inverted polarity CD_COMMON CN1 10 3V3 GND CN1 11 Ground GND CN1 12 Ground GND CN1 13 Ground GND CN1 14 Ground Pushbuttons SW1 RESET BOARD RESET CPU JTAG COP CPU_TDO J3 1 Test Data In J3 2 CPU_T...

Page 29: ...ansion GND J4 1 Ground 3 3V J4 2 Power SER7_RXD0 J4 3 UCC7 RXD0 SER3_RXD0 J4 4 UCC3 RXD0 SER7_TXD0 J4 5 UCC7 TXD0 SER3_TXD0 J4 6 UCC3 RXD0 SER7_RTS_B J4 7 UCC7 RTS_B GND J4 8 Ground SER7_CTS_B J4 9 UC...

Page 30: ...588_ALARM_OUT2 Dual USB A1 J5 1 5V Out A2 J5 2 USB3_DN A3 J5 3 USB3_DP A4 J5 4 Ground B1 J5 5 5V Out B2 J5 6 USB4_DN B3 J5 7 USB4_DP B4 J5 8 Ground miniPCIe WAKE P2 1 Pull up to 3 3V 3 3V P2 2 Power R...

Page 31: ...Power GND P2 29 Ground SMBCLK P2 30 I2C_SCL PERTN0 P2 31 PCIE_TX0_N SMBDATA P2 32 I2C_SDA PERTP0 P2 33 PCIE_TX0_P GND P2 34 Ground GND P2 35 Ground USB_D P2 36 USB2_DM RSV P2 37 Reserved USB_D P2 38 U...

Page 32: ...tors and Pin Usage Table TWR P1025 Hardware User Guide Rev 0 6 Freescale Semiconductor RSV P2 51 Reserved 3 3V P2 52 Power Table 5 2 I O Connectors and Pin Usage Table continued Feature Connection Por...

Page 33: ...Table 15 provides the pinout for the Secondary Connector Table 6 1 TWR P1025 Primary Connector Pinout Pin Side B Pin Side A Name Usage Name Usage B1 5V 5 0V Power A1 5V 5 0V Power B2 GND Ground A2 GND...

Page 34: ..._D1 A22 SSI_BCLK TDMA_CLK B23 GPIO3 CE_PB1 A23 SSI_FS TDMA_SYNC B24 CLKIN0 ENET5_REF CLK A24 SSI_RXD TDMA_RXD B25 CLKOUT1 A25 SSI_TXD TDMA_TXD B26 GND Ground A26 GND Ground B27 AN7 A27 AN3 B28 AN6 A28...

Page 35: ...55 IRQ_H IRQ_H A55 USB0_DP B56 IRQ_G IRQ_G A56 USB0_ID B57 IRQ_F IRQ_F A57 USB0_VBUS B58 IRQ_E IRQ_E A58 TMR7 B59 IRQ_D IRQ_D A59 TMR6 B60 IRQ_C IRQ_C A60 TMR5 B61 IRQ_B IRQ_B A61 TMR4 B62 IRQ_A IRQ_A...

Page 36: ...3V 3 3V Power A82 3 3V 3 3V Power Table 6 2 TWR P1025 Primary Connector Pinout Pin Side B Pin Side A Name Usage Name Usage D1 5V 5 0VPower C1 5V 5 0V Power D2 GND Ground C2 GND Ground D3 3 3V 3 3V Pow...

Page 37: ...21 ULPI_DATA 0 I2S1_MCLK D22 ULPI_DIR USB_HS_DP C22 ULPI_DATA 1 I2S1_DOUT _SCK D23 UPLI_DATA5 USB_HS_VBUS CE_PB1 C23 ULPI_DATA 2 I2S1_DOUT _WS D24 ULPI_DATA6 USB_HS_ID ENET5_RE FCLK C24 ULPI_DATA 3 I2...

Page 38: ...D45 LCD_D0 LCD_P0 SPI0_MOSI C45 UART3_RX D TSI4 SER7_RXD0 D46 LCD_D1 LCD_P1 ELEV_SPI0 _CS0_b C46 UART3_TX D TSI5 SER7_TXD0 D47 LCD_D2 LCD_P2 ELEV_SPI0 _CS1_b C47 UART3_RT S CAN3_RX SER7_RTS D48 LCD_D...

Page 39: ..._ RX1_N C64 LCD_D17 LCD_P17 SD_GND SD_GND D65 GND Ground C65 GND Ground D66 EBI_AD20 LCD_P42 SD_GND SD_GND C66 EBI_BE_32 _24_b LCD_P28 SD_TX_0 ELEV_SD_TX1_P D67 EBI_AD21 LCD_P43 SD_GND SD_GND C67 EBI_...

Page 40: ...SD_GND SD_GND C75 EBI_CS4_b LCD_P37 SD_TXb_2 ELEV_SD_TX3_N D76 EBI_AD30 LCD_P52 SD_RX_3 C76 EBI_CS3_b LCD_P38 SD_GND SD_GND D77 EBI_AD31 LCD_P53 SD_RXb_3 C77 EBI_CS2_b LCD_P39 SD_GND SD_GND D78 LCD_D...

Page 41: ...conductor 1 Appendix A Revision History This appendix provides a list of the major differences between current TWR P1025 hardware user guide and its previous revisions A 1 Version Number 0 This is ini...

Reviews:

No comments