Freescale Semiconductor TWR-P1025, Hardware User'S Manual, Page: 22 / 41

Hardware Description
TWR-P1025 Hardware User Guide, Rev. 0
Freescale Semiconductor 11
The codewarrior initialization for the DDR3 controller are:
# DDR Controllers Setup
# DDR_SDRAM_CFG
reg ${DDR_CONT_GROUP}DDR_SDRAM_CFG = 0x470C0000
#CS0_BNDS
reg ${DDR_CONT_GROUP}CS0_BNDS = 0x0000001f
#CS1_BNDS
reg ${DDR_CONT_GROUP}CS1_BNDS = 0x00000000
#CS0_CNFG
reg ${DDR_CONT_GROUP}CS0_CONFIG = 0x80014202
#CS1_CNFG
reg ${DDR_CONT_GROUP}CS1_CONFIG = 0x00000000
# TIMING_CFG_0
#reg ${DDR_CONT_GROUP}TIMING_CFG_0 = 0x00330004
reg ${DDR_CONT_GROUP}TIMING_CFG_0 = 0x00220004
# TIMING_CFG_1
#reg ${DDR_CONT_GROUP}TIMING_CFG_1 = 0x6f6b4846
reg ${DDR_CONT_GROUP}TIMING_CFG_1 = 0x5c5b6544
# TIMING_CFG_2
#reg ${DDR_CONT_GROUP}TIMING_CFG_2 = 0x0fa8c8cf
reg ${DDR_CONT_GROUP}TIMING_CFG_2 = 0x0fa880de
# TIMING_CFG_3
#reg ${DDR_CONT_GROUP}TIMING_CFG_3 = 0x00020000
reg ${DDR_CONT_GROUP}TIMING_CFG_3 = 0x00020000
# DDR_SDRAM_CFG_2
#reg ${DDR_CONT_GROUP}DDR_SDRAM_CFG_2 = 0x04401040
reg ${DDR_CONT_GROUP}DDR_SDRAM_CFG_2 = 0x04401050
Clocks MCK0+/- MCK0+/- MCK0+/- Clock/compleme
nt
MCK1+/- NC NC
Misc ZQ 240 Ohm to
VSSQ (GND)
ZQ calibration
MDIC0 Half Strength
mode 40ohm to
GND
Driver calibration
MDIC1 Half Strength
mode 40ohm to
GVDD
Driver calibration
RESET RESET 1.5V Tolerant Device Reset
Table 3-9. DDR3 Signals (continued)
Signal Group P1 Signal
DDR3 Device 1
Signal
DDR3 Device 2
Signal
Termination/
Notes
Description