Hardware Description
TWR-P1025 Hardware User Guide, Rev. 0
2
Freescale Semiconductor
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Dual high-performance 32-bit cores, built on Power Architecture® technology:
— 32-bit e500v2 PowerPC core
— 36-bit physical addressing
— Double-precision floating-point support
— 32 Kbyte L1 instruction cache and 32 Kbyte L1 data cache for each core
— 400 MHz to 533 MHz clock frequency
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256 Kbyte L2 cache with ECC. Also configurable as SRAM and stashing memory.
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Three 10/100/1000 Mbps enhanced three-speed Ethernet controllers (eTSECs)
— TCP/IP acceleration, quality of service, and classification capabilities
— IEEE® 1588 support
— Lossless flow control
— MII, RMII, RGMII, SGMII
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High-speed interfaces supporting various multiplexing options:
— Four SerDes upto 2.5 GHz/lane multiplexed across controllers
— Two PCI Express interfaces
— Two SGMII interfaces
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High-speed USB controller (USB 2.0)
— Host and device support
— Enhanced host controller interface (EHCI)
— ULPI interface to PHY
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Enhanced secure digital host controller (SD/MMC)
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Enhanced serial peripheral interface (eSPI)
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Integrated security engine
— Protocol support includes ARC4, 3DES, AES, RSA/ECC, RNG, single-pass SSL/TLS
— XOR acceleration
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32-bit DDR3 SDRAM memory controller with ECC support
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Programmable interrupt controller (PIC) compliant with OpenPIC standard
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One four-channel DMA controller
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Two I2C controllers, DUART, timers
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Enhanced local bus controller (eLBC)
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QUICC Engine block
3.2
Clocking
The P1025 takes a single input clock, SYSCLK, as its primary clock source for the e500 cores and all of
the devices and interfaces that operate synchronously with the core. As shown in
Figure 3-1
, the SYSCLK
input (frequency) is multiplied up using a phase lock loop (PLL) to create the core complex bus (CCB)
clock (also called the platform clock). The CCB clock is used by virtually all of the synchronous system
logic, including the L2 cache, and other internal blocks such as the DMA and interrupt controller. The CCB