Chip Configuration Module
Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0
Freescale Semiconductor
20-11
20.2.2.8
ONCE Debug and Burst Control Register (ODBC)
The ODBC Control Register is shown in
PSE[4]
Pin Switch Control bits for ESAI Pin FST and ESAI_2 Pin FST
0 Pin Switch Disabled
1 Pin Switch Enabled
PSE[3]
Pin Switch Control bits for ESAI Pin SCKT and ESAI_2 Pin SCKT
0 Pin Switch Disabled
1 Pin Switch Enabled
PSE[2]
Pin Switch Control bits for ESAI Pin HCKR and ESAI_2 Pin HCKR
0 Pin Switch Disabled
1 Pin Switch Enabled
PSE[1]
Pin Switch Control bits for ESAI Pin FSR and ESAI_2 Pin FSR
0 Pin Switch Disabled
1 Pin Switch Enabled
PSE[0]
Pin Switch Control bits for ESAI Pin SCKR and ESAI_2 Pin SCKR
0 Pin Switch Disabled
1 Pin Switch Enabled
Note:
See the product pin-out information for using these bits to switch the available pins on the DSP56724 or DSP56725.
Address
Y:FFFFE2
Access: User Read/Write
23
22
21
20
19
18
17
16
15
14
13
12
R
ODRE1 ODRE0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
11
10
9
8
7
6
5
4
3
2
1
0
R
IWB3
IWB2
IWB1
IWB0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
Figure 20-8. ONCE Debug and Burst Control Register (ODBC)
Table 20-10. EPSC Field Descriptions (Continued)
Field Description