Freescale Semiconductor PowerQUICC III MPC8541E, Manuallines

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7 Revision History
Table 11 provides a revision history for this application note.
Table 11. Document Revision History
Rev.
Number
Date Changes
5 05/2013 Changed
“......minimum of 100ms” to “......minimum of 100
μ
s” in Section 5,
“Power-On Reset/Reset Configurations
4 06/2010 Added a NOTE to Section 2.3, “Power Sequencing .”
3 11/2006 Made updates to bring this application note in line with the hardware specification updates. Changes
are summarized as follows:
•
Section 4.1, “TRST , “ replaced Figure 3 and added section on Section 4.2, “Termination of Unused
Signals .
• Modified Section 2.3, “Power Sequencing .”
• Modified signal names in Table 6 .
2 6/2006 Updates are as follows:
• Modified note in
Section 6.3, “DDR SDRAM ” to clarify that while MSYNC_IN mube connected to
MSYNC_OUT, the length of this trace need not be matched to anything because the operating
mode is Source Synchrounous mode.
• Section 2.2, removed Table 2.
• Section 3.1. Removed the current Figure 2 and replaced it with Figure 4-6 from the MPC8555E
reference manual.
• Section 6.3. Added a bullet to the note section.
• Section 6.5.1. Added the following line: “A weak pull-up (2–10 K
Ω
) is required on the LGTA signal.
• Removed and replaced Figure 3 with the MPC8560EC hardware specification Figure 59.
0.1 12/2004 Deleted sentence from Section 6.5.1
0 10/2004 Initial Release