Freescale Semiconductor PowerQUICC III MPC8541E, Manuallines

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PowerQUICC III MPC8555E and MPC8541E Bring-Up Guidelines, Rev. 5
12 Freescale Semiconductor
Debug
The COP header is fully described in Figure 4 and Table 6 .
Figure 4. COP Header Pinout
4.2 Termination of Unused Signals
If the JTAG interface and COP header are not used, Freescale recommends the following connections:
• TRST should be tied to HRESET through a 0 k
Ω
isolation resistor so that it is asserted when the
system reset signal (HRESET) is asserted, ensuring that the JTAG scan chain is initialized during
Table 6. COP Header Definition
Header Position Name Description
1 COP_TDO Test Data Output
2 NC
3 COP_TDI Test Data Input
4 TRST Test Reset
5 Not implemented. Connect to OV
DD
with a 10K
Ω
resistor.
6 COP_VDDS VDD Sense
7 COP_TCK Test Clock
8 COP_CHKSTP_IN Checkstop In
9 COP_TMS Test Mode Select
10 NC
11 COP_SREST Soft Reset
12 NC
13 COP_HRESET Hard Reset
14 KEY
15 COP_CHKSTP Checkstop Out
16 GND Ground
3
13
9
5
1
6
10
15
11
7
16
12
8
4
KEY
No pin
1 2