PowerQUICC III MPC8555E and MPC8541E Bring-Up Guidelines, Rev. 5
Freescale Semiconductor
13
Power-On Reset/Reset Configurations
the power-on reset flow. Freescale recommends that the COP header be designed into the system
as shown in
. If this is not possible, the isolation resistor allows future access to TRST if a
JTAG interface needs to be wired onto the system in future debug situations.
•
Tie TCK to OV
DD
through a 10 k
Ω
resistor to prevent TCK from changing state and reading
incorrect data into the device.
•
No connection is required for TDI, TMS, or TDO.
4.3
Recommended Test Points
For easier debug, it is recommended that the test points on the board include the following pins:
•
CLK_OUT (This helps to verify the CCB clock)
•
TRIG_OUT (This helps to verify the end of the reset sequence)
•
ASLEEP (This helps to verify the end of the reset sequence)
•
SENSEVDD (This helps to verify power plane V
DD
)
•
SENSEVSS (This helps to verify ground plane V
SS
)
•
HRESET_REQ (This helps to verify proper boot sequencer functions and reset requests)
5
Power-On Reset/Reset Configurations
Various device functions are initialized by sampling certain signals during the assertion of HRESET. These
inputs are either pulled high or low during this period. While these pins are generally output pins during
normal operation, they are treated as inputs while HRESET is asserted. HRESET must be asserted for a
minimum of 100
μ
s. When HRESET negates, the configuration pins are sampled and latched into registers
and the pins then take on their normal output circuit characteristic from an input circuit during HRESET.
All configuration pins have an internally gated 20 K
Ω
pull-up resistor, enabled only during HRESET. For
configurations in which the default state is desired, no external pull-up is required. Otherwise, a 4.7 K
Ω
pull-down resistor is recommended to pull the configuration pin to a valid logic-low level. If a
configuration pin has no default, 4.7 K
Ω
pull-up or pull-down resistors are recommended for appropriate
summarizes all the power-on reset configurations possible on the device.
Table 7. Power-On Reset Configurations
Type of Configuration
Configuration Pins
Default State
CCB Clock PLL Ratio
LA[28:31]
No default state;
pins must be configured at HRESET
e500 Core PLL Ratio
LALE, LGPL2
No default state;
pins must be configured at HRESET
Boot ROM Location
LGPL0, LGPL1,
LWE[3]
Local Bus GPCM, 32-bit ROM
Host/Agent
LWE[2]
Device acts as the host on processor for PCI 1
CPU Boot
LA27
The core is allowed to boot without waiting for configuration from any
external master
Boot Sequencer
LGPL3, LGPL5
Boot sequencer is disabled
TSEC Width
EC_MDC
Ethernet interfaces operate in standard GMII or TBI modes
