Freescale Semiconductor MSC8144E, Reference Manual

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GPIO Programming Model
MSC8144E Reference Manual, Rev. 3
Freescale Semiconductor 22-7
22.5 GPIO Programming Model
The GPIO registers reside on a 256 KB address space. The GPIO block has five
memory-mapped, read/write, 32-bit control registers. This section describes these registers in
detail. Following is a list of the registers:
„
Pin Open-Drain Register (PODR), page 22-7
„
Pin Data Register (PDAT), page 22-8
„
Pin Data Direction Registers (PDIR), page 22-9
„
Pin Assignment Register (PAR), page 22-9
„
Pin Special Options Registers (PSOR), page 22-10
Note: The GPIO registers use a base address of: 0xFFF27200.
22.5.1 Pin Open-Drain Register (PODR)
PODR indicates a normal or active low open drain mode for wired-OR configuration of the
outputs.
When a GPIO port has Ethernet functionality (see Table 22-1), PODRx does not influence its
driving mode.
PODR Pin Open-Drain Register Offset 0x00
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OD31 OD30 OD29 OD28 OD27 OD26 OD25 OD24 OD23 OD22 OD21 OD20 OD19 OD18 OD17 OD16
Type R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OD15 OD14 OD13 OD12 OD11 OD10 OD9 OD8 OD7 OD6 OD5 OD4 OD3 OD2 OD1 OD0
Type R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 22-3. PODR Bit Descriptions
Name Reset Description Settings
OD[31–0]
31–0
0 Open-Drain Configuration
Determines whether the corresponding port is
actively driven as an output or is an open-drain
driver. As an open-drain driver, the port is
driven active-low. Otherwise, it is tri-stated
(high impedance). 0 The I/O port is actively driven as an output.
1 The I/O port is an open-drain driver.