Freescale Semiconductor MSC8144E, Reference Manual

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GPIO Programming Model
MSC8144E Reference Manual, Rev. 3
Freescale Semiconductor 22-9
22.5.3 Pin Data Direction Register (PDIR)
PDIR is cleared at system reset.
22.5.4 Pin Assignment Register (PAR)
PAR is cleared at system reset.
PDIR Pin Data Direction Register Offset 0x10
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DR31 DR30 DR29 DR28 DR27 DR26 DR25 DR24 DR23 DR22 DR21 DR20 DR19 DR18 DR17 DR16
Type R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DR15 DR14 DR13 DR12 DR11 DR10 DR9 DR8 DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0
Type R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 22-4. PDIR Bit Descriptions
Name Reset Description Settings
DR
0–31
0
Direction
Indicates whether a port is an input or an
output. 0 The corresponding port is an input.
1 The corresponding port is an output.
Note: This register sets the direction of the selected port, but you must enable the port using the General Input Enable
Register (GIER) to use it. See Section 8.2.9, GPIO Input Enable Register (GIER), on page 8-11 for details.
PAR Pin Assignment Register Offset 0x18
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DD31 DD30 DD29 DD28 DD27 DD26 DD25 DD24 DD23 DD22 DD21 DD20 DD19 DD18 DD17 DD16
Type R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DD15 DD14 DD13 DD12 DD11 DD10 DD9 DD8 DD7 DD6 DD5 DD4 DD3 DD2 DD1 DD0
Type R/W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 22-5. PAR Bit Descriptions
Name Reset Description Bit Settings
DD[31–0]
0–31
0 Dedicated Enable
Indicates whether a pin is a GPIO or a dedicated peripheral port.
As a dedicated peripheral function, the pin is used by the internal
module. The internal peripheral function to which it is dedicated
can be determined by other bits, such as those in the PSOR.
When a GPIO port has Ethernet functionality (see Table 22-1), its
PAR bit should be set to 0. 0 GPIO. The peripheral
functions of the pin are not
used.
1 Dedicated peripheral
function.