Freescale Semiconductor MPC5565, Reference Manual

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Enhanced Modular Input/Output Subsystem (eMIOS)
MPC5565 Microcontroller Reference Manual, Rev. 1.0
Freescale Semiconductor 16-29
16.4.4.4.1 General Purpose Input/Output Mode (GPIO)
The following table lists the general purpose input/output mode settings:
In GPIO mode, all input capture and output compare functions of the UC are disabled, the internal counter
(EMIOS_CCNTRn register) is cleared and disabled. All control bits remain accessible. To prepare the UC
for a new operating mode, writing to registers EMIOS_CADR
n or EMIOS_CBDR n stores the same value
in registers A1/A2 or B1/B2, respectively.
MODE[6] bit selects between input (MODE[6] = 0) and output (MODE[6] = 1) modes.
It is required that when changing MODE[0:6], the application software goes to GPIO mode first to reset
the UC’s internal functions properly. Failure to do this can lead to invalid and unexpected output compares
and input capture results, or can cause the FLAGs to be set incorrectly.
In GPIO input mode, the FLAG generation is determined according to EDPOL and EDSEL bits and the
input pin status can be determined by reading the UCIN bit.
In GPIO output mode, the unified channel is used as a single output port pin and the value of the EDPOL
bit is permanently transferred to the output flip-flop.
NOTE
The GPIO modes provided in the eMIOS are particularly useful as interim
modes when certain other eMIOS modes are being dynamically configured
and enabled or disabled during the execution of the application. For normal
GPIO function on the eMIOS pins, it is recommended that the SIU be used
to configure those pins as system GPIO. See
Section 6.2.1.3,
“General-Purpose I/O (GPIO[0:213]) ” pins.
16.4.4.4.2 Single-action Input Capture Mode (SAIC)
The following table lists the single action input capture mode settings:
In SAIC mode, when a triggering event occurs on the input pin, the value on the selected time base is
captured into register A2. At the same time, the FLAG bit is set to indicate that an input capture has
occurred. Register EMIOS_CADR
n returns the value of register A2.
The input capture is triggered by a rising, falling or either edges in the input pin, as configured by EDPOL
and EDSEL bits in EMIOS_CCR
n
.
Table 16-14. GPIO Operating Mode
MODE[0:6] Unified Channel GPIO Operating Mode
0b0000000 General purpose input/output mode (input)
0b0000001 General purpose input/output mode (output)
Table 16-15. SAIC Operating Mode
MODE[0:6] Unified Channel SAIC
Operating
Mode
0b0000010 Single action input capture mode